nuvoTon
NUC1262AE
2024.05.01
NUC1262AE SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0x20
registers
n
0x100
0x4
registers
n
0x74
0x8
registers
n
0x80
0x20
registers
n
ADCHER
ADC_ADCHER
ADC Channel Enable Register
0x84
-1
read-write
n
0x0
0x0
CHEN
Analog Input Channel Enable Control
Set ADC_ADCHER[7:0] bits to enable the corresponding analog input channel 7 ~ 0. If DIFFEN (ADC_ADCR[10]) bit is set to 1, only the even number channel needs to be enabled.
Besides, setting ADC_ADCHER[29] to ADC_ADCHER[30] bits will enable internal channel for band-gap voltage and temperature sensor respectively. Other bits are reserved.
Note 1: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300 KSPS.
Note 2: If the internal channel for temperature sensor (CHEN[30]) is active, the maximum sampling rate will be 300 KSPS.
0
32
read-write
0
Channel Disabled
0
1
Channel Enabled
1
ADCMPR0
ADC_ADCMPR0
ADC Compare Register 0
0x88
-1
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection
3
5
read-write
0
Channel 0 conversion result is selected to be compared
#00000
1
Channel 1 conversion result is selected to be compared
#00001
2
Channel 2 conversion result is selected to be compared
#00010
3
Channel 3 conversion result is selected to be compared
#00011
4
Channel 4 conversion result is selected to be compared
#00100
5
Channel 5 conversion result is selected to be compared
#00101
6
Channel 6 conversion result is selected to be compared
#00110
7
Channel 7 conversion result is selected to be compared
#00111
29
Band-gap voltage conversion result is selected to be compared
#11101
30
Temperature sensor conversion result is selected to be compared
#11110
CMPCOND
Compare Condition
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one
#1
CMPD
Comparison Data
The 12-bit data is used to compare with conversion result of specified channel.
Note: CMPD bits should be filled in unsigned format (straight binary format).
16
12
read-write
CMPEN
Compare Enable Bit
Set this bit to 1 to enable ADC controller to compare CMPD with specified channel conversion result when converted data is loaded into ADC_ADDRx register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable Bit
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count
8
4
read-write
CMPWEN
Compare Window Mode Enable Bit
Note: This bit is only presented in ADC_ADCMPR0 register.
15
1
read-write
0
Compare Window Mode Disabled
#0
1
Compare Window Mode Enabled
#1
ADCMPR1
ADC_ADCMPR1
ADC Compare Register 1
0x8C
-1
read-write
n
0x0
0x0
ADCR
ADC_ADCR
ADC Control Register
0x80
-1
read-write
n
0x0
0x0
ADEN
A/D Converter Enable Bit
Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
0
1
read-write
0
A/D converter Disabled
#0
1
A/D converter Enabled
#1
ADIE
A/D Interrupt Enable Bit
A/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADMD
A/D Converter Operation Mode Control
Note 1: When changing the operation mode, software should clear ADST bit first.
Note 2: In Burst mode, the A/D result data is always at ADC Data Register 0.
2
2
read-write
0
Single conversion
#00
1
Burst conversion
#01
2
Single-cycle Scan
#10
3
Continuous Scan
#11
ADST
A/D Conversion Start
ADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
11
1
read-write
0
Conversion stops and A/D converter enters idle state
#0
1
Conversion starts
#1
DIFFEN
Differential Input Mode Control
Note 1: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADC_ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
Differential Input Mode Output Format
If user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADC_ADDRx registers with unsigned format (straight binary format)
#0
1
A/D Conversion result will be filled in RSLT at ADC_ADDRx registers with 2's complement format
#1
PTEN
PDMA Transfer Enable Bit
When A/D conversion is completed, the converted data is loaded into ADC_ADDR0~7, ADC_ADDR29~ADC_ADDR30 registers. Software can enable this bit to generate a PDMA data transfer request.
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADC_ADDR0~7, ADC_ADDR29~ADC_ADDR30 Enabled
#1
SMPTSEL
ADC Internal Sampling Time Selection
16
3
read-write
0
4 ADC clock for sampling 16 ADC clock for complete conversion
#000
1
5 ADC clock for sampling 17 ADC clock for complete conversion
#001
2
6 ADC clock for sampling 18 ADC clock for complete conversion
#010
3
7 ADC clock for sampling 19 ADC clock for complete conversion
#011
4
8 ADC clock for sampling 20 ADC clock for complete conversion
#100
5
9 ADC clock for sampling 21 ADC clock for complete conversion
#101
6
10 ADC clock for sampling 22 ADC clock for complete conversion
#110
7
11 ADC clock for sampling 23 ADC clock for complete conversion
#111
TRGCOND
External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger. If edge trigger condition is selected, the STADC pin must be kept original state at least 4 PCLKs, and the state after edge transition also must be kept at least 4 PCLKs.
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
External Trigger Enable Bit
Enable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.
Note: The ADC external trigger function is only supported in Single-cycle Scan mode.
8
1
read-write
0
External trigger Disabled
#0
1
External trigger Enabled
#1
TRGS
Hardware Trigger Source
Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
1
Timer0 ~ Timer3 overflow pulse trigger
#01
2
Reserved.
#10
3
A/D conversion is started by BPWM trigger
#11
ADDR0
ADC_ADDR0
ADC Data Register 0
0x0
-1
read-only
n
0x0
0x0
OVERRUN
Overrun Flag (Read Only)
If converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read.
16
1
read-only
0
Data in RSLT bits is not overwritten
#0
1
Data in RSLT bits is overwritten
#1
RSLT
A/D Conversion Result (Read Only)
This field contains conversion result of ADC.
0
16
read-only
VALID
Valid Flag (Read Only)
This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read.
17
1
read-only
0
Data in RSLT bits is not valid
#0
1
Data in RSLT bits is valid
#1
ADDR1
ADC_ADDR1
ADC Data Register 1
0x4
-1
read-write
n
0x0
0x0
ADDR2
ADC_ADDR2
ADC Data Register 2
0x8
-1
read-write
n
0x0
0x0
ADDR29
ADC_ADDR29
ADC Data Register 29
0x74
-1
read-write
n
0x0
0x0
ADDR3
ADC_ADDR3
ADC Data Register 3
0xC
-1
read-write
n
0x0
0x0
ADDR30
ADC_ADDR30
ADC Data Register 30
0x78
-1
read-write
n
0x0
0x0
ADDR4
ADC_ADDR4
ADC Data Register 4
0x10
-1
read-write
n
0x0
0x0
ADDR5
ADC_ADDR5
ADC Data Register 5
0x14
-1
read-write
n
0x0
0x0
ADDR6
ADC_ADDR6
ADC Data Register 6
0x18
-1
read-write
n
0x0
0x0
ADDR7
ADC_ADDR7
ADC Data Register 7
0x1C
-1
read-write
n
0x0
0x0
ADPDMA
ADC_ADPDMA
ADC PDMA Current Transfer Data Register
0x100
-1
read-only
n
0x0
0x0
CURDAT
ADC PDMA Current Transfer Data Register (Read Only)
When PDMA transferring, reading this register can monitor current PDMA transfer data.
The current PDMA transfer data could be the content of ADC_ADDR0 ~ ADC_ADDR7 and ADC_ADDR29 ~ ADC_ADDR30 registers.
0
18
read-only
ADSR0
ADC_ADSR0
ADC Status Register0
0x90
-1
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag
A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.
ADF bit is set to 1 at the following three conditions:
When A/D conversion ends in Single mode.
When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.
When more than or equal to 9 data in FIFO in Burst mode.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)
This bit is a mirror of ADST bit in ADC_ADCR register.
7
1
read-only
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel (Read Only)
27
5
read-only
CMPF0
Compare Flag 0
When the A/D conversion result of the selected channel meets setting condition in ADC_ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
1
1
read-write
0
Conversion result in ADC_ADDRx did not meet ADC_ADCMPR0 setting
#0
1
Conversion result in ADC_ADDRx met ADC_ADCMPR0 setting
#1
CMPF1
Compare Flag 1
When the A/D conversion result of the selected channel meets setting condition in ADC_ADCMPR1 register then this bit is set to 1 it is cleared by writing 1 to it
2
1
read-write
0
Conversion result in ADC_ADDRx did not meet ADC_ADCMPR1 setting
#0
1
Conversion result in ADC_ADDRx met ADC_ADCMPR1 setting
#1
OVERRUNF
Overrun Flag (Read Only)
If any of OVERRUN (ADC_ADDRx[16]) is set, this flag will be set to 1.
Note: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
16
1
read-only
VALIDF
Data Valid Flag (Read Only)
If any of VALID (ADC_ADDRx[17]) is set, this flag will be set to 1.
Note: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
8
1
read-only
ADSR1
ADC_ADSR1
ADC Status Register1
0x94
-1
read-only
n
0x0
0x0
VALID
Data Valid Flag (Read Only)
VALID[30:29], VALID[7:0] are the mirror of the VALID bits in ADC_ADDR30[17] ~ ADC_ADDR29[17], ADC_ADDR7[17]~ ADC_ADDR0[17]. The other bits are reserved.
Note: When ADC is in burst mode and any conversion result is valid, VALID[30:29], VALID[7:0] will be set to 1.
0
32
read-only
ADSR2
ADC_ADSR2
ADC Status Register2
0x98
-1
read-only
n
0x0
0x0
OVERRUN
Overrun Flag (Read Only)
OVERRUN[30:29], VALID[7:0] are the mirror of the OVERRUN bit in ADC_ADDR30[16] ~ADC_ADDR29[16], ADC_ADDR7[16] ~ ADC_ADDR0[16]. The other bits are reserved.
Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[30:29], OVERRUN[7:0] will be set to 1.
0
32
read-only
ADTDCR
ADC_ADTDCR
ADC Trigger Delay Control Register
0x9C
-1
read-write
n
0x0
0x0
PTDT
BPWM Trigger Delay Time
Set this field will delay ADC start conversion time after BPWM trigger.
BPWM trigger delay time is (4 * PTDT) * system clock
0
8
read-write
BPWM0
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
-1
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH0 Trigger ADC function Disabled
#0
1
BPWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH1 Trigger ADC function Disabled
#0
1
BPWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
BPWM_CH2 Trigger ADC function Disabled
#0
1
BPWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
BPWM_CH3 Trigger ADC function Disabled
#0
1
BPWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select
Others reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select
Others reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
-1
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH4 Trigger ADC function Disabled
#0
1
BPWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH5 Trigger ADC function Disabled
#0
1
BPWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
-1
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 3
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)
Used as CMPDAT active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
-1
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
-1
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
-1
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
-1
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
-1
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register
CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
-1
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)
Monitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down counting
#0
1
Counter is UP counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit
Note: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
-1
read-write
n
0x0
0x0
PERIOD
BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
-1
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit
When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from BPWM0
#00
1
Synchronous start source come from BPWM1
#01
2
Synchronous start source come from BPWM2
#10
3
Synchronous start source come from BPWM3
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
-1
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit (Write Only)
BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.
Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
-1
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
CNTMAXF0
Time-base Counter 0 Equal to 0xFFFF Latched Flag
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
BPWM1
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
-1
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH0 Trigger ADC function Disabled
#0
1
BPWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH1 Trigger ADC function Disabled
#0
1
BPWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
BPWM_CH2 Trigger ADC function Disabled
#0
1
BPWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
BPWM_CH3 Trigger ADC function Disabled
#0
1
BPWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select
Others reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select
Others reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
-1
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH4 Trigger ADC function Disabled
#0
1
BPWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH5 Trigger ADC function Disabled
#0
1
BPWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
-1
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 3
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)
Used as CMPDAT active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
-1
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
-1
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
-1
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
-1
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
-1
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register
CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
-1
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)
Monitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down counting
#0
1
Counter is UP counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit
Note: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
-1
read-write
n
0x0
0x0
PERIOD
BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
-1
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit
When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from BPWM0
#00
1
Synchronous start source come from BPWM1
#01
2
Synchronous start source come from BPWM2
#10
3
Synchronous start source come from BPWM3
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
-1
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit (Write Only)
BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.
Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
-1
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
CNTMAXF0
Time-base Counter 0 Equal to 0xFFFF Latched Flag
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
BPWM2
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
-1
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH0 Trigger ADC function Disabled
#0
1
BPWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH1 Trigger ADC function Disabled
#0
1
BPWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
BPWM_CH2 Trigger ADC function Disabled
#0
1
BPWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
BPWM_CH3 Trigger ADC function Disabled
#0
1
BPWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select
Others reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select
Others reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
-1
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH4 Trigger ADC function Disabled
#0
1
BPWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH5 Trigger ADC function Disabled
#0
1
BPWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
-1
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 3
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)
Used as CMPDAT active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
-1
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
-1
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
-1
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
-1
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
-1
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register
CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
-1
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)
Monitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down counting
#0
1
Counter is UP counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit
Note: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
-1
read-write
n
0x0
0x0
PERIOD
BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
-1
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit
When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from BPWM0
#00
1
Synchronous start source come from BPWM1
#01
2
Synchronous start source come from BPWM2
#10
3
Synchronous start source come from BPWM3
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
-1
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit (Write Only)
BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.
Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
-1
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
CNTMAXF0
Time-base Counter 0 Equal to 0xFFFF Latched Flag
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
BPWM3
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
-1
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH0 Trigger ADC function Disabled
#0
1
BPWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH1 Trigger ADC function Disabled
#0
1
BPWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
BPWM_CH2 Trigger ADC function Disabled
#0
1
BPWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
BPWM_CH3 Trigger ADC function Disabled
#0
1
BPWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count compared point
#0011
4
BPWM_CH0 down-count compared point
#0100
8
BPWM_CH1 up-count compared point
#1000
9
BPWM_CH1 down-count compared point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select
Others reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select
Others reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count compared point
#0011
4
BPWM_CH2 down-count compared point
#0100
8
BPWM_CH3 up-count compared point
#1000
9
BPWM_CH3 down-count compared point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
-1
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH4 Trigger ADC function Disabled
#0
1
BPWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH5 Trigger ADC function Disabled
#0
1
BPWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count compared point
#0011
4
BPWM_CH4 down-count compared point
#0100
8
BPWM_CH5 up-count compared point
#1000
9
BPWM_CH5 down-count compared point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. BPWM_RCAPDATn/BPWM_FCAPDATn register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)
Each bit controls the corresponding BPWM channel n.
This flag indicates if falling latch happened when the corresponding CAPFIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)
Each bit n controls the corresponding BPWM channel n.
This flag indicates if rising latch happened when the corresponding CAPRIF is 1.
Note: This bit will be cleared automatically when user clears corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
-1
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 3
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)
Used as CMPDAT active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
-1
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
-1
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
-1
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
-1
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
-1
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register
CMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
-1
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)
Monitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down counting
#0
1
Counter is UP counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will be loaded to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit
Note: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag
Each bit controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.
Note: If CMPDAT is equal to PERIOD, this flag will not work in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit
This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
-1
read-write
n
0x0
0x0
PERIOD
BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn pin at tri-state
#0
1
BPWMx_CHn pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWMx_CHn output polar inverse Disabled
#0
1
BPWMx_CHn output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
-1
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit
When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from BPWM0
#00
1
Synchronous start source come from BPWM1
#01
2
Synchronous start source come from BPWM2
#10
3
Synchronous start source come from BPWM3
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
-1
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit (Write Only)
BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.
Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
-1
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event occurred
#0
1
An ADC start of conversion trigger event occurred. Software can write 1 to clear this bit
#1
CNTMAXF0
Time-base Counter 0 Equal to 0xFFFF Latched Flag
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
Note: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
0x30
0x8
registers
n
0x40
0x4
registers
n
0x54
0x4
registers
n
0x70
0x10
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
CRCCKEN
CRC Generator Controller Clock Enable Bit
7
1
read-write
0
CRC peripheral clock Disabled
#0
1
CRC peripheral clock Enabled
#1
FMCIDLE
Flash Memory Controller Clock Enable Bit in IDLE Mode
15
1
read-write
0
FMC peripheral clock Disabled when chip operating at IDLE mode
#0
1
FMC peripheral clock Enabled when chip operating at IDLE mode
#1
GPIOACKEN
General Purpose I/O PA Group Clock Enable Bit
16
1
read-write
0
GPIO PA group clock Disabled
#0
1
GPIO PA group clock Enabled
#1
GPIOBCKEN
General Purpose I/O PB Group Clock Enable Bit
17
1
read-write
0
GPIO PB group clock Disabled
#0
1
GPIO PB group clock Enabled
#1
GPIOCCKEN
General Purpose I/O PC Group Clock Enable Bit
18
1
read-write
0
GPIO PC group clock Disabled
#0
1
GPIO PC group clock Enabled
#1
GPIODCKEN
General Purpose I/O PD Group Clock Enable Bit
19
1
read-write
0
GPIO PD group clock Disabled
#0
1
GPIO PD group clock Enabled
#1
GPIOFCKEN
General Purpose I/O PF Group Clock Enable Bit
21
1
read-write
0
GPIO PF group clock Disabled
#0
1
GPIO PF group clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
PDMACKEN
PDMA Controller Clock Enable Bit
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
-1
read-write
n
0x0
0x0
ADCCKEN
Analog-digital-converter Clock Enable Bit
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
BPWM0CKEN
BPWM0 Clock Enable Bit
20
1
read-write
0
BPWM0 clock Disabled
#0
1
BPWM0 clock Enabled
#1
BPWM1CKEN
BPWM1 Clock Enable Bit
21
1
read-write
0
BPWM1 clock Disabled
#0
1
BPWM1 clock Enabled
#1
BPWM2CKEN
BPWM2 Clock Enable Bit
22
1
read-write
0
BPWM2 clock Disabled
#0
1
BPWM2 clock Enabled
#1
BPWM3CKEN
BPWM3 Clock Enable Bit
23
1
read-write
0
BPWM3 clock Disabled
#0
1
BPWM3 clock Enabled
#1
CLKOCKEN
CLKO Clock Enable Bit
6
1
read-write
0
CLKO Clock Disabled
#0
1
CLKO Clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit
8
1
read-write
0
I2C0 Clock Disabled
#0
1
I2C0 Clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit
9
1
read-write
0
I2C1 Clock Disabled
#0
1
I2C1 Clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit
12
1
read-write
0
SPI0 Clock Disabled
#0
1
SPI0 Clock Enabled
#1
SPI1CKEN
SPI1 Clock Enable Bit
13
1
read-write
0
SPI1 Clock Disabled
#0
1
SPI1 Clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit
2
1
read-write
0
Timer0 Clock Disabled
#0
1
Timer0 Clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit
3
1
read-write
0
Timer1 Clock Disabled
#0
1
Timer1 Clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit
4
1
read-write
0
Timer2 Clock Disabled
#0
1
Timer2 Clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit
5
1
read-write
0
Timer3 Clock Disabled
#0
1
Timer3 Clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
USBDCKEN
USB Device Clock Enable Bit
27
1
read-write
0
USB Device clock Disabled
#0
1
USB Device clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Watchdog Timer Clock Disabled
#0
1
Watchdog Timer Clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0x30
-1
read-write
n
0x0
0x0
LLSI0CKEN
LLSI0 Clock Enable Bit
16
1
read-write
0
LLSI0 clock Disabled
#0
1
LLSI0 clock Enabled
#1
LLSI1CKEN
LLSI1 Clock Enable Bit
17
1
read-write
0
LLSI1 clock Disabled
#0
1
LLSI1 clock Enabled
#1
LLSI2CKEN
LLSI2 Clock Enable Bit
18
1
read-write
0
LLSI2 clock Disabled
#0
1
LLSI2 clock Enabled
#1
LLSI3CKEN
LLSI3 Clock Enable Bit
19
1
read-write
0
LLSI3 clock Disabled
#0
1
LLSI3 clock Enabled
#1
LLSI4CKEN
LLSI4 Clock Enable Bit
20
1
read-write
0
LLSI4 clock Disabled
#0
1
LLSI4 clock Enabled
#1
LLSI5CKEN
LLSI5 Clock Enable Bit
21
1
read-write
0
LLSI5 clock Disabled
#0
1
LLSI5 clock Enabled
#1
LLSI6CKEN
LLSI6 Clock Enable Bit
22
1
read-write
0
LLSI6 clock Disabled
#0
1
LLSI6 clock Enabled
#1
LLSI7CKEN
LLSI7 Clock Enable Bit
23
1
read-write
0
LLSI7 clock Disabled
#0
1
LLSI7 clock Enabled
#1
LLSI8CKEN
LLSI8 Clock Enable Bit
24
1
read-write
0
LLSI8 clock Disabled
#0
1
LLSI8 clock Enabled
#1
LLSI9CKEN
LLSI9 Clock Enable Bit
25
1
read-write
0
LLSI9 clock Disabled
#0
1
LLSI9 clock Enabled
#1
BODCLK
CLK_BODCLK
Clock Source Select for BOD Control Register
0x40
-1
read-write
n
0x0
0x0
VDETCKSEL
Clock Source Selection for Voltage Detector
The Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL.
Note 1: If LIRC is selected, LIRCEN (CLK_PWRCTL[3]) must be enabled.
Note 2: If LXT is selected, LXTEN (CLK_PWRCTL[1]) must be enabled.
Note 3: This bit is also used for Brown-out detector clock source.
0
1
read-write
0
Clock source is from 10 kHz internal low speed RC oscillator (LIRC) clock
#0
1
Clock source is from 32.768 kHz external low speed crystal oscillator (LXT) clock
#1
CDLOWB
CLK_CDLOWB
Clock Frequency Detector Low Boundary Register
0x7C
-1
read-write
n
0x0
0x0
LOWERBD
HXT Clock Frequency Detector Low Boundary
The bits define the low value of frequency monitor window.
When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will be set to 1.
Note: The frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
0
10
read-write
CDUPB
CLK_CDUPB
Clock Frequency Detector Upper Boundary Register
0x78
-1
read-write
n
0x0
0x0
UPERBD
HXT Clock Frequency Detector Upper Boundary
The bits define the high value of frequency monitor window.
When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will be set to 1.
Note: The frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
0
10
read-write
CLKDCTL
CLK_CLKDCTL
Clock Fail Detector Control Register
0x70
-1
read-write
n
0x0
0x0
HXTFDEN
HXT Clock Fail Detector Enable Bit
4
1
read-write
0
4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Enabled
#1
HXTFIEN
HXT Clock Fail Interrupt Enable Bit
5
1
read-write
0
4~24 MHz external high speed crystal oscillator (HXT) clock Fail interrupt Disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock Fail interrupt Enabled
#1
HXTFQDEN
HXT Clock Frequency Monitor Enable Bit
16
1
read-write
0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled
#1
HXTFQIEN
HXT Clock Frequency Monitor Interrupt Enable Bit
17
1
read-write
0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled
#1
LXTFDEN
LXT Clock Fail Detector Enable Bit
12
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Enabled
#1
LXTFIEN
LXT Clock Fail Interrupt Enable Bit
13
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x18
-1
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
8
4
read-write
UART1DIV
UART1 Clock Divide Number From UART1 Clock Source
12
4
read-write
USBDIV
USB Clock Divide Number From PLL Source
Note: If the HIRC is selected, it is delivery to USB clock directly.
4
4
read-write
CLKDSTS
CLK_CLKDSTS
Clock Fail Detector Status Register
0x74
-1
read-write
n
0x0
0x0
HXTFIF
HXT Clock Fail Interrupt Flag (Write Protect)
Note 1: This bit can be cleared to 0 by software writing 1.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
4~24 MHz external high speed crystal oscillator (HXT) clock normal
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock stop
#1
HXTFQIF
HXT Clock Frequency Monitor Interrupt Flag (Write Protect)
Note 1: This bit can be cleared to 0 by software writing 1.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
4~24 MHz external high speed crystal oscillator (HXT) clock normal
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency abnormal
#1
LXTFIF
LXT Clock Fail Interrupt Flag (Write Protect)
Note 1: This bit can be cleared to 0 by software writing 1.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock normal
#0
1
32.768 kHz external low speed crystal oscillator (LXT) stop
#1
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x24
-1
read-write
n
0x0
0x0
CLKOEN
Clock Output Enable Bit
4
1
read-write
0
Clock Output function Disabled
#0
1
Clock Output function Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
0
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from PLL/2 clock
#010
3
Clock source from LIRC
#011
4
Clock source from HIRC
#100
7
Clock source from HIRC/2 clock
#111
PCLK0SEL
PCLK0 Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
APB0 BUS clock source from HCLK
#0
1
APB0 BUS clock source from HCLK/2
#1
PCLK1SEL
PCLK1 Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
APB1 BUS clock source from HCLK
#0
1
APB1 BUS clock source from HCLK/2
#1
STCLKSEL
Cortex-M23 SysTick Clock Source Selection (Write Protect)
Note 2: These bits are write protected. Refer to the SYS_REGLCTL register.
3
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from HXT/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC/4
#111
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADCSEL
ADC Clock Source Selection
2
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#00
1
Clock source from PLL
#01
2
Clock source from PCLK0
#10
3
Clock source from HIRC/2 clock
#11
TMR0SEL
TIMER0 Clock Source Selection
8
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock T0 pin
#011
5
Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock
#101
7
Clock source from HIRC/2 clock
#111
TMR1SEL
TIMER1 Clock Source Selection
12
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock T1 pin
#011
5
Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock
#101
7
Clock source from HIRC/2 clock
#111
TMR2SEL
TIMER2 Clock Source Selection
16
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock T2 pin
#011
5
Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock
#101
7
Clock source from HIRC/2 clock
#111
TMR3SEL
TIMER3 Clock Source Selection
20
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock T3 pin
#011
5
Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock
#101
7
Clock source from HIRC/2 clock
#111
UART0SEL
UART0 Clock Source Selection
24
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#00
1
Clock source from PLL/2 clock
#01
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#10
3
Clock source from HIRC/2 clock
#11
UART1SEL
UART1 Clock Source Selection
26
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#00
1
Clock source from PLL/2 clock
#01
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#10
3
Clock source from HIRC/2 clock
#11
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
0
2
read-write
0
Reserved.
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection
2
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock
#001
2
Clock source from HCLK
#010
3
Clock source from HIRC/2 clock
#011
4
Clock source from SOF (USB start of frame event)
#100
5
Clock source from HIRC clock
#101
SPI0SEL
SPI0 Clock Source Selection
24
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#00
1
Clock source from PLL/2 clock
#01
2
Clock source from PCLK0
#10
3
Clock source from HIRC clock
#11
SPI1SEL
SPI1 Clock Source Selection
26
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock
#00
1
Clock source from PLL/2 clock
#01
2
Clock source from PCLK0
#10
3
Clock source from HIRC clock
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection
16
2
read-write
2
Clock source from HCLK/2048 clock
#10
3
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#11
CLKSEL3
CLK_CLKSEL3
Clock Source Select Control Register 3
0x34
-1
read-write
n
0x0
0x0
USBDSEL
USBD Clock Source Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
Clock source from HIRC clock
#0
1
Clock source from PLL clock
#1
LXTCTL
CLK_LXTCTL
LXT Control Register
0x54
-1
read-write
n
0x0
0x0
GAIN
Oscillator Gain Option
User can select oscillator gain according to crystal external loading and operating temperature range. The greater gain value corresponding to stronger driving capability and higher power consumption.
1
3
read-write
0
L0 mode (ESR=35K CL =25pF)
#000
1
L1 mode (ESR=35K CL =25pF)
#001
2
L2 mode (ESR=35K CL =25pF)
#010
3
L3 mode (ESR=70K CL =25pF)
#011
4
L4 mode (ESR=70K CL =25pF)
#100
5
L5 mode (ESR=70K CL =25pF)
#101
6
L6 mode (ESR=90K CL =25pF)
#110
7
L7 mode (ESR=90K CL =25pF)
#111
PLLCTL
CLK_PLLCTL
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as PLL input clock FIN
#1
FBDIV
PLL Feedback Divider Control
Refer to the formulas below the table.
0
9
read-write
INDIV
PLL Input Divider Control
Refer to the formulas below the table.
9
5
read-write
OE
PLL OUT Enable Control
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDIV
PLL Output Divider Control
Refer to the formulas below the table.
14
2
read-write
PD
Power-down Mode
If set PDEN(CLK_PWRCTL[7]) bit to 1, the PLL will enter Power-down mode, too.
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLLSRC
PLL Source Clock Selection
19
1
read-write
0
PLL source clock from external 4~24 MHz high-speed crystal (HXT)
#0
1
PLL source clock from 48 MHz internal high-speed oscillator divided by 2 (HIRC/2)
#1
STBSEL
PLL Stable Counter Selection
23
1
read-write
0
PLL stable time is 6144 PLL source clock (suitable for source clock equal to or less than 12 MHz)
#0
1
PLL stable time is 12288 PLL source clock (suitable for source clock greater than 12 MHz)
#1
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
48 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) Enabled
#1
HXTEN
HXT Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
4~24 MHz External High Speed Crystal (HXT) Disabled
#0
1
4~24 MHz External High Speed Crystal (HXT) Enabled
#1
HXTGAIN
HXT Gain Control Bit (Write Protect)
Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
10
3
read-write
0
HXT frequency is from 4 MHz to 8 MHz
#000
1
HXT frequency is from 8 MHz to 12 MHz
#001
2
HXT frequency is from 12 MHz to 16 MHz
#010
3
HXT frequency is from 16 MHz to 24 MHz
#011
HXTMD
HXT Bypass Mode (Write Protect)
Note 2: This bit is write protected. Refer to the SYS_REGCTL register.
31
1
read-write
0
HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins
#0
1
HXT works as external clock mode. PF.3 is configured as external clock input pin
#1
LIRCEN
LIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) Enabled
#1
LXTEN
LXT Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
32.768 kHz External Low Speed Crystal (LXT) Disabled
#0
1
32.768 kHz External Low Speed Crystal (LXT) Enabled
#1
PDEN
System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is automatically cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and the clock source selection is ignored. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI command
#0
1
Chip waits CPU sleep command WFI and then enters Power-down mode
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal oscillator (HXT) and 512 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event', which indicates that resume from Power-down mode'
The flag is set if the EINT0~5, VDET, GPIO, USBD, UART0~1, WDT, BOD, TMR0~3 or I2C0~1 wake-up occurred.
Note 1: This bit can be cleared by software writing 1.
Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
6
1
read-write
STATUS
CLK_STATUS
Clock Status Monitor Register
0xC
-1
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
Note: After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
4
1
read-only
0
HIRC clock is not stable or disabled
#0
1
HIRC clock is stable and enabled
#1
HXTSTB
HXT Clock Source Stable Flag (Read Only)
0
1
read-only
0
4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)
3
1
read-only
0
10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
LXTSTB
LXT Clock Source Stable Flag (Read Only)
1
1
read-only
0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled
#1
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable and enabled
#1
CRC
CRC Register Map
CRC
0x0
0x0
0x10
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
-1
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Results
This field indicates the CRC checksum result.
Note: The valid bits of CRC_CHECKSUM[31:0] are correlated to CRCMODE (CRC_CTL[31:30]).
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum 1's Complement Enable Bit
This bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
27
1
read-write
0
1's complement for CRC CHECKSUM Disabled
#0
1
1's complement for CRC CHECKSUM Enabled
#1
CHKSINIT
Checksum Initialization
Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.
Note: This bit will be cleared automatically.
1
1
read-write
0
No effect
#0
1
Reload SEED value to CHECKSUM as CRC operation initial value
#1
CHKSREV
Checksum Bit Order Reverse Enable Bit
This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
Bit order reverse for CRC CHECKSUM Disabled
#0
1
Bit order reverse for CRC CHECKSUM Enabled
#1
CRCEN
CRC Generator Enable Bit
Set this bit 1 to enable CRC generator for CRC operation.
0
1
read-write
0
No effect
#0
1
CRC generator is active
#1
CRCMODE
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
DATFMT
Write Data 1's Complement Enable Bit
This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
26
1
read-write
0
1's complement for CRC DATA Disabled
#0
1
1's complement for CRC DATA Enabled
#1
DATLEN
CPU Write Data Length
This field indicates the valid write data length of DATA (CRC_DAT[31:0]).
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.
Data length is 32-bit mode
#01
DATREV
Write Data Bit Order Reverse Enable Bit
This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]).
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
24
1
read-write
0
Bit order reversed for CRC DATA Disabled
#0
1
Bit order reversed for CRC DATA Enabled (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
-1
read-write
n
0x0
0x0
DATA
CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
-1
read-write
n
0x0
0x0
SEED
CRC Seed Value
This field indicates the CRC seed value.
Note 1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.
Note 2: The valid bits of CRC_SEED[31:0] are correlated to CRCMODE (CRC_CTL[31:30]).
0
32
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
0x80
0x10
registers
n
0xC0
0x8
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address
This register indicates Data Flash start address. It is a read only register.
The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
0
32
read-only
FTCTL
FMC_FTCTL
Flash Access Time Control Register
0x18
-1
read-write
n
0x0
0x0
FOM
Frequency Optimization Mode (Write Protect)
This chip supports adjustable Flash access timing to optimize the Flash access cycles in different working frequency.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
4
3
read-write
0
Frequency is less than or equal to 72 MHz
#000
1
Frequency is less than or equal to 24 MHz
#001
2
Frequency is less than or equal to 48 MHz
#010
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address
The NuMicro NUC1261 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
For Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP CMD Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP CMD
ISP command table is shown below:
The other commands are invalid.
0
7
read-write
0
FLASH Read
0x00
4
Read Unique ID
0x04
8
Read Flash All-One Result
0x08
11
Read Company ID
0x0b
12
Read Device ID
0x0c
13
Read Checksum
0x0d
33
FLASH 32-bit Program
0x21
34
FLASH Page Erase
0x22
38
FLASH Mass Erase
0x26
39
FLASH Multi-Word Program
0x27
40
Run Flash All-One Verification
0x28
45
Run Checksum Calculation
0x2d
46
Vector Remap
0x2e
64
FLASH 64-bit Read
0x40
97
FLASH 64-bit Program
0x61
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Select (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
CONFIG Update Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
CONFIG cannot be updated
#0
1
CONFIG can be updated
#1
ISPEN
ISP Enable Bit (Write Protect)
ISP function enable bit. Set this bit to enable ISP function.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection
(7) Erase or Program command at brown-out detected
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands
Note: This bit is write-protected. Refer to the SYS_REGLCTL register. This bit needs to be cleared by writing 1 to it.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)
LDROM update enable bit.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
SPUEN
SPROM Update Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
SPROM cannot be updated
#0
1
SPROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
-1
read-write
n
0x0
0x0
ALLONE
Flash All-one Verification Flag
This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit can also be cleared by writing 1
7
1
read-write
0
Flash bits are not all 1 after 'Run Flash All-One Verification' complete
#0
1
All of Flash bits are 1 after 'Run Flash All-One Verification' complete
#1
CBS
Boot Selection of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
1
2
read-only
0
LDROM with IAP mode
#00
1
LDROM without IAP mode
#01
2
APROM with IAP mode
#10
3
APROM without IAP mode
#11
ISPBUSY
ISP Busy Flag (Read Only)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP operation is finished
#0
1
ISP is progressed
#1
ISPFF
ISP Fail Flag (Write Protect)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection
(7) Erase or Program command at brown-out detected
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands.
(10) System vector address is remapped to SPROM.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
6
1
read-write
SCODE
Security Code Active Flag
This bit is set by hardware when detecting SPROM secured code is active at Flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation.
31
1
read-write
0
Secured code is inactive
#0
1
Secured code is active
#1
VECMAP
Vector Page Mapping Address (Read Only)
All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.
VECMAP [18:12] should be 0.
9
21
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed
#1
MPADDR
FMC_MPADDR
ISP Multi-program Address Register
0xC4
-1
read-only
n
0x0
0x0
MPADDR
ISP Multi-word Program Address
MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
MPADDR will keep the final ISP address when ISP multi-word program is complete.
0
32
read-only
MPDAT0
FMC_MPDAT0
ISP Data0 Register
0x80
-1
read-write
n
0x0
0x0
ISPDAT0
ISP Data 0
This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
0
32
read-write
MPDAT1
FMC_MPDAT1
ISP Data1 Register
0x84
-1
read-write
n
0x0
0x0
ISPDAT1
ISP Data 1
This register is the second 32-bit data for 64-bit/multi-word programming.
0
32
read-write
MPDAT2
FMC_MPDAT2
ISP Data2 Register
0x88
-1
read-write
n
0x0
0x0
ISPDAT2
ISP Data 2
This register is the third 32-bit data for multi-word programming.
0
32
read-write
MPDAT3
FMC_MPDAT3
ISP Data3 Register
0x8C
-1
read-write
n
0x0
0x0
ISPDAT3
ISP Data 3
This register is the fourth 32-bit data for multi-word programming.
0
32
read-write
MPSTS
FMC_MPSTS
ISP Multi-program Status Register
0xC0
-1
read-only
n
0x0
0x0
D0
ISP DATA 0 Flag (Read Only)
This bit is set when FMC_MPDAT0 is written and auto-cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
4
1
read-only
0
FMC_MPDAT0 register is empty, or program to Flash complete
#0
1
FMC_MPDAT0 register has been written, and not programmed to Flash complete
#1
D1
ISP DATA 1 Flag (Read Only)
This bit is set when FMC_MPDAT1 is written and auto-cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
5
1
read-only
0
FMC_MPDAT1 register is empty, or program to Flash complete
#0
1
FMC_MPDAT1 register has been written, and not programmed to Flash complete
#1
D2
ISP DATA 2 Flag (Read Only)
This bit is set when FMC_MPDAT2 is written and auto-cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
6
1
read-only
0
FMC_MPDAT2 register is empty, or program to Flash complete
#0
1
FMC_MPDAT2 register has been written, and not programmed to Flash complete
#1
D3
ISP DATA 3 Flag (Read Only)
This bit is set when FMC_MPDAT3 is written and auto-cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
7
1
read-only
0
FMC_MPDAT3 register is empty, or program to Flash complete
#0
1
FMC_MPDAT3 register has been written, and not programmed to Flash complete
#1
ISPFF
ISP Fail Flag (Read Only)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) Page Erase command at LOCK mode with ICE connection
(5) Erase or Program command at brown-out detected
(6) Destination address is illegal, such as over an available range.
(7) Invalid ISP commands
2
1
read-only
MPBUSY
ISP Multi-word Program Busy Flag (Read Only)
Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP Multi-Word program operation is finished
#0
1
ISP Multi-Word program operation is progressed
#1
PPGO
ISP Multi-program Status (Read Only)
1
1
read-only
0
ISP multi-word program operation is not active
#0
1
ISP multi-word program operation is in progress
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x34
registers
n
0x140
0x34
registers
n
0x180
0x4
registers
n
0x200
0x100
registers
n
0x340
0x40
registers
n
0x40
0x2C
registers
n
0x70
0x4
registers
n
0x80
0x2C
registers
n
0xB0
0x4
registers
n
0xC0
0x2C
registers
n
0xF0
0x4
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz internal low speed oscillator
#1
ICLKON
Interrupt Clock on Mode
Note: It is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output
0x200
-1
read-write
n
0x0
0x0
PDIO
GPIO Px.n Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
Read this register to get GPIO pin status.
For example, writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).
Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output
0x228
-1
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output
0x22C
-1
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output
0x230
-1
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output
0x234
-1
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output
0x238
-1
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output
0x23C
-1
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output
0x204
-1
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output
0x208
-1
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output
0x20C
-1
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output
0x210
-1
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output
0x214
-1
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output
0x218
-1
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output
0x21C
-1
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output
0x220
-1
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output
0x224
-1
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK0
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK10
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK11
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK12
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK13
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK14
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK15
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK8
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK9
Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control
0x14
-1
read-write
n
0x0
0x0
DBEN0
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN10
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN11
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN12
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN13
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN14
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN15
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN8
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN9
Port A-F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
-1
read-write
n
0x0
0x0
DINOFF0
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF10
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
26
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF11
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
27
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF12
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
28
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF13
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
29
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF14
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
30
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF15
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
31
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF8
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
24
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF9
Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
25
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_DRVCTL
PA_DRVCTL
PA High Drive Strength Control
0x2C
-1
read-write
n
0x0
0x0
HDRVEN0
Port A and F Pin[n] Driving Strength Control
0
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN1
Port A and F Pin[n] Driving Strength Control
1
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN10
Port A and F Pin[n] Driving Strength Control
10
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN11
Port A and F Pin[n] Driving Strength Control
11
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN12
Port A and F Pin[n] Driving Strength Control
12
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN13
Port A and F Pin[n] Driving Strength Control
13
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN14
Port A and F Pin[n] Driving Strength Control
14
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN15
Port A and F Pin[n] Driving Strength Control
15
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN2
Port A and F Pin[n] Driving Strength Control
2
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN3
Port A and F Pin[n] Driving Strength Control
3
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN4
Port A and F Pin[n] Driving Strength Control
4
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN5
Port A and F Pin[n] Driving Strength Control
5
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN6
Port A and F Pin[n] Driving Strength Control
6
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN7
Port A and F Pin[n] Driving Strength Control
7
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN8
Port A and F Pin[n] Driving Strength Control
8
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
HDRVEN9
Port A and F Pin[n] Driving Strength Control
9
1
read-write
0
Px.n output with basic driving and sink strength
#0
1
Px.n output with high driving and sink strength
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control
0x1C
-1
read-write
n
0x0
0x0
FLIEN0
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN10
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN11
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN12
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN13
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN14
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN15
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN8
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN9
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN10
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
26
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN11
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
27
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN12
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
28
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN13
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
29
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN14
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
30
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN15
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
31
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN8
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
24
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN9
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
25
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC0
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC1
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC10
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC11
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC12
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC13
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC14
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC15
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC2
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC3
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC4
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC5
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC6
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC7
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC8
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC9
Port A-F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
-1
read-write
n
0x0
0x0
TYPE0
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE10
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE11
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE12
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE13
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE14
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE15
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE8
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE9
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE10
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
20
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE11
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
22
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE12
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
24
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE13
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
26
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE14
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
28
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE15
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
30
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE8
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
16
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE9
Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
18
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN0
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-only
PIN1
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-only
PIN10
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-only
PIN11
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-only
PIN12
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-only
PIN13
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-only
PIN14
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-only
PIN15
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-only
PIN2
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-only
PIN3
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-only
PIN4
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-only
PIN5
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-only
PIN6
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-only
PIN7
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-only
PIN8
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-only
PIN9
Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-only
PA_PUSEL
PA_PUSEL
PA Pull-up Selection Register
0x30
-1
read-write
n
0x0
0x0
PUSEL0
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL1
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL10
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
20
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL11
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
22
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL12
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
24
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL13
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
26
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL14
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
28
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL15
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
30
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL2
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL3
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL4
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL5
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL6
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL7
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL8
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
16
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PUSEL9
Port A-F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: Basically, the pull-up control has following behavior limitation.
The independent pull-up control register only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
18
1
read-write
0
Px.n pull-up disable
#0
1
Px.n pull-up enable
#1
PA_SLEWCTL
PA_SLEWCTL
PA High Slew Rate Control
0x28
-1
read-write
n
0x0
0x0
HSREN0
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN1
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN10
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN11
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN12
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN13
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN14
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN15
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN2
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN3
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN4
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN5
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN6
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN7
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN8
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
HSREN9
Port A-F Pin[n] High Slew Rate Control
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Px.n output with basic slew rate
#0
1
Px.n output with higher slew rate
#1
PA_SMTEN
PA_SMTEN
PA Input Schmitt Trigger Enable
0x24
-1
read-write
n
0x0
0x0
SMTEN0
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
0
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN1
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
1
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN10
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
10
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN11
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
11
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN12
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
12
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN13
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
13
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN14
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
14
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN15
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
15
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN2
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
2
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN3
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
3
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN4
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
4
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN5
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
5
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN6
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
6
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN7
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
7
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN8
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
8
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN9
Port A-F Pin[n] Input Schmitt Trigger Enable Bit
Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored.
9
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output
0x240
-1
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output
0x268
-1
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output
0x26C
-1
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output
0x270
-1
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output
0x274
-1
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output
0x278
-1
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output
0x27C
-1
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output
0x244
-1
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output
0x248
-1
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output
0x24C
-1
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output
0x250
-1
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output
0x254
-1
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output
0x258
-1
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output
0x25C
-1
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output
0x260
-1
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output
0x264
-1
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
-1
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control
0x54
-1
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Control
0x58
-1
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
-1
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
-1
read-write
n
0x0
0x0
PB_PUSEL
PB_PUSEL
PB Pull-up Selection Register
0x70
-1
read-write
n
0x0
0x0
PB_SLEWCTL
PB_SLEWCTL
PB High Slew Rate Control
0x68
-1
read-write
n
0x0
0x0
PB_SMTEN
PB_SMTEN
PB Input Schmitt Trigger Enable
0x64
-1
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output
0x280
-1
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output
0x2A8
-1
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output
0x2AC
-1
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output
0x2B0
-1
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output
0x2B4
-1
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output
0x2B8
-1
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output
0x2BC
-1
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output
0x284
-1
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output
0x288
-1
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output
0x28C
-1
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output
0x290
-1
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output
0x294
-1
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output
0x298
-1
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output
0x29C
-1
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output
0x2A0
-1
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output
0x2A4
-1
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
-1
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control
0x94
-1
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
-1
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
-1
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control
0x9C
-1
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
-1
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Control
0x98
-1
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
-1
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
-1
read-write
n
0x0
0x0
PC_PUSEL
PC_PUSEL
PC Pull-up Selection Register
0xB0
-1
read-write
n
0x0
0x0
PC_SLEWCTL
PC_SLEWCTL
PC High Slew Rate Control
0xA8
-1
read-write
n
0x0
0x0
PC_SMTEN
PC_SMTEN
PC Input Schmitt Trigger Enable
0xA4
-1
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output
0x2C0
-1
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output
0x2E8
-1
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output
0x2EC
-1
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output
0x2F0
-1
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output
0x2F4
-1
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output
0x2F8
-1
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output
0x2FC
-1
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output
0x2C4
-1
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output
0x2C8
-1
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output
0x2CC
-1
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output
0x2D0
-1
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output
0x2D4
-1
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output
0x2D8
-1
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output
0x2DC
-1
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output
0x2E0
-1
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output
0x2E4
-1
read-write
n
0x0
0x0
PD_DATMSK
PD_DATMSK
PD Data Output Write Mask
0xCC
-1
read-write
n
0x0
0x0
PD_DBEN
PD_DBEN
PD De-bounce Enable Control
0xD4
-1
read-write
n
0x0
0x0
PD_DINOFF
PD_DINOFF
PD Digital Input Path Disable Control
0xC4
-1
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
PD Data Output Value
0xC8
-1
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
PD Interrupt Enable Control
0xDC
-1
read-write
n
0x0
0x0
PD_INTSRC
PD_INTSRC
PD Interrupt Source Flag
0xE0
-1
read-write
n
0x0
0x0
PD_INTTYPE
PD_INTTYPE
PD Interrupt Trigger Type Control
0xD8
-1
read-write
n
0x0
0x0
PD_MODE
PD_MODE
PD I/O Mode Control
0xC0
-1
read-write
n
0x0
0x0
PD_PIN
PD_PIN
PD Pin Value
0xD0
-1
read-write
n
0x0
0x0
PD_PUSEL
PD_PUSEL
PD Pull-up Selection Register
0xF0
-1
read-write
n
0x0
0x0
PD_SLEWCTL
PD_SLEWCTL
PD High Slew Rate Control
0xE8
-1
read-write
n
0x0
0x0
PD_SMTEN
PD_SMTEN
PD Input Schmitt Trigger Enable
0xE4
-1
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output
0x340
-1
read-write
n
0x0
0x0
PF10_PDIO
PF10_PDIO
GPIO PF.n Pin Data Input/Output
0x368
-1
read-write
n
0x0
0x0
PF11_PDIO
PF11_PDIO
GPIO PF.n Pin Data Input/Output
0x36C
-1
read-write
n
0x0
0x0
PF12_PDIO
PF12_PDIO
GPIO PF.n Pin Data Input/Output
0x370
-1
read-write
n
0x0
0x0
PF13_PDIO
PF13_PDIO
GPIO PF.n Pin Data Input/Output
0x374
-1
read-write
n
0x0
0x0
PF14_PDIO
PF14_PDIO
GPIO PF.n Pin Data Input/Output
0x378
-1
read-write
n
0x0
0x0
PF15_PDIO
PF15_PDIO
GPIO PF.n Pin Data Input/Output
0x37C
-1
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output
0x344
-1
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output
0x348
-1
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output
0x34C
-1
read-write
n
0x0
0x0
PF4_PDIO
PF4_PDIO
GPIO PF.n Pin Data Input/Output
0x350
-1
read-write
n
0x0
0x0
PF5_PDIO
PF5_PDIO
GPIO PF.n Pin Data Input/Output
0x354
-1
read-write
n
0x0
0x0
PF6_PDIO
PF6_PDIO
GPIO PF.n Pin Data Input/Output
0x358
-1
read-write
n
0x0
0x0
PF7_PDIO
PF7_PDIO
GPIO PF.n Pin Data Input/Output
0x35C
-1
read-write
n
0x0
0x0
PF8_PDIO
PF8_PDIO
GPIO PF.n Pin Data Input/Output
0x360
-1
read-write
n
0x0
0x0
PF9_PDIO
PF9_PDIO
GPIO PF.n Pin Data Input/Output
0x364
-1
read-write
n
0x0
0x0
PF_DATMSK
PF_DATMSK
PF Data Output Write Mask
0x14C
-1
read-write
n
0x0
0x0
PF_DBEN
PF_DBEN
PF De-bounce Enable Control
0x154
-1
read-write
n
0x0
0x0
PF_DINOFF
PF_DINOFF
PF Digital Input Path Disable Control
0x144
-1
read-write
n
0x0
0x0
PF_DOUT
PF_DOUT
PF Data Output Value
0x148
-1
read-write
n
0x0
0x0
PF_DRVCTL
PF_DRVCTL
PF High Drive Strength Control
0x16C
-1
read-write
n
0x0
0x0
PF_INTEN
PF_INTEN
PF Interrupt Enable Control
0x15C
-1
read-write
n
0x0
0x0
PF_INTSRC
PF_INTSRC
PF Interrupt Source Flag
0x160
-1
read-write
n
0x0
0x0
PF_INTTYPE
PF_INTTYPE
PF Interrupt Trigger Type Control
0x158
-1
read-write
n
0x0
0x0
PF_MODE
PF_MODE
PF I/O Mode Control
0x140
-1
read-write
n
0x0
0x0
PF_PIN
PF_PIN
PF Pin Value
0x150
-1
read-write
n
0x0
0x0
PF_PUSEL
PF_PUSEL
PF Pull-up Selection Register
0x170
-1
read-write
n
0x0
0x0
PF_SLEWCTL
PF_SLEWCTL
PF High Slew Rate Control
0x168
-1
read-write
n
0x0
0x0
PF_SMTEN
PF_SMTEN
PF Input Schmitt Trigger Enable
0x164
-1
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x30
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software sets 10'h000, the address cannot be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_BUSCTL
I2C_BUSCTL
I2C Bus Management Control Register
0x50
-1
read-write
n
0x0
0x0
ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
11
1
read-write
0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#0
1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1
ACKMEN
Acknowledge Control by Manual
In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0
1
read-write
0
Slave byte control Disabled
#0
1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCL signal low between the 8th and 9th SCL pulse
#1
ALERTEN
Bus Management Alert Enable Bit
4
1
read-write
0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
BM_ALERT pin not supported
#0
1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
BM_ALERT pin supported
#1
BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
12
1
read-write
0
Byte count done interrupt Disabled
#0
1
Byte count done interrupt Enabled
#1
BMDEN
Bus Management Device Default Address Enable Bit
2
1
read-write
0
Device default address Disable. When the address 0'b1100001x comes and either BMDEN or ACKMEN is disabled, the device responses NACK
#0
1
Device default address Enabled. When the address 0'b1100001x comes and both BMDEN and ACKMEN are enabled, the device responses ACK
#1
BMHEN
Bus Management Host Enable Bit
3
1
read-write
0
Host function Disabled
#0
1
Host function Enabled
#1
BUSEN
BUS Enable Bit
Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
7
1
read-write
0
The system management function Disabled
#0
1
The system management function Enabled
#1
BUSTOCHK
Timer Check in Idle State
The BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.
Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
9
1
read-write
0
BUSTOCHK is used to calculate the clock low period in bus active
#0
1
BUSTOCHK is used to calculate the IDLE period in bus Idle
#1
PECCLR
PEC Clear at Repeat
The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation.
10
1
read-write
0
PEC calculation is cleared by 'Repeat START' function Disabled
#0
1
PEC calculation is cleared by 'Repeat START' function Enabled
#1
PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
13
1
read-write
0
PEC transfer done interrupt Disabled
#0
1
PEC transfer done interrupt Enabled
#1
PECEN
Packet Error Checking Calculation Enable Bit
Note: When I2C enters Power-down mode, the bit should be enabled after wake-up if needed PEC calculation.
1
1
read-write
0
Packet Error Checking Calculation Disabled
#0
1
Packet Error Checking Calculation Enabled
#1
PECTXEN
Packet Error Checking Byte Transmission/Reception
8
1
read-write
0
No PEC transfer
#0
1
PEC transmission is requested
#1
SCTLOEN
Suspend or Control Pin Output Enable Bit
6
1
read-write
0
The SUSCON pin in input
#0
1
The output enable is active on the SUSCON pin
#1
SCTLOSTS
Suspend/Control Data Output Status
5
1
read-write
0
The output of SUSCON pin is low
#0
1
The output of SUSCON pin is high
#1
I2C_BUSSTS
I2C_BUSSTS
I2C Bus Management Status Register
0x58
-1
read-write
n
0x0
0x0
ALERT
SMBus Alert Status
Note: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
3
1
read-write
0
SMBALERT pin state is low.
No SMBALERT event
#0
1
SMBALERT pin state is high.
There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
#1
BCDONE
Byte Count Transmission/Receive Done
Note: Software can write 1 to clear this bit.
1
1
read-write
0
Byte count transmission/ receive is not finished when the PECEN is set
#0
1
Byte count transmission/ receive is finished when the PECEN is set
#1
BUSTO
Bus Time-out Status
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
5
1
read-write
0
There is no any time-out or external clock time-out
#0
1
A time-out or external clock time-out occurred
#1
BUSY
Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
0
1
read-only
0
Bus is IDLE (both SCL and SDA High)
#0
1
Bus is busy
#1
CLKTO
Clock Low Cumulate Time-out Status
Note: Software can write 1 to clear this bit.
6
1
read-write
0
Cumulative clock low is no any time-out
#0
1
Cumulative clock low time-out occurred
#1
PECDONE
PEC Byte Transmission/Receive Done
Note: Software can write 1 to clear this bit.
7
1
read-write
0
PEC transmission/ receive is not finished when the PECEN is set
#0
1
PEC transmission/ receive is finished when the PECEN is set
#1
PECERR
PEC Error in Reception
Note: Software can write 1 to clear this bit.
2
1
read-write
0
PEC value equal the received PEC data packet
#0
1
PEC value doesn't match the receive PEC data packet
#1
SCTLDIN
Bus Suspend or Control Signal Input Status (Read Only)
4
1
read-only
0
The input status of SUSCON pin is 0
#0
1
The input status of SUSCON pin is 1
#1
I2C_BUSTCTL
I2C_BUSTCTL
I2C Bus Management Timer Control Register
0x54
-1
read-write
n
0x0
0x0
BUSTOEN
Bus Time Out Enable Bit
0
1
read-write
0
Bus clock low time-out detection Disabled
#0
1
Bus clock low time-out detection Enabled (bus clock is low for more than BUSTO (I2C_BUSTOUT[7:0]) (in BIDLE=0) or high more than BUSTO (in BIDLE =1)
#1
BUSTOIEN
Time-out Interrupt Enable Bit
2
1
read-write
0
SCL low time-out interrupt Disabled.
Bus IDLE time-out interrupt Disabled
#0
1
SCL low time-out interrupt Enabled.
Bus IDLE time-out interrupt Enabled
#1
CLKTOEN
Cumulative Clock Low Time Out Enable Bit
For Master, it calculates the period from START to ACK.
For Slave, it calculates the period from START to STOP.
1
1
read-write
0
Cumulative clock low time-out detection Disabled
#0
1
Cumulative clock low time-out detection Enabled
#1
CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
3
1
read-write
0
Clock time out interrupt Disabled
#0
1
Clock time out interrupt Enabled
#1
TORSTEN
Time Out Reset Enable Bit
4
1
read-write
0
I2C state machine reset Disabled
#0
1
I2C state machine reset Enabled. (The clock and data bus will be released to high.)
#1
I2C_BUSTOUT
I2C_BUSTOUT
I2C Bus Management Timer Register
0x64
-1
read-write
n
0x0
0x0
BUSTO
Bus Management Time-out Value
Indicates the bus time-out value in bus is IDLE or SCL low.
Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
0
8
read-write
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
NFCNT
Noise Filter Count
The register bits control the input filter width.
Note: Filter width Min :3*PCLK, Max : 18*PCLK
12
4
read-write
0
Filter width 3*PCLK
0
1
Filter width 4*PCLK
1
I2C_CLKTOUT
I2C_CLKTOUT
I2C Bus Management Clock Low Timer Register
0x68
-1
read-write
n
0x0
0x0
CLKTO
Bus Clock Low Timer
The field is used to configure the cumulative clock extension time-out.
Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and cleared to 0 first in the BUSEN is set.
0
8
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable Bit
9
1
read-write
0
Address match 10-bit function Disabled
#0
1
Address match 10-bit function Enabled
#1
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_PKTCRC
I2C_PKTCRC
I2C Packet Error Checking Byte Value Register
0x60
-1
read-only
n
0x0
0x0
PECCRC
Packet Error Checking Byte Value
0
8
read-only
I2C_PKTSIZE
I2C_PKTSIZE
I2C Packet Error Checking Byte Number Register
0x5C
-1
read-write
n
0x0
0x0
PLDSIZE
Transfer Byte Number
The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.
Note: The byte number counting includes address, command code, and data frame.
0
9
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCL and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x30
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software sets 10'h000, the address cannot be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_BUSCTL
I2C_BUSCTL
I2C Bus Management Control Register
0x50
-1
read-write
n
0x0
0x0
ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
11
1
read-write
0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#0
1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1
ACKMEN
Acknowledge Control by Manual
In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0
1
read-write
0
Slave byte control Disabled
#0
1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCL signal low between the 8th and 9th SCL pulse
#1
ALERTEN
Bus Management Alert Enable Bit
4
1
read-write
0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
BM_ALERT pin not supported
#0
1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
BM_ALERT pin supported
#1
BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
12
1
read-write
0
Byte count done interrupt Disabled
#0
1
Byte count done interrupt Enabled
#1
BMDEN
Bus Management Device Default Address Enable Bit
2
1
read-write
0
Device default address Disable. When the address 0'b1100001x comes and either BMDEN or ACKMEN is disabled, the device responses NACK
#0
1
Device default address Enabled. When the address 0'b1100001x comes and both BMDEN and ACKMEN are enabled, the device responses ACK
#1
BMHEN
Bus Management Host Enable Bit
3
1
read-write
0
Host function Disabled
#0
1
Host function Enabled
#1
BUSEN
BUS Enable Bit
Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
7
1
read-write
0
The system management function Disabled
#0
1
The system management function Enabled
#1
BUSTOCHK
Timer Check in Idle State
The BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.
Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
9
1
read-write
0
BUSTOCHK is used to calculate the clock low period in bus active
#0
1
BUSTOCHK is used to calculate the IDLE period in bus Idle
#1
PECCLR
PEC Clear at Repeat
The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation.
10
1
read-write
0
PEC calculation is cleared by 'Repeat START' function Disabled
#0
1
PEC calculation is cleared by 'Repeat START' function Enabled
#1
PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
13
1
read-write
0
PEC transfer done interrupt Disabled
#0
1
PEC transfer done interrupt Enabled
#1
PECEN
Packet Error Checking Calculation Enable Bit
Note: When I2C enters Power-down mode, the bit should be enabled after wake-up if needed PEC calculation.
1
1
read-write
0
Packet Error Checking Calculation Disabled
#0
1
Packet Error Checking Calculation Enabled
#1
PECTXEN
Packet Error Checking Byte Transmission/Reception
8
1
read-write
0
No PEC transfer
#0
1
PEC transmission is requested
#1
SCTLOEN
Suspend or Control Pin Output Enable Bit
6
1
read-write
0
The SUSCON pin in input
#0
1
The output enable is active on the SUSCON pin
#1
SCTLOSTS
Suspend/Control Data Output Status
5
1
read-write
0
The output of SUSCON pin is low
#0
1
The output of SUSCON pin is high
#1
I2C_BUSSTS
I2C_BUSSTS
I2C Bus Management Status Register
0x58
-1
read-write
n
0x0
0x0
ALERT
SMBus Alert Status
Note: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
3
1
read-write
0
SMBALERT pin state is low.
No SMBALERT event
#0
1
SMBALERT pin state is high.
There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
#1
BCDONE
Byte Count Transmission/Receive Done
Note: Software can write 1 to clear this bit.
1
1
read-write
0
Byte count transmission/ receive is not finished when the PECEN is set
#0
1
Byte count transmission/ receive is finished when the PECEN is set
#1
BUSTO
Bus Time-out Status
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
5
1
read-write
0
There is no any time-out or external clock time-out
#0
1
A time-out or external clock time-out occurred
#1
BUSY
Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
0
1
read-only
0
Bus is IDLE (both SCL and SDA High)
#0
1
Bus is busy
#1
CLKTO
Clock Low Cumulate Time-out Status
Note: Software can write 1 to clear this bit.
6
1
read-write
0
Cumulative clock low is no any time-out
#0
1
Cumulative clock low time-out occurred
#1
PECDONE
PEC Byte Transmission/Receive Done
Note: Software can write 1 to clear this bit.
7
1
read-write
0
PEC transmission/ receive is not finished when the PECEN is set
#0
1
PEC transmission/ receive is finished when the PECEN is set
#1
PECERR
PEC Error in Reception
Note: Software can write 1 to clear this bit.
2
1
read-write
0
PEC value equal the received PEC data packet
#0
1
PEC value doesn't match the receive PEC data packet
#1
SCTLDIN
Bus Suspend or Control Signal Input Status (Read Only)
4
1
read-only
0
The input status of SUSCON pin is 0
#0
1
The input status of SUSCON pin is 1
#1
I2C_BUSTCTL
I2C_BUSTCTL
I2C Bus Management Timer Control Register
0x54
-1
read-write
n
0x0
0x0
BUSTOEN
Bus Time Out Enable Bit
0
1
read-write
0
Bus clock low time-out detection Disabled
#0
1
Bus clock low time-out detection Enabled (bus clock is low for more than BUSTO (I2C_BUSTOUT[7:0]) (in BIDLE=0) or high more than BUSTO (in BIDLE =1)
#1
BUSTOIEN
Time-out Interrupt Enable Bit
2
1
read-write
0
SCL low time-out interrupt Disabled.
Bus IDLE time-out interrupt Disabled
#0
1
SCL low time-out interrupt Enabled.
Bus IDLE time-out interrupt Enabled
#1
CLKTOEN
Cumulative Clock Low Time Out Enable Bit
For Master, it calculates the period from START to ACK.
For Slave, it calculates the period from START to STOP.
1
1
read-write
0
Cumulative clock low time-out detection Disabled
#0
1
Cumulative clock low time-out detection Enabled
#1
CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
3
1
read-write
0
Clock time out interrupt Disabled
#0
1
Clock time out interrupt Enabled
#1
TORSTEN
Time Out Reset Enable Bit
4
1
read-write
0
I2C state machine reset Disabled
#0
1
I2C state machine reset Enabled. (The clock and data bus will be released to high.)
#1
I2C_BUSTOUT
I2C_BUSTOUT
I2C Bus Management Timer Register
0x64
-1
read-write
n
0x0
0x0
BUSTO
Bus Management Time-out Value
Indicates the bus time-out value in bus is IDLE or SCL low.
Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
0
8
read-write
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
NFCNT
Noise Filter Count
The register bits control the input filter width.
Note: Filter width Min :3*PCLK, Max : 18*PCLK
12
4
read-write
0
Filter width 3*PCLK
0
1
Filter width 4*PCLK
1
I2C_CLKTOUT
I2C_CLKTOUT
I2C Bus Management Clock Low Timer Register
0x68
-1
read-write
n
0x0
0x0
CLKTO
Bus Clock Low Timer
The field is used to configure the cumulative clock extension time-out.
Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and cleared to 0 first in the BUSEN is set.
0
8
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable Bit
9
1
read-write
0
Address match 10-bit function Disabled
#0
1
Address match 10-bit function Enabled
#1
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_PKTCRC
I2C_PKTCRC
I2C Packet Error Checking Byte Value Register
0x60
-1
read-only
n
0x0
0x0
PECCRC
Packet Error Checking Byte Value
0
8
read-only
I2C_PKTSIZE
I2C_PKTSIZE
I2C Packet Error Checking Byte Number Register
0x5C
-1
read-write
n
0x0
0x0
PLDSIZE
Transfer Byte Number
The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.
Note: The byte number counting includes address, command code, and data frame.
0
9
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy (Read Only)
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCL and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
LLSI0
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI1
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI2
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI3
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI4
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI5
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI6
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI7
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI8
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
LLSI9
LLSI Register Map
LLSI
0x0
0x0
0x24
registers
n
LLSI_CLKDIV
LLSI_CLKDIV
LLSI Clock Divider Register
0x18
-1
read-write
n
0x0
0x0
DIVIDER
LLSI Clock Divider
It indicates the LLSI clock,
0
8
read-write
LLSI_CTL
LLSI_CTL
LLSI Control Register
0x0
-1
read-write
n
0x0
0x0
EMPINTEN
FIFO Empty Interrupt Enable Bit
Note: If this bit is enabled, when the EMPIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
5
1
read-write
0
FIFO empty interrupt Disabled
#0
1
FIFO empty interrupt Enabled
#1
FENDINTEN
Frame End Interrupt Enable Bit
Note: If this bit is enabled, when the FENDIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
3
1
read-write
0
Frame end interrupt Disabled
#0
1
Frame end interrupt Enabled
#1
FULINTEN
FIFO FULL Interrupt Enable Bit
Note: If this bit is enabled, when the FULIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
6
1
read-write
0
FIFO full interrupt Disabled
#0
1
FIFO full interrupt Enabled
#1
LLSIEN
LLSI Enable Bit
0
1
read-write
0
LLSI Disabled
#0
1
LLSI Enabled
#1
LLSIMODE
LLSI Mode Select
8
1
read-write
0
Software mode
#0
1
PDMA mode
#1
OFDEF
Output Format Define
12
1
read-write
0
Output RGB format
#0
1
Output GRB format
#1
RSTCEN
Reset Command Function Enable Bit
Note: If this bit is enabled, when FIFO and shift register are both empty, LLSI will send reset command out.
1
1
read-write
0
Reset command function Disabled
#0
1
Reset command function Enabled
#1
RSTCINTEN
Reset Command Interrupt Enable Bit
Note: If this bit is enabled, when the RSTCIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
4
1
read-write
0
Reset command interrupt Disabled
#0
1
Reset command interrupt Enabled
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
16
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
Note: This bit is only supported in software mode.
7
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
UNDFLINTEN
Underflow Interrupt Enable Bit
Note: If this bit is enabled, when the UNDFLIF interrupt flag is set to 1, the LLSI interrupt signal is generated and inform to CPU.
2
1
read-write
0
Underflow interrupt Disabled
#0
1
Underflow interrupt Enabled
#1
LLSI_DATA
LLSI_DATA
LLSI Data Register
0x10
-1
write-only
n
0x0
0x0
DATA
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers.
0
32
write-only
LLSI_DUTY
LLSI_DUTY
LLSI Duty Control Register
0xC
-1
read-write
n
0x0
0x0
T0H
T0H Data Register
This field is used to define the time of T0H.
0
8
read-write
T1H
T1H Data Register
This field is used to define the time of T1H.
16
8
read-write
LLSI_OCTL
LLSI_OCTL
LLSI Output Control Register
0x20
-1
read-write
n
0x0
0x0
IDOS
Idle Output Control
0
1
read-write
0
Idle will output 0
#0
1
Idle will output 1
#1
LLSI_PCNT
LLSI_PCNT
LLSI Pixel Count Register
0x14
-1
read-write
n
0x0
0x0
PCNT
Pixel Count Register
User should write a frame size to this register before transfer.
For example, if there are a total of 5 LED (5 pixels) in frame, user should write 5 to this control register.
0
12
read-write
LLSI_PERIOD
LLSI_PERIOD
LLSI Period Control Register
0x8
-1
read-write
n
0x0
0x0
PERIOD
LLSI Period Register
This field is used to define data transfer time (TH+TL).
0
8
read-write
LLSI_RSTPERIOD
LLSI_RSTPERIOD
LLSI Reset Period Control Register
0x4
-1
read-write
n
0x0
0x0
RSTPERIOD
Reset Command Period
This field is used to adjust the time of reset command.
0
16
read-write
LLSI_STATUS
LLSI_STATUS
LLSI Status Register
0x1C
-1
read-write
n
0x0
0x0
EMPIF
FIFO Empty Interrupt Flag
1
1
read-write
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
FENDIF
Frame End Interrupt Flag
This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.
User can use this flag to prepare data in advance.
Software can write 1 to clear this bit.
5
1
read-write
FULIF
FIFO Full Interrupt Flag
2
1
read-write
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
LDT
Last Data Transmit
8
1
read-write
RSTCIF
Reset Command Interrupt Flag
This bit indicates that LLSI has finished reset command transmission.
0
1
read-write
TXTHIF
Transmit FIFO Threshold Interrupt Flag
3
1
read-write
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
UNDFLIF
Under Flow Interrupt Flag
Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.
Software can write 1 to clear this bit.
4
1
read-write
NMI
NMI Register Map
NMI
0x0
0x0
0x8
registers
n
NMIEN
NMIEN
NMI Source Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BODOUT
BOD NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock fail detected interrupt NMI source Disabled
#0
1
Clock fail detected interrupt NMI source Enabled
#1
EINT0
External Interrupt From INT0 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt from INT0 pin NMI source Disabled
#0
1
External interrupt from INT0 pin NMI source Enabled
#1
EINT1
External Interrupt From INT1 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt from INT1 pin NMI source Disabled
#0
1
External interrupt from INT1 pin NMI source Enabled
#1
EINT2
External Interrupt From INT2 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
External interrupt from INT2 pin NMI source Disabled
#0
1
External interrupt from INT2 pin NMI source Enabled
#1
EINT3
External Interrupt From INT3 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
11
1
read-write
0
External interrupt from INT3 pin NMI source Disabled
#0
1
External interrupt from INT3 pin NMI source Enabled
#1
EINT4
External Interrupt From INT4 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
External interrupt from INT4 pin NMI source Disabled
#0
1
External interrupt from INT4 pin NMI source Enabled
#1
EINT5
External Interrupt From INT5 Pin NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
External interrupt from INT5 pin NMI source Disabled
#0
1
External interrupt from INT5 pin NMI source Enabled
#1
IRC_INT
IRC TRIM NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWU_INT
Power-down Mode Wake-up NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
UART0_INT
UART0 NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
UART1_INT
UART1 NMI Source Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
UART1 NMI source Disabled
#0
1
UART1 NMI source Enabled
#1
NMISTS
NMISTS
NMI Source Interrupt Status Register
0x4
-1
read-only
n
0x0
0x0
BODOUT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected Interrupt Flag (Read Only)
4
1
read-only
0
Clock fail detected interrupt is deasserted
#0
1
Clock fail detected interrupt is asserted
#1
EINT0
External Interrupt From INT0 Pin Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt from INT0 pin interrupt is deasserted
#0
1
External Interrupt from INT0 pin interrupt is asserted
#1
EINT1
External Interrupt From INT1 Pin Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt from INT1 pin interrupt is deasserted
#0
1
External Interrupt from INT1 pin interrupt is asserted
#1
EINT2
External Interrupt From INT2 Pin Interrupt Flag (Read Only)
10
1
read-only
0
External Interrupt from INT2 pin interrupt is deasserted
#0
1
External Interrupt from INT2 pin interrupt is asserted
#1
EINT3
External Interrupt From INT3 Pin Interrupt Flag (Read Only)
11
1
read-only
0
External Interrupt from INT3 pin interrupt is deasserted
#0
1
External Interrupt from INT3 pin interrupt is asserted
#1
EINT4
External Interrupt From INT4 Pin Interrupt Flag (Read Only)
12
1
read-only
0
External Interrupt from INT4 pin interrupt is deasserted
#0
1
External Interrupt from INT4 pin interrupt is asserted
#1
EINT5
External Interrupt From INT5 Pin Interrupt Flag (Read Only)
13
1
read-only
0
External Interrupt from INT5 pin interrupt is deasserted
#0
1
External Interrupt from INT5 pin interrupt is asserted
#1
IRC_INT
IRC TRIM Interrupt Flag (Read Only)
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWU_INT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
UART0_INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
UART1_INT
UART1 Interrupt Flag (Read Only)
15
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x8
registers
n
0x100
0x8
registers
n
0x180
0x8
registers
n
0x200
0x8
registers
n
0x80
0x8
registers
n
IABR0
NVIC_IABR0
IRQ0 ~ IRQ31 Active Bit Register
0x200
-1
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
IABR1
NVIC_IABR1
IRQ32 ~ IRQ41 Active Bit Register
0x204
-1
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags
The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
ICER0
NVIC_ICER0
IRQ0 ~ IRQ31 Clear-enable Control Register
0x80
-1
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER1 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
ICER1
NVIC_ICER1
IRQ32 ~ IRQ41 Clear-enable Control Register
0x84
-1
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ31 Clear-pending Control Register
0x180
-1
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state an interrupt.
Interrupt is pending
1
ICPR1
NVIC_ICPR1
IRQ32 ~ IRQ41 Clear-pending Control Register
0x184
-1
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state an interrupt.
Interrupt is pending
1
ISER0
NVIC_ISER0
IRQ0 ~ IRQ31 Set-enable Control Register
0x0
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER1 registers enable interrupts, and show which interrupts are enabled
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
ISER1
NVIC_ISER1
IRQ32 ~ IRQ41 Set-enable Control Register
0x4
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit
The NVIC_ISER0-NVIC_ISER1 registers enable interrupts, and show which interrupts are enabled
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ31 Set-pending Control Register
0x100
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
ISPR1
NVIC_ISPR1
IRQ32 ~ IRQ41 Set-pending Control Register
0x104
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending
The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
PDMA
PDMA Register Map
PDMA
0x0
0x0
0xC8
registers
n
0x400
0x44
registers
n
0x460
0x4
registers
n
0x480
0xC
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Channel Read/Write Target Abort Flag Register
0x420
-1
read-write
n
0x0
0x0
ABTIF0
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
0
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF1
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
1
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF2
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
2
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF3
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
3
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF4
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
4
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF5
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
5
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF6
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
6
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF7
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
7
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF8
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
8
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF9
PDMA Channel n Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
9
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
CHCTL
PDMA_CHCTL
PDMA Channel Control Register
0x400
-1
read-write
n
0x0
0x0
CHEN0
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
0
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN1
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
1
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN2
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
2
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN3
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
3
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN4
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
4
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN5
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
5
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN6
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
6
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN7
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
7
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN8
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
8
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN9
PDMA Channel n Enable Bit
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
9
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xA0
-1
read-only
n
0x0
0x0
CURADDR
PDMA Current Description Address Register (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xA4
-1
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xA8
-1
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xAC
-1
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xB0
-1
read-write
n
0x0
0x0
CURSCAT5
PDMA_CURSCAT5
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xB4
-1
read-write
n
0x0
0x0
CURSCAT6
PDMA_CURSCAT6
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xB8
-1
read-write
n
0x0
0x0
CURSCAT7
PDMA_CURSCAT7
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xBC
-1
read-write
n
0x0
0x0
CURSCAT8
PDMA_CURSCAT8
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xC0
-1
read-write
n
0x0
0x0
CURSCAT9
PDMA_CURSCAT9
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0xC4
-1
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel n
0x0
-1
read-write
n
0x0
0x0
BURSIZE
Burst Size
This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.
Note: This field is only useful in burst transfer type.
4
3
read-write
0
128 Transfers
#000
1
64 Transfers
#001
2
32 Transfers
#010
3
16 Transfers
#011
4
8 Transfers
#100
5
4 Transfers
#101
6
2 Transfers
#110
7
1 Transfers
#111
DAINC
Destination Address Increment
This field is used to set the destination address increment size.
10
2
read-write
3
No increment (fixed address)
#11
OPMODE
PDMA Operation Mode Selection
Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
0
2
read-write
0
Idle state: Channel is stopped or this table is complete. When PDMA finishes channel table task, OPMODE will be cleared to idle state automatically
#00
1
Basic mode: The descriptor table only has one task. When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted
#01
2
Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register the PDMA controller will ignore this task, then load the next task to execute
#10
3
Reserved.
#11
SAINC
Source Address Increment
This Field Is Used To Set The Source Address Increment Size.
8
2
read-write
3
No Increment (Fixed Address)
#11
TBINTDIS
Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
Note: If this bit set to '1', the TEMPTYF will not be set.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finishes each transfer data, this field will be decreased immediately.
16
14
read-write
TXTYPE
Transfer Type
2
1
read-write
0
Burst transfer type
#0
1
Single transfer type
#1
TXWIDTH
Transfer Width Selection
This field is used for transfer width.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment. The source address is aligned when TXWIDTH is byte or half-word transfer.
12
2
read-write
0
One byte (8 bit) is transferred for every operation
#00
1
One half-word (16 bit) is transferred for every operation
#01
2
One word (32-bit) is transferred for every operation
#10
3
Reserved.
#11
DSCT0_DA
PDMA_DSCT0_DA
Destination Address Register of PDMA Channel n
0x8
-1
read-write
n
0x0
0x0
DA
PDMA Transfer Destination Address Register
This field indicates a 32-bit destination address of PDMA controller.
0
32
read-write
DSCT0_FIRST
PDMA_DSCT0_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0xC
-1
read-write
n
0x0
0x0
FIRST
PDMA First Descriptor Table Offset
This field indicates the offset of the first descriptor table address in system memory.
Write Operation:
If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is started from 0x2000_0100, then this field must be filled with 0x0100.
Read Operation:
When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.
Note 1: The first descriptor table address must be word boundary.
Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
0
16
read-write
NEXT
PDMA Next Descriptor Table Offset
This field indicates the offset of next descriptor table address in system memory.
Note: write operation is useless in this field.
16
16
read-write
DSCT0_SA
PDMA_DSCT0_SA
Source Address Register of PDMA Channel n
0x4
-1
read-write
n
0x0
0x0
SA
PDMA Transfer Source Address Register
This field indicates a 32-bit source address of PDMA controller.
0
32
read-write
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel n
0x10
-1
read-write
n
0x0
0x0
DSCT1_DA
PDMA_DSCT1_DA
Destination Address Register of PDMA Channel n
0x18
-1
read-write
n
0x0
0x0
DSCT1_FIRST
PDMA_DSCT1_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x1C
-1
read-write
n
0x0
0x0
DSCT1_SA
PDMA_DSCT1_SA
Source Address Register of PDMA Channel n
0x14
-1
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel n
0x20
-1
read-write
n
0x0
0x0
DSCT2_DA
PDMA_DSCT2_DA
Destination Address Register of PDMA Channel n
0x28
-1
read-write
n
0x0
0x0
DSCT2_FIRST
PDMA_DSCT2_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x2C
-1
read-write
n
0x0
0x0
DSCT2_SA
PDMA_DSCT2_SA
Source Address Register of PDMA Channel n
0x24
-1
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel n
0x30
-1
read-write
n
0x0
0x0
DSCT3_DA
PDMA_DSCT3_DA
Destination Address Register of PDMA Channel n
0x38
-1
read-write
n
0x0
0x0
DSCT3_FIRST
PDMA_DSCT3_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x3C
-1
read-write
n
0x0
0x0
DSCT3_SA
PDMA_DSCT3_SA
Source Address Register of PDMA Channel n
0x34
-1
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel n
0x40
-1
read-write
n
0x0
0x0
DSCT4_DA
PDMA_DSCT4_DA
Destination Address Register of PDMA Channel n
0x48
-1
read-write
n
0x0
0x0
DSCT4_FIRST
PDMA_DSCT4_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x4C
-1
read-write
n
0x0
0x0
DSCT4_SA
PDMA_DSCT4_SA
Source Address Register of PDMA Channel n
0x44
-1
read-write
n
0x0
0x0
DSCT5_CTL
PDMA_DSCT5_CTL
Descriptor Table Control Register of PDMA Channel n
0x50
-1
read-write
n
0x0
0x0
DSCT5_DA
PDMA_DSCT5_DA
Destination Address Register of PDMA Channel n
0x58
-1
read-write
n
0x0
0x0
DSCT5_FIRST
PDMA_DSCT5_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x5C
-1
read-write
n
0x0
0x0
DSCT5_SA
PDMA_DSCT5_SA
Source Address Register of PDMA Channel n
0x54
-1
read-write
n
0x0
0x0
DSCT6_CTL
PDMA_DSCT6_CTL
Descriptor Table Control Register of PDMA Channel n
0x60
-1
read-write
n
0x0
0x0
DSCT6_DA
PDMA_DSCT6_DA
Destination Address Register of PDMA Channel n
0x68
-1
read-write
n
0x0
0x0
DSCT6_FIRST
PDMA_DSCT6_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x6C
-1
read-write
n
0x0
0x0
DSCT6_SA
PDMA_DSCT6_SA
Source Address Register of PDMA Channel n
0x64
-1
read-write
n
0x0
0x0
DSCT7_CTL
PDMA_DSCT7_CTL
Descriptor Table Control Register of PDMA Channel n
0x70
-1
read-write
n
0x0
0x0
DSCT7_DA
PDMA_DSCT7_DA
Destination Address Register of PDMA Channel n
0x78
-1
read-write
n
0x0
0x0
DSCT7_FIRST
PDMA_DSCT7_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x7C
-1
read-write
n
0x0
0x0
DSCT7_SA
PDMA_DSCT7_SA
Source Address Register of PDMA Channel n
0x74
-1
read-write
n
0x0
0x0
DSCT8_CTL
PDMA_DSCT8_CTL
Descriptor Table Control Register of PDMA Channel n
0x80
-1
read-write
n
0x0
0x0
DSCT8_DA
PDMA_DSCT8_DA
Destination Address Register of PDMA Channel n
0x88
-1
read-write
n
0x0
0x0
DSCT8_FIRST
PDMA_DSCT8_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x8C
-1
read-write
n
0x0
0x0
DSCT8_SA
PDMA_DSCT8_SA
Source Address Register of PDMA Channel n
0x84
-1
read-write
n
0x0
0x0
DSCT9_CTL
PDMA_DSCT9_CTL
Descriptor Table Control Register of PDMA Channel n
0x90
-1
read-write
n
0x0
0x0
DSCT9_DA
PDMA_DSCT9_DA
Destination Address Register of PDMA Channel n
0x98
-1
read-write
n
0x0
0x0
DSCT9_FIRST
PDMA_DSCT9_FIRST
First Scatter-gather Descriptor Table Offset of PDMA Channel n
0x9C
-1
read-write
n
0x0
0x0
DSCT9_SA
PDMA_DSCT9_SA
Source Address Register of PDMA Channel n
0x94
-1
read-write
n
0x0
0x0
INTEN
PDMA_INTEN
PDMA Interrupt Enable Register
0x418
-1
read-write
n
0x0
0x0
INTEN0
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
0
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN1
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
1
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN2
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
2
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN3
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
3
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN4
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
4
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN5
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
5
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN6
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
6
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN7
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
7
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN8
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
8
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN9
PDMA Channel n Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
9
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTSTS
PDMA_INTSTS
PDMA Interrupt Status Register
0x41C
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read Only)
This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
0
1
read-only
0
No AHB bus ERROR response received
#0
1
AHB bus ERROR response received
#1
REQTOF0
PDMA Channel n Request Time-out Flag
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
8
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
REQTOF1
PDMA Channel n Request Time-out Flag
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
9
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
TDIF
Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
1
1
read-only
0
Not finished yet
#0
1
PDMA channel has finished transmission
#1
TEIF
Table Empty Interrupt Flag (Read Only)
This bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty.
2
1
read-only
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty
#1
PAUSE
PDMA_PAUSE
PDMA Transfer Pause Control Register
0x404
-1
write-only
n
0x0
0x0
PAUSE0
PDMA Channel n Transfer Pause Control Register (Write Only)
0
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE1
PDMA Channel n Transfer Pause Control Register (Write Only)
1
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE2
PDMA Channel n Transfer Pause Control Register (Write Only)
2
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE3
PDMA Channel n Transfer Pause Control Register (Write Only)
3
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE4
PDMA Channel n Transfer Pause Control Register (Write Only)
4
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE5
PDMA Channel n Transfer Pause Control Register (Write Only)
5
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE6
PDMA Channel n Transfer Pause Control Register (Write Only)
6
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE7
PDMA Channel n Transfer Pause Control Register (Write Only)
7
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE8
PDMA Channel n Transfer Pause Control Register (Write Only)
8
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE9
PDMA Channel n Transfer Pause Control Register (Write Only)
9
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
-1
write-only
n
0x0
0x0
FPRICLR0
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
0
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR1
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
1
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR2
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
2
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR3
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
3
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR4
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
4
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR5
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
5
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR6
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
6
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR7
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
7
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR8
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
8
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR9
PDMA Channel n Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
9
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
-1
read-write
n
0x0
0x0
FPRISET0
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
0
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET1
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
1
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET2
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
2
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET3
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
3
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET4
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
4
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET5
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
5
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET6
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
6
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET7
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
7
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET8
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
8
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET9
PDMA Channel n Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
9
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
REQSEL0_3
PDMA_REQSEL0_3
PDMA Channel 0 to Channel 3 Request Source Select Register
0x480
-1
read-write
n
0x0
0x0
REQSRC0
Channel 0 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.
Note 1: A request source can't assign to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
0
6
read-write
0
Disable PDMA
0
1
Reserved.
1
10
Reserved
10
11
Reserved
11
12
Reserved
12
13
Reserved
13
14
Reserved
14
15
Reserved
15
16
Channel connects to SPI0_TX
16
17
Channel connects to SPI0_RX
17
18
Channel connects to SPI1_TX
18
19
Channel connects to SPI1_RX
19
20
Channel connects to ADC_RX
20
21
Reserved
21
22
Reserved
22
23
Reserved
23
24
Reserved
24
25
Reserved
25
26
Reserved
26
27
Reserved.
27
28
Channel connects to I2C0_TX
28
29
Channel connects to I2C0_RX
29
30
Channel connects to I2C1_TX
30
31
Channel connects to I2C1_RX
31
32
Channel connects to TMR0
32
33
Channel connects to TMR1
33
34
Channel connects to TMR2
34
35
Channel connects to TMR3
35
36
Channel connects to LLSI0
36
37
Channel connects to LLSI1
37
38
Channel connects to LLSI2
38
39
Channel connects to LLSI3
39
4
Channel connects to UART0_TX
4
40
Channel connects to LLSI4
40
41
Channel connects to LLSI5
41
42
Channel connects to LLSI6
42
43
Channel connects to LLSI7
43
44
Channel connects to LLSI8
44
45
Channel connects to LLSI9
45
5
Channel connects to UART0_RX
5
6
Channel connects to UART1_TX
6
7
Channel connects to UART1_RX
7
8
Channel connects to UART2_TX
8
9
Channel connects to UART2_RX
9
REQSRC1
Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC2
Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC3
Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL4_7
PDMA_REQSEL4_7
PDMA Channel 4 to Channel 7 Request Source Select Register
0x484
-1
read-write
n
0x0
0x0
REQSRC4
Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC5
Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC6
Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC7
Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL8_9
PDMA_REQSEL8_9
PDMA Channel 8 to Channel 9 Request Source Select Register
0x488
-1
read-write
n
0x0
0x0
REQSRC8
Channel 8 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC9
Channel 9 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
RESET
PDMA_RESET
PDMA Channel Reset Control Register
0x460
-1
read-write
n
0x0
0x0
RESET0
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
0
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET1
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
1
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET2
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
2
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET3
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
3
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET4
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
4
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET5
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
5
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET6
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
6
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET7
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
7
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET8
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
8
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
RESET9
PDMA Channel n Reset Control Register
Note: This bit will be cleared automatically after finishing reset process.
9
1
read-write
0
No effect
#0
1
Reset PDMA channel n
#1
SCATBA
PDMA_SCATBA
PDMA Scatter-gather Descriptor Table Base Address Register
0x43C
-1
read-write
n
0x0
0x0
SCATBA
PDMA Scatter-gather Descriptor Table Address Register
In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is
Note: Only useful in Scatter-Gather mode.
16
16
read-write
SCATSTS
PDMA_SCATSTS
PDMA Scatter-gather Table Empty Status Register
0x428
-1
read-write
n
0x0
0x0
TEMPTYF0
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
0
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF1
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
1
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF2
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
2
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF3
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
3
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF4
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
4
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF5
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
5
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF6
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
6
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF7
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
7
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF8
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
8
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
TEMPTYF9
Table Empty Flag Register
T This bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
9
1
read-write
0
PDMA channel scatter-gather table is not empty
#0
1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
#1
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
-1
write-only
n
0x0
0x0
SWREQ0
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
0
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ1
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
1
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ2
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
2
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ3
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
3
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ4
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
4
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ5
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
5
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ6
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
6
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ7
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
7
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ8
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
8
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ9
PDMA Channel n Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
9
1
write-only
0
No effect
#0
1
Generate a software request
#1
TACTSTS
PDMA_TACTSTS
PDMA Transfer Active Flag Register
0x42C
-1
read-only
n
0x0
0x0
TXACTF0
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
0
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF1
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
1
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF2
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
2
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF3
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
3
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF4
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
4
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF5
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
5
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF6
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
6
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF7
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
7
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF8
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
8
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF9
PDMA Channel n Transfer on Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
9
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TDSTS
PDMA_TDSTS
PDMA Channel Transfer Done Flag Register
0x424
-1
read-write
n
0x0
0x0
TDIF0
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
0
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF1
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
1
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF2
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
2
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF3
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
3
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF4
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
4
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF5
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
5
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF6
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
6
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF7
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
7
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF8
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
8
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF9
PDMA Channel n Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
9
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TOC0_1
PDMA_TOC0_1
PDMA Channel 0 and Channel 1 Time-out Counter Register
0x440
-1
read-write
n
0x0
0x0
TOC0
Time-out Counter for Channel 0
This controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
0
16
read-write
TOC1
Time-out Counter for Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description.
16
16
read-write
TOUTEN
PDMA_TOUTEN
PDMA Time-out Enable Register
0x434
-1
read-write
n
0x0
0x0
TOUTEN0
PDMA Channel n Time-out Enable Bit
0
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTEN1
PDMA Channel n Time-out Enable Bit
1
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTIEN
PDMA_TOUTIEN
PDMA Time-out Interrupt Enable Register
0x438
-1
read-write
n
0x0
0x0
TOUTIEN0
PDMA Channel n Time-out Interrupt Enable Bit
0
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTIEN1
PDMA Channel n Time-out Interrupt Enable Bit
1
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTPSC
PDMA_TOUTPSC
PDMA Time-out Prescaler Register
0x430
-1
read-write
n
0x0
0x0
TOUTPSC0
PDMA Channel 0 Time-out Clock Source Prescaler Bits
0
3
read-write
0
PDMA channel 0 time-out clock source is HCLK/28
#000
1
PDMA channel 0 time-out clock source is HCLK/29
#001
2
PDMA channel 0 time-out clock source is HCLK/210
#010
3
PDMA channel 0 time-out clock source is HCLK/211
#011
4
PDMA channel 0 time-out clock source is HCLK/212
#100
5
PDMA channel 0 time-out clock source is HCLK/213
#101
6
PDMA channel 0 time-out clock source is HCLK/214
#110
7
PDMA channel 0 time-out clock source is HCLK/215
#111
TOUTPSC1
PDMA Channel 1 Time-out Clock Source Prescaler Bits
4
3
read-write
0
PDMA channel 1 time-out clock source is HCLK/28
#000
1
PDMA channel 1 time-out clock source is HCLK/29
#001
2
PDMA channel 1 time-out clock source is HCLK/210
#010
3
PDMA channel 1 time-out clock source is HCLK/211
#011
4
PDMA channel 1 time-out clock source is HCLK/212
#100
5
PDMA channel 1 time-out clock source is HCLK/213
#101
6
PDMA channel 1 time-out clock source is HCLK/214
#110
7
PDMA channel 1 time-out clock source is HCLK/215
#111
TRGSTS
PDMA_TRGSTS
PDMA Channel Request Status Register
0x40C
-1
read-only
n
0x0
0x0
REQSTS0
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
0
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS1
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
1
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS2
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
2
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS3
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
3
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS4
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
4
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS5
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
5
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS6
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
6
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS7
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
7
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS8
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
8
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS9
PDMA Channel n Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When the PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
9
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
SCS
SYST_SCS Register Map
SYST_SCS
0x0
0x10
0xC
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
System Reset Request
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.
The bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit
Reserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
1
1
read-write
VECTORKEY
Register Access Key
Write Operation:
When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
Read Operation:
Read as 0xFA05.
16
16
read-write
CPUID
CPUID
CPUID Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
Implementer Code Assigned by Arm
24
8
read-only
PART
Architecture of the Processor
Read as 0xC for Armv6-M parts.
16
4
read-only
PARTNO
Part Number of the Processor
Read as 0xC20.
4
12
read-only
REVISION
Revision Number
Read as 0x0.
0
4
read-only
ICSR
ICSR
Interrupt Control and State Register
0xD04
-1
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)
If Set, a Pending Exception Will Be Serviced on Exit From the Debug Halt State
23
1
read-only
NMIPENDSET
NMI Set-pending Bit
Write Operation:
Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.
NMI exception not pending
#0
1
Changes NMI exception state to pending.
NMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write Operation:
This is a write only bit. When you want to clear PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit
Write Operation:
26
1
read-write
0
No effect.
SysTick exception is not pending
#0
1
Changes SysTick exception state to pending.
SysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write Operation:
This is a write only bit. When you want to clear PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit
Write Operation:
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.
PendSV exception is not pending
#0
1
Changes PendSV exception state to pending.
PendSV exception is pending
#1
VECTACTIVE
Number of the Current Active Exception
0
6
read-write
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception
12
6
read-write
0
No pending exceptions
0
SCR
SCR
System Control Register
0xD10
-1
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending Bit
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection
Controls whether the processor uses sleep or deep sleep as its low power mode:
2
1
read-write
0
Sleep mode
#0
1
Deep Sleep mode
#1
SLEEPONEXIT
Sleep-on-exit Enable Bit
This bit indicates sleep-on-exit when returning from Handler mode to Thread mode.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter Sleep or Deep Sleep when returning from ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
-1
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
'0' denotes the highest priority and '3' denotes the lowest priority
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
-1
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
'0' denotes the highest priority and '3' denotes the lowest priority
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
'0' denotes the highest priority and '3' denotes the lowest priority
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag
Returns 1 if timer counted to 0 since last time this register is read.
COUNTFLAG is set by a count transition from 1 to 0.
COUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
CURRENT
System Tick Current Value
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x60
0xC
registers
n
SPIx_CLKDIV
SPIx_CLKDIV
SPI Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note: Not supported in I2S mode.
0
8
read-write
SPIx_CTL
SPIx_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer.
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width
This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
Note: This bit is for Master mode only.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
Note: This bit field is for Master mode only.
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPIx_FIFOCTL
SPIx_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is greater than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
2
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity
Note:
1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
2. This bit should be set as 0 in I2S mode.
3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPIx_I2SCLK
SPIx_I2SCLK
I2S Clock Divider Control Register
0x64
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
8
9
read-write
MCLKDIV
Master Clock Divider
If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
0
6
read-write
SPIx_I2SCTL
SPIx_I2SCTL
I2S Control Register
0x60
-1
read-write
n
0x0
0x0
FORMAT
Data Format Selection
28
2
read-write
0
I2S data format
#00
1
MSB justified data format
#01
2
PCM mode A
#10
3
PCM mode B
#11
I2SEN
I2S Controller Enable Bit
Note:
1. If this bit is enabled, I2Sx_BCLK will start to output in Master mode.
2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
0
1
read-write
0
I2S mode Disabled
#0
1
I2S mode Enabled
#1
LZCEN
Left Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
17
1
read-write
0
Left channel zero cross detection Disabled
#0
1
Left channel zero cross detection Enabled
#1
LZCIEN
Left Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MCLKEN
Master Clock Enable Bit
If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
ORDER
Stereo Data Order in FIFO
7
1
read-write
0
Left channel data at high byte
#0
1
Left channel data at low byte
#1
RXEN
Receive Enable Bit
2
1
read-write
0
Data receive Disabled
#0
1
Data receive Enabled
#1
RXLCH
Receive Left Channel Enable Bit
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RZCEN
Right Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
16
1
read-write
0
Right channel zero cross detection Disabled
#0
1
Right channel zero cross detection Enabled
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SLAVE
Slave Mode
I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXEN
Transmit Enable Bit
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
WDWIDTH
Word Width
4
2
read-write
0
Data size is 8-bit
#00
1
Data size is 16-bit
#01
2
Data size is 24-bit
#10
3
Data size is 32-bit
#11
SPIx_I2SSTS
SPIx_I2SSTS
I2S Status Register
0x68
-1
read-write
n
0x0
0x0
I2SENSTS
I2S Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
15
1
read-only
0
SPI/I2S control logic Disabled
#0
1
SPI/I2S control logic Enabled
#1
LZCIF
Left Channel Zero Cross Interrupt Flag
21
1
read-write
0
No zero cross event occurred on left channel
#0
1
Zero cross event occurred on left channel
#1
RIGHT
Right Channel (Read Only)
This bit indicates the current transmit data is belong to which channel.
4
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
3
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is less than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is greater than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
RZCIF
Right Channel Zero Cross Interrupt Flag
20
1
read-write
0
No zero cross event occurred on right channel
#0
1
Zero cross event occurred on right channel
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
3
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is greater than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
19
1
read-write
SPIx_PDMACTL
SPIx_PDMACTL
SPI PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit
Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPIx_RX
SPIx_RX
SPI Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register
There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SPIx_SSCTL
SPIx_SSCTL
SPI Slave Select Control Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit
Note: This bit is for Master mode only.
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control
If AUTOSS bit is cleared to 0,
Note: This bit is for Master mode only.
0
1
read-write
0
set the SPIx_SS line to inactive state.
Keep the SPIx_SS line at inactive state
#0
1
set the SPIx_SS line to active state.
SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal (SPIx_SS).
2
1
read-write
0
The slave selection signal SPIx_SS is active low
#0
1
The slave selection signal SPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPIx_STATUS
SPIx_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is less than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer greater than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
SPI controller Disabled
#0
1
SPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is greater than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPIx_TX
SPIx_TX
SPI Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SPI1
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x60
0xC
registers
n
SPIx_CLKDIV
SPIx_CLKDIV
SPI Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note: Not supported in I2S mode.
0
8
read-write
SPIx_CTL
SPIx_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer.
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width
This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
Note: This bit is for Master mode only.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
Note: This bit field is for Master mode only.
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPIx_FIFOCTL
SPIx_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is greater than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
2
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity
Note:
1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
2. This bit should be set as 0 in I2S mode.
3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPIx_I2SCLK
SPIx_I2SCLK
I2S Clock Divider Control Register
0x64
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
8
9
read-write
MCLKDIV
Master Clock Divider
If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
0
6
read-write
SPIx_I2SCTL
SPIx_I2SCTL
I2S Control Register
0x60
-1
read-write
n
0x0
0x0
FORMAT
Data Format Selection
28
2
read-write
0
I2S data format
#00
1
MSB justified data format
#01
2
PCM mode A
#10
3
PCM mode B
#11
I2SEN
I2S Controller Enable Bit
Note:
1. If this bit is enabled, I2Sx_BCLK will start to output in Master mode.
2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
0
1
read-write
0
I2S mode Disabled
#0
1
I2S mode Enabled
#1
LZCEN
Left Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
17
1
read-write
0
Left channel zero cross detection Disabled
#0
1
Left channel zero cross detection Enabled
#1
LZCIEN
Left Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MCLKEN
Master Clock Enable Bit
If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
ORDER
Stereo Data Order in FIFO
7
1
read-write
0
Left channel data at high byte
#0
1
Left channel data at low byte
#1
RXEN
Receive Enable Bit
2
1
read-write
0
Data receive Disabled
#0
1
Data receive Enabled
#1
RXLCH
Receive Left Channel Enable Bit
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RZCEN
Right Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
16
1
read-write
0
Right channel zero cross detection Disabled
#0
1
Right channel zero cross detection Enabled
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SLAVE
Slave Mode
I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXEN
Transmit Enable Bit
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
WDWIDTH
Word Width
4
2
read-write
0
Data size is 8-bit
#00
1
Data size is 16-bit
#01
2
Data size is 24-bit
#10
3
Data size is 32-bit
#11
SPIx_I2SSTS
SPIx_I2SSTS
I2S Status Register
0x68
-1
read-write
n
0x0
0x0
I2SENSTS
I2S Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
15
1
read-only
0
SPI/I2S control logic Disabled
#0
1
SPI/I2S control logic Enabled
#1
LZCIF
Left Channel Zero Cross Interrupt Flag
21
1
read-write
0
No zero cross event occurred on left channel
#0
1
Zero cross event occurred on left channel
#1
RIGHT
Right Channel (Read Only)
This bit indicates the current transmit data is belong to which channel.
4
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
3
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is less than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is greater than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
RZCIF
Right Channel Zero Cross Interrupt Flag
20
1
read-write
0
No zero cross event occurred on right channel
#0
1
Zero cross event occurred on right channel
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
3
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is greater than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
19
1
read-write
SPIx_PDMACTL
SPIx_PDMACTL
SPI PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit
Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPIx_RX
SPIx_RX
SPI Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register
There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SPIx_SSCTL
SPIx_SSCTL
SPI Slave Select Control Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit
Note: This bit is for Master mode only.
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control
If AUTOSS bit is cleared to 0,
Note: This bit is for Master mode only.
0
1
read-write
0
set the SPIx_SS line to inactive state.
Keep the SPIx_SS line at inactive state
#0
1
set the SPIx_SS line to active state.
SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal (SPIx_SS).
2
1
read-write
0
The slave selection signal SPIx_SS is active low
#0
1
The slave selection signal SPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPIx_STATUS
SPIx_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is less than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer greater than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
SPI controller Disabled
#0
1
SPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is greater than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPIx_TX
SPIx_TX
SPI Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x114
0x4
registers
n
0x18
0x8
registers
n
0x24
0x4
registers
n
0x30
0x20
registers
n
0x58
0x8
registers
n
0x80
0xC
registers
n
0xC0
0x4
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODDGSEL
Brown-out Detector Output De-glitch Time Select (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
BOD output is sampled by RC10K clock
#000
1
4 system clock (HCLK)
#001
2
8 system clock (HCLK)
#010
3
16 system clock (HCLK)
#011
4
32 system clock (HCLK)
#100
5
64 system clock (HCLK)
#101
6
128 system clock (HCLK)
#110
7
256 system clock (HCLK)
#111
BODEN
Brown-out Detector Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [23]).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag
Note: This bit can be cleared by software writing 1.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)
Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
BOD operated in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status
It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function is disabled. This bit always responds 0.
6
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.
Note 1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)
The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]).
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
1
2
read-write
0
Brown-Out Detector threshold voltage is 2.2V
#00
1
Brown-Out Detector threshold voltage is 2.7V
#01
2
Brown-Out Detector threshold voltage is 3.7V
#10
3
Brown-Out Detector threshold voltage is 4.5V
#11
LVRDGSEL
LVR Output De-glitch Time Select (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
12
3
read-write
0
Without de-glitch function
#000
1
4 system clock (HCLK)
#001
2
8 system clock (HCLK)
#010
3
16 system clock (HCLK)
#011
4
32 system clock (HCLK)
#100
5
64 system clock (HCLK)
#101
6
128 system clock (HCLK)
#110
7
256 system clock (HCLK)
#111
LVREN
Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note 1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
VDETDGSEL
Voltage Detector Output De-glitch Time Select (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
25
3
read-write
0
VDET output is sampled by VDET clock
#000
1
16 system clock (HCLK)
#001
2
32 system clock (HCLK)
#010
3
64 system clock (HCLK)
#011
4
128 system clock (HCLK)
#100
5
256 system clock (HCLK)
#101
6
512 system clock (HCLK)
#110
7
1024 system clock (HCLK)
#111
VDETEN
Voltage Detector Enable Bit
Note 1: This function is still active in whole chip Power-down mode.
Note 2: This function need use LIRC or LXT as VDET clock source, which is selected in VDETCKSEL (CLK_BODCLK[0]).
Note2: The input pin for VDET detect voltage is selectable by VDETPINSEL (SYS_BODCTL[17]).
16
1
read-write
0
VDET detect external input voltage function Disabled
#0
1
VDET detect external input voltage function Enabled
#1
VDETIEN
Voltage Detector Interrupt Enable Bit
18
1
read-write
0
VDET interrupt Disabled
#0
1
VDET interrupt Enabled
#1
VDETIF
Voltage Detector Interrupt Flag
Note: This bit can be cleared by software writing 1.
19
1
read-write
0
VDET does not detect any voltage draft at external pin down through or up through the voltage of Band-gap
#0
1
When VDET detects the external pin is dropped down through the voltage of Band-gap or the external pin is raised up through the voltage of Band-gap, this bit is set to 1 and the voltage detector interrupt is requested if voltage detector interrupt is enabled
#1
VDETOUT
Voltage Detector Output Status
It means the detected voltage is lower than Band-gap. If the VDETEN is 0, VDET function is disabled. This bit always responds 0.
24
1
read-write
0
VDET output status is 0
#0
1
VDET output status is 1
#1
VDETPINSEL
Voltage Detector External Input Voltage Pin Selection
Note 1: If VDET_P0 is selected, multi-function pin must be selected correctly in PB0MFP (SYS_GPB_MFPL[3:0]).
Note 2: If VDET_P1 is selected, multi-function pin must be selected correctly in PB1MFP (SYS_GPB_MFPL[7:4]).
17
1
read-write
0
The input voltage is from VDET_P0 (PB.0)
#0
1
The input voltage is from VDET_P1 (PB.1)
#1
GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multiple Function Control Register
0x34
-1
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
4
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
4
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
4
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
4
read-write
GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multiple Function Control Register
0x30
-1
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
4
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
4
read-write
GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multiple Function Control Register
0x3C
-1
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
4
read-write
GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multiple Function Control Register
0x38
-1
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFPH
SYS_GPC_MFPH
GPIOC High Byte Multiple Function Control Register
0x44
-1
read-write
n
0x0
0x0
PC14MFP
PC14 Multi-function Pin Selection
24
4
read-write
GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multiple Function Control Register
0x40
-1
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
4
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
4
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
4
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
4
read-write
GPD_MFPH
SYS_GPD_MFPH
GPIOD High Byte Multiple Function Control Register
0x4C
-1
read-write
n
0x0
0x0
PD15MFP
PD.15 Multi-function Pin Selection
28
4
read-write
GPD_MFPL
SYS_GPD_MFPL
GPIOD Low Byte Multiple Function Control Register
0x48
-1
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
4
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
4
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
4
read-write
PD3MFP
PD.3 Multi-function Pin Selection
12
4
read-write
GPF_MFPH
SYS_GPF_MFPH
GPIOF High Byte Multiple Function Control Register
0x5C
-1
read-write
n
0x0
0x0
PF14MFP
PF.14 Multi-function Pin Selection
24
4
read-write
PF15MFP
PF.15 Multi-function Pin Selection
28
4
read-write
GPF_MFPL
SYS_GPF_MFPL
GPIOF Low Byte Multiple Function Control Register
0x58
-1
read-write
n
0x0
0x0
PF0MFP
PF.0 Multi-function Pin Selection
0
4
read-write
PF1MFP
PF.1 Multi-function Pin Selection
4
4
read-write
PF2MFP
PF.2 Multi-function Pin Selection
8
4
read-write
PF3MFP
PF.3 Multi-function Pin Selection
12
4
read-write
PF4MFP
PF.4 Multi-function Pin Selection
16
4
read-write
PF5MFP
PF.5 Multi-function Pin Selection
20
4
read-write
PF6MFP
PF.6 Multi-function Pin Selection
24
4
read-write
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.
About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller (FMC), and this bit will automatically return to 0 after the 2 clock cycles.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Calculation Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CRC calculation controller normal operation
#0
1
CRC calculation controller reset
#1
PDMARST
PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
-1
read-write
n
0x0
0x0
ADCRST
ADC Controller Reset
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
BPWM0RST
BPWM0 Controller Reset
20
1
read-write
0
BPWM0 controller normal operation
#0
1
BPWM0 controller reset
#1
BPWM1RST
BPWM1 Controller Reset
21
1
read-write
0
BPWM1 controller normal operation
#0
1
BPWM1 controller reset
#1
BPWM2RST
BPWM2 Controller Reset
22
1
read-write
0
BPWM2 controller normal operation
#0
1
BPWM2 controller reset
#1
BPWM3RST
BPWM3 Controller Reset
23
1
read-write
0
BPWM3 controller normal operation
#0
1
BPWM3 controller reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
SPI0RST
SPI0 Controller Reset
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1RST
SPI1 Controller Reset
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
USBDRST
USB Device Controller Reset
27
1
read-write
0
USB device controller normal operation
#0
1
USB device controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Reset Control Register 2
0x10
-1
read-write
n
0x0
0x0
LLSI0RST
LLSI0 Controller Reset
16
1
read-write
0
LED Lighting Strip Interface 0 controller normal operation
#0
1
LED Lighting Strip Interface 0 controller reset
#1
LLSI1RST
LLSI1 Controller Reset
17
1
read-write
0
LED Lighting Strip Interface 1 controller normal operation
#0
1
LED Lighting Strip Interface 1 controller reset
#1
LLSI2RST
LLSI2 Controller Reset
18
1
read-write
0
LED Lighting Strip Interface 2 controller normal operation
#0
1
LED Lighting Strip Interface 2 controller reset
#1
LLSI3RST
LLSI3 Controller Reset
19
1
read-write
0
LED Lighting Strip Interface 3 controller normal operation
#0
1
LED Lighting Strip Interface 3 controller reset
#1
LLSI4RST
LLSI4 Controller Reset
20
1
read-write
0
LED Lighting Strip Interface 4 controller normal operation
#0
1
LED Lighting Strip Interface 4 controller reset
#1
LLSI5RST
LLSI5 Controller Reset
21
1
read-write
0
LED Lighting Strip Interface 5 controller normal operation
#0
1
LED Lighting Strip Interface 5 controller reset
#1
LLSI6RST
LLSI6 Controller Reset
22
1
read-write
0
LED Lighting Strip Interface 6 controller normal operation
#0
1
LED Lighting Strip Interface 6 controller reset
#1
LLSI7RST
LLSI7 Controller Reset
23
1
read-write
0
LED Lighting Strip Interface 7 controller normal operation
#0
1
LED Lighting Strip Interface 7 controller reset
#1
LLSI8RST
LLSI8 Controller Reset
24
1
read-write
0
LED Lighting Strip Interface 8 controller normal operation
#0
1
LED Lighting Strip Interface 8 controller reset
#1
LLSI9RST
LLSI9 Controller Reset
25
1
read-write
0
LED Lighting Strip Interface 9 controller normal operation
#0
1
LED Lighting Strip Interface 9 controller reset
#1
IRCTCTL
SYS_IRCTCTL
HIRC Trim Control Register
0x80
-1
read-write
n
0x0
0x0
BOUNDARY
Boundary Selection
Fill the boundary range from 0x1 to 0x1F, 0x0 is reserved.
Note: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled.
16
5
read-write
BOUNDEN
Boundary Enable Bit
9
1
read-write
0
Boundary function Disabled
#0
1
Boundary function Enabled
#1
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation is keep going if clock is inaccurate
#0
1
The trim operation is stopped if clock is inaccurate
#1
FREQSEL
Trim Frequency Selection
This field indicates the target frequency of internal high speed RC oscillator (HIRC) auto trim.
During auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#01
2
Reserved.
#10
3
Reserved.
#11
LOOPSEL
Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many clocks of reference clock (32.768 kHz, LXT).
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks of reference clock
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection
10
1
read-write
0
HIRC trim reference clock is from LXT (32.768 kHz)
#0
1
HIRC trim reference clock is from USB synchronous mode packet
#1
RETRYCNT
Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
IRCTIEN
SYS_IRCTIEN
HIRC Trim Interrupt Enable Register
0x84
-1
read-write
n
0x0
0x0
CLKEIEN
HIRC Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while HIRC clock is inaccurate during auto trim operation.
If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate.
2
1
read-write
0
Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU
#1
TFAILIEN
HIRC Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count reached.
1
1
read-write
0
Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU
#1
IRCTISTS
SYS_IRCTISTS
HIRC Trim Interrupt Status Register
0x88
-1
read-write
n
0x0
0x0
CLKERRIF
Clock Error Interrupt Status
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and indicate that clock frequency is inaccurate.
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0.
2
1
read-write
0
Clock frequency is accurate
#0
1
Clock frequency is inaccurate
#1
FREQLOCK
HIRC Frequency Lock Status
This bit indicates the HIRC frequency is locked.
This is a status bit and does not trigger any interrupt.
0
1
read-write
0
The internal high-speed RC oscillator frequency is not locked at 48 MHz yet
#0
1
The internal high-speed RC oscillator frequency locked at 48 MHz
#1
TFAILIF
Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count reached. Write 1 to clear this to 0.
1
1
read-write
0
Trim value update limitation count not reached
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
IVSCTL
SYS_IVSCTL
Internal Voltage Source Control Register
0x1C
-1
read-write
n
0x0
0x0
VBGUGEN
Band-gap VBG Unity Gain Buffer Enable Bit
This bit is used to enable/disable Band-gap VBG unity gain buffer function.
Note: After this bit is set to 1, the value of VBG unity gain buffer output voltage can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
1
1
read-write
0
VBG unity gain buffer function Disabled (default)
#0
1
VBG unity gain buffer function Enabled
#1
VTEMPEN
Temperature Sensor Enable Bit
This bit is used to enable/disable temperature sensor function.
Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
MODCTL
SYS_MODCTL
Modulation Control Register
0xC0
-1
read-write
n
0x0
0x0
MODEN
Modulation Function Enable Bit
This bit enables modulation function by modulating with BPWM channel output and UART1_TXD.
0
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MODH
Modulation at Data High
Select modulation pulse (BPWM) at UART1_TXD high or low.
1
1
read-write
0
Modulation pulse at UART1_TXD low
#0
1
Modulation pulse at UART1_TXD high
#1
MODPWMSEL
BPWM0 Channel Select for Modulation
Select the BPWM0 channel to modulate with the UART1_TXD.
Note: These bits are valid while MODEN (SYS_MODCTL[0]) is set to 1.
4
3
read-write
0
BPWM0 channel 0 modulate with UART1_TXD
#000
1
BPWM0 channel 1 modulate with UART1_TXD
#001
2
BPWM0 channel 2 modulate with UART1_TXD
#010
3
BPWM0 channel 3 modulate with UART1_TXD
#011
PDID
SYS_PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)
This register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
PORCTL
SYS_PORCTL
Power-on Reset Controller Register
0x24
-1
read-write
n
0x0
0x0
POROFF
Power-on Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Code
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
1
7
read-write
REGLCTL0
Register Lock Control Disable Index
The Protected registers are:
SYS_IPRST0: address 0x5000_0008
SYS_BODCTL: address 0x5000_0018
SYS_PORCTL: address 0x5000_0024
SYS_SRAM_BISTCTL: address 0x5000_00D0
CLK_PWRCTL: address 0x5000_0200
CLK_APBCLK0: address 0x5000_0208
CLK_CLKSEL0: address 0x5000_0210
CLK_CLKSEL1: address 0x5000_0214
CLK_CLKSEL3: address 0x5000_0234
CLK_CLKDSTS: address 0x5000_0274
FMC_ISPCTL: address 0x5000_C000 (Flash ISP Control register)
FMC_ISPTRG: address 0x5000_C010 (ISP Trigger Control register)
FMC_FTCTL: address 0x5000_C018
FMC_ISPSTS: address 0x5000_C040
WDT_CTL: address 0x4000_4000
BPWM0_CTL0: address 0x4004_0000
BPWM1_CTL0: address 0x4014_0000
BPWM2_CTL0: address 0x4004_4000
BPWM3_CTL0: address 0x4014_4000
TIMER0_CTL: address 0x4001_0000
TIMER1_CTL: address 0x4001_0020
TIMER2_CTL: address 0x4011_0000
TIMER3_CTL: address 0x4011_0020
0
1
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
#0
1
Write-protection Disabled for writing protected registers
#1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.
Note: This bit can be cleared by software writing 1.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPULKRF
CPU Lockup Reset Flag
The CPU lockup reset flag is set by hardware If Cortex-M23 lockup happened.
Note 1: This bit can be cleared by software writing 1.
Note 2: When CPU lockup happened under ICE is connected, this flag will be set to 1 but chip will not reset.
8
1
read-write
0
No reset from CPU lockup happened
#0
1
The Cortex-M23 lockup happened and chip is reset
#1
CPURF
CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC).
Note: This bit can be cleared by software writing 1.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M23 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.
Note: This bit can be cleared by software writing 1.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
MCURF
MCU Reset Flag
The MCU reset flag is set by the 'Reset Signal' from the Cortex-M23 Core to indicate the previous reset source.
Note: This bit can be cleared by software writing 1.
5
1
read-write
0
No reset from Cortex-M23
#0
1
The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core
#1
PINRF
nRESET Pin Reset Flag
The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.
Note: This bit can be cleared by software writing 1.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: This bit can be cleared by software writing 1.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note 1: This bit can be cleared by software writing 1.
Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
TSOFFSET
SYS_TSOFFSET
Temperature Sensor Offset Register
0x114
-1
read-only
n
0x0
0x0
VTEMP
Temperature Sensor Offset Value (Read Only)
This field reflects temperature sensor output voltage offset at 25oC from Flash.
0
12
read-only
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from LIRC
#1
CNTEN
Timer Counting Enable Bit
Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note 2: When Timer/Timer INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter
Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
Note: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM01
Trigger BPWM01 Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM01.
19
1
read-write
0
Timer interrupt trigger BPWM01 Disabled
#0
1
Timer interrupt trigger BPWM01 Enabled
#1
TRGBPWM23
Trigger BPWM23 Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM23.
9
1
read-write
0
Timer interrupt trigger BPWM23 Disabled
#0
1
Timer interrupt trigger BPWM23 Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger BPWM, ADC and PDMA
#0
1
Capture interrupt signal is used to trigger BPWM, ADC and PDMA
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer Capture Interrupt Flag
This bit indicates the timer capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin or LIRC capture interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin or LIRC capture interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on TMx_EXT (x= 0~3) pin or LIRC will be detected
#00
1
A Rising edge on TMx_EXT (x= 0~3) pin or LIRC will be detected
#01
2
Either Rising or Falling edge on TMx_EXT (x= 0~3) pin or LIRC will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
Capture Mode Enabled
#0
1
Capture and Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin or LIRC detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin or LIRC detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matched the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer did not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x30
-1
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Comparator Register
0x24
-1
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
-1
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control Register
0x20
-1
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x38
-1
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
-1
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER2_CTL
TIMER2_CTL
Timer2 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from LIRC
#1
CNTEN
Timer Counting Enable Bit
Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note 2: When Timer/Timer INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter
Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
Note: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM01
Trigger BPWM01 Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM01.
19
1
read-write
0
Timer interrupt trigger BPWM01 Disabled
#0
1
Timer interrupt trigger BPWM01 Enabled
#1
TRGBPWM23
Trigger BPWM23 Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM23.
9
1
read-write
0
Timer interrupt trigger BPWM23 Disabled
#0
1
Timer interrupt trigger BPWM23 Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger BPWM, ADC and PDMA
#0
1
Capture interrupt signal is used to trigger BPWM, ADC and PDMA
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer Capture Interrupt Flag
This bit indicates the timer capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin or LIRC capture interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin or LIRC capture interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on TMx_EXT (x= 0~3) pin or LIRC will be detected
#00
1
A Rising edge on TMx_EXT (x= 0~3) pin or LIRC will be detected
#01
2
Either Rising or Falling edge on TMx_EXT (x= 0~3) pin or LIRC will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
Capture Mode Enabled
#0
1
Capture and Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin or LIRC detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin or LIRC detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matched the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer did not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x30
-1
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Comparator Register
0x24
-1
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x2C
-1
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control Register
0x20
-1
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x38
-1
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x28
-1
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note: The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note: This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in Table 6.113.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in Table 6.113.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation.
Note: The detailed description is shown in Table 6.113.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.113.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing 1 to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing 1 to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing 1 to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).
Note: This bit can be cleared by writing 1 to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit can be cleared by writing 1 to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
Note: This bit can be cleared by writing 1 to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing 1 to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing 1 to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
2
read-write
0
UART function
#00
1
Reserved.
#01
2
IrDA function
#10
3
RS-485 function
#11
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not disable immediately when this bit is set. The TX and RX complete current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
This bit can enable or disable TX PDMA service.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated.
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag (Read Only)
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-only
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
Note: In IrDA mode, the BAUDM1 (UART_BAUD [29]) register must be disabled, the baud equation must be Clock / (16 * (BRD + 2)).
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit
Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection
The parity bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode.
Note 2: Refer to Figure 6.1117 and Figure 6.1118 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing 1 to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled. When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode
#1
WKDATEN
Incoming Data Wake-up Enable Bit
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake up system from Power-down mode
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled. When the system is in Power-down mode, Received Data FIFO reached threshold will wake up system from Power-down mode
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up
#1
UART1
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note: The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note: This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in Table 6.113.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in Table 6.113.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation.
Note: The detailed description is shown in Table 6.113.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.113.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]).
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing 1 to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing 1 to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing 1 to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).
Note: This bit can be cleared by writing 1 to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit can be cleared by writing 1 to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
Note: This bit can be cleared by writing 1 to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing 1 to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer is equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing 1 to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer is equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
DGE
Deglitch Enable Bit
Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter logic.
Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps.
6
1
read-write
0
Deglitch Disabled
#0
1
Deglitch Enabled
#1
FUNCSEL
Function Select
0
2
read-write
0
UART function
#00
1
Reserved.
#01
2
IrDA function
#10
3
RS-485 function
#11
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not disable immediately when this bit is set. The TX and RX complete current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
This bit can enable or disable TX PDMA service.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag (Read Only)
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-only
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
Note: In IrDA mode, the BAUDM1 (UART_BAUD [29]) register must be disabled, the baud equation must be Clock / (16 * (BRD + 2)).
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit
Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection
The parity bit can be selected to be generated and checked automatically or by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode.
Note 2: Refer to Figure 6.1117 and Figure 6.1118 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing 1 to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled. When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode
#1
WKDATEN
Incoming Data Wake-up Enable Bit
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake up system from Power-down mode
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled. When the system is in Power-down mode, Received Data FIFO reached threshold will wake up system from Power-down mode
#1
WKRS485EN
RS-485 Address Match Wake-up Enable Bit
Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .
Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up
#1
USBD
USBD Register Map
USBD
0x0
0x0
0x1C
registers
n
0x500
0x80
registers
n
0x88
0xC
registers
n
ATTR
USBD_ATTR
USB Device Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPUEN
Pull-up Resistor on USB_DP Enable Bit
8
1
read-write
0
Pull-up resistor in USB_D+ bus Disabled
#0
1
Pull-up resistor in USB_D+ bus Active
#1
L1RESUME
LPM L1 Resume (Read Only)
13
1
read-only
0
Bus no LPM L1 state resume
#0
1
LPM L1 state resume from LPM L1 state suspend
#1
L1SUSPEND
LPM L1 Suspend (Read Only)
12
1
read-only
0
Bus no L1 state suspend
#0
1
This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged
#1
LPMACK
LPM Token Acknowledge Enable Bit
11
1
read-write
0
The valid LPM Token will be NYET
#0
1
The valid LPM Token will be ACK
#1
PHYEN
PHY Transceiver Function Enable Bit
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-down PHY Transceiver, Low Active
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn-on related circuit of PHY transceiver
#1
RESUME
Resume Status (Read Only)
2
1
read-only
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status (Read Only)
1
1
read-only
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged out or host is sleeping
#1
TOUT
Time-out Status (Read Only)
3
1
read-only
0
No time-out
#0
1
No Bus response more than 18 bits time(
#1
USBEN
USB Controller Enable Bit
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USBRST
USB Reset Status (Read Only)
0
1
read-only
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
BUFSEG0
USBD_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x500
-1
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:
USBD_SRAM address + { BUFSEG, 3'b000}
Refer to the Buffer Control section for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USBD_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x510
-1
read-write
n
0x0
0x0
BUFSEG2
USBD_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x520
-1
read-write
n
0x0
0x0
BUFSEG3
USBD_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x530
-1
read-write
n
0x0
0x0
BUFSEG4
USBD_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x540
-1
read-write
n
0x0
0x0
BUFSEG5
USBD_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x550
-1
read-write
n
0x0
0x0
BUFSEG6
USBD_BUFSEG6
Endpoint 6 Buffer Segmentation Register
0x560
-1
read-write
n
0x0
0x0
BUFSEG7
USBD_BUFSEG7
Endpoint 7 Buffer Segmentation Register
0x570
-1
read-write
n
0x0
0x0
CFG0
USBD_CFG0
Endpoint 0 Configuration Register
0x508
-1
read-write
n
0x0
0x0
CSTALL
Clear STALL Response
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQSYNC
Data Sequence Synchronization
Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EPNUM
Endpoint Number
These bits are used to define the endpoint number of the current endpoint.
0
4
read-write
ISOCH
Isochronous Endpoint
This bit is used to set the endpoint as Isochronous endpoint, no handshake.
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint State
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USBD_CFG1
Endpoint 1 Configuration Register
0x518
-1
read-write
n
0x0
0x0
CFG2
USBD_CFG2
Endpoint 2 Configuration Register
0x528
-1
read-write
n
0x0
0x0
CFG3
USBD_CFG3
Endpoint 3 Configuration Register
0x538
-1
read-write
n
0x0
0x0
CFG4
USBD_CFG4
Endpoint 4 Configuration Register
0x548
-1
read-write
n
0x0
0x0
CFG5
USBD_CFG5
Endpoint 5 Configuration Register
0x558
-1
read-write
n
0x0
0x0
CFG6
USBD_CFG6
Endpoint 6 Configuration Register
0x568
-1
read-write
n
0x0
0x0
CFG7
USBD_CFG7
Endpoint 7 Configuration Register
0x578
-1
read-write
n
0x0
0x0
CFGP0
USBD_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x50C
-1
read-write
n
0x0
0x0
CLRRDY
Clear Ready
When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
This bit is write 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USBD_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x51C
-1
read-write
n
0x0
0x0
CFGP2
USBD_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x52C
-1
read-write
n
0x0
0x0
CFGP3
USBD_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x53C
-1
read-write
n
0x0
0x0
CFGP4
USBD_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x54C
-1
read-write
n
0x0
0x0
CFGP5
USBD_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x55C
-1
read-write
n
0x0
0x0
CFGP6
USBD_CFGP6
Endpoint 6 Set Stall and Clear In/Out Ready Control Register
0x56C
-1
read-write
n
0x0
0x0
CFGP7
USBD_CFGP7
Endpoint 7 Set Stall and Clear In/Out Ready Control Register
0x57C
-1
read-write
n
0x0
0x0
EPSTS
USBD_EPSTS
USB Device Endpoint Status Register
0xC
-1
read-only
n
0x0
0x0
EPSTS0
Endpoint 0 Status
These bits are used to indicate the current status of this endpoint
8
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS1
Endpoint 1 Status
These bits are used to indicate the current status of this endpoint
11
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS2
Endpoint 2 Status
These bits are used to indicate the current status of this endpoint
14
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS3
Endpoint 3 Status
These bits are used to indicate the current status of this endpoint
17
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS4
Endpoint 4 Status
These bits are used to indicate the current status of this endpoint
20
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS5
Endpoint 5 Status
These bits are used to indicate the current status of this endpoint
23
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS6
Endpoint 6 Status
These bits are used to indicate the current status of this endpoint
26
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS7
Endpoint 7 Status
These bits are used to indicate the current status of this endpoint
29
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
OV
Overrun
It indicates that the received data is more than the maximum payload number or not.
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
FADDR
USBD_FADDR
USB Device Function Address Register
0x8
-1
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FN
USBD_FN
USB Frame Number Register
0x8C
-1
read-only
n
0x0
0x0
FN
Frame Number
These bits contain the 11-bits frame number in the last received SOF packet.
0
11
read-only
INTEN
USBD_INTEN
USB Device Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BUSIEN
Bus Event Interrupt Enable Bit
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
INNAKEN
Active NAK Function and Its Status in IN Token
15
1
read-write
0
When the device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted when the device responds NAK after receiving IN token
#1
NEVWKIEN
USB No-event-wake-up Interrupt Enable Bit
3
1
read-write
0
No-event-wake-up Interrupt Disabled
#0
1
No-event-wake-up Interrupt Enabled
#1
SOFIEN
Start of Frame Interrupt Enable Bit
4
1
read-write
0
SOF Interrupt Disabled
#0
1
SOF Interrupt Enabled
#1
USBIEN
USB Event Interrupt Enable Bit
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
VBDETIEN
VBUS Detection Interrupt Enable Bit
2
1
read-write
0
VBUS detection Interrupt Disabled
#0
1
VBUS detection Interrupt Enabled
#1
WKEN
Wake-up Function Enable Bit
Note: If woken up by any change by VBUS state, VBDETIEN must be enabled. If woken up by receiving resume signal, BUSIEN must be enabled.
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
INTSTS
USBD_INTSTS
USB Device Interrupt Event Status Register
0x4
-1
read-write
n
0x0
0x0
BUSIF
BUS Interrupt Status
The BUS event means that there is one of the suspense or the resume function in the bus.
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event occurred, and it is cleared by writing 1 to USBD_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USBD_EPSTS[10:8] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USBD_EPSTS[13:11] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USBD_EPSTS[19:17] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USBD_EPSTS[22:20] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USBD_EPSTS[25:23] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
#1
EPEVT6
Endpoint 6's USB Event Status
22
1
read-write
0
No event occurred in endpoint 6
#0
1
USB event occurred on Endpoint 6, check USBD_EPSTS[28:26] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1]
#1
EPEVT7
Endpoint 7's USB Event Status
23
1
read-write
0
No event occurred in endpoint 7
#0
1
USB event occurred on Endpoint 7, check USBD_EPSTS[31:29] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1]
#1
NEVWKIF
No-event-wake-up Interrupt Status
3
1
read-write
0
NEVWK event did not occur
#0
1
No-event-wake-up event occurred, and it is cleared by writing 1 to USBD_INTSTS[3]
#1
SETUP
Setup Event Status
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, and it is cleared by writing 1 to USBD_INTSTS[31]
#1
SOFIF
Start of Frame Interrupt Status
4
1
read-write
0
SOF event did not occur
#0
1
SOF event occurred, and it is cleared by writing 1 to USBD_INTSTS[4]
#1
USBIF
USB Event Interrupt Status
The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred check EPSTS0~7[2:0] to know which kind of USB event occurred, and it is cleared by writing 1 to USBD_INTSTS[1] or EPSTS0~7 and SETUP (USBD_INTSTS[31])
#1
VBDETIF
VBUS Detection Interrupt Status
2
1
read-write
0
There is no attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]
#1
LPMATTR
USBD_LPMATTR
USB LPM Attribution Register
0x88
-1
read-only
n
0x0
0x0
LPMBESL
LPM Best Effort Service Latency
These bits contain the BESL value received with last ACK LPM Token
4
4
read-only
LPMLINKSTS
LPM Link State
These bits contain the bLinkState received with last ACK LPM Token
0
4
read-only
LPMRWAKUP
LPM Remote Wake-up
This bit contains the bRemoteWake value received with last ACK LPM Token
8
1
read-only
MXPLD0
USBD_MXPLD0
Endpoint 0 Maximal Payload Register
0x504
-1
read-write
n
0x0
0x0
MXPLD
Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USBD_MXPLD1
Endpoint 1 Maximal Payload Register
0x514
-1
read-write
n
0x0
0x0
MXPLD2
USBD_MXPLD2
Endpoint 2 Maximal Payload Register
0x524
-1
read-write
n
0x0
0x0
MXPLD3
USBD_MXPLD3
Endpoint 3 Maximal Payload Register
0x534
-1
read-write
n
0x0
0x0
MXPLD4
USBD_MXPLD4
Endpoint 4 Maximal Payload Register
0x544
-1
read-write
n
0x0
0x0
MXPLD5
USBD_MXPLD5
Endpoint 5 Maximal Payload Register
0x554
-1
read-write
n
0x0
0x0
MXPLD6
USBD_MXPLD6
Endpoint 6 Maximal Payload Register
0x564
-1
read-write
n
0x0
0x0
MXPLD7
USBD_MXPLD7
Endpoint 7 Maximal Payload Register
0x574
-1
read-write
n
0x0
0x0
SE0
USBD_SE0
USB Device Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
SE0
Drive Single Ended Zero in USB Bus
The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0
1
read-write
0
Normal operation
#0
1
Force USB PHY transceiver to drive SE0
#1
STBUFSEG
USBD_STBUFSEG
SETUP Token Buffer Segmentation Register
0x18
-1
read-write
n
0x0
0x0
STBUFSEG
SETUP Token Buffer Segmentation
It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
USBD_SRAM address + {STBUFSEG, 3'b000}
Note: It is used for SETUP token only.
3
6
read-write
VBUSDET
USBD_VBUSDET
USB Device VBUS Detection Register
0x14
-1
read-only
n
0x0
0x0
VBUSDET
Device VBUS Detection
0
1
read-only
0
Controller is not attached to the USB host
#0
1
Controller is attached to the USB host
#1
WDT
WDT Register Map
WDT
0x0
0x0
0xC
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
-1
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Period Selection (Write Protect)
When WDT time-out event happened, user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred. User can select a suitable setting of RSTDSEL for application program.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This register will be reset to 0 if WDT time-out reset system event occurred.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag
This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt event did not occur
#0
1
WDT time-out interrupt event occurred
#1
INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)
If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and WDT time-out interrupt signal is generated and inform to CPU.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTEN
WDT Time-out Reset Enable Bit (Write Protect)
Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset system function Disabled
#0
1
WDT time-out reset system function Enabled
#1
RSTF
WDT Time-out Reset Flag
This bit indicates the system has been reset by WDT time-out reset system event or not.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset system event did not occur
#0
1
WDT time-out reset system event has been occurred
#1
SYNC
WDT Enable Control SYNC Flag Indicator (Read Only)
If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
30
1
read-only
0
Set WDTEN bit is completed
#0
1
Set WDTEN bit is synchronizing and not become active yet.
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protect)
These three bits select the time-out interval period after WDT starts counting.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
24 * WDT_CLK
#000
1
26 * WDT_CLK
#001
2
28 * WDT_CLK
#010
3
210 * WDT_CLK
#011
4
212 * WDT_CLK
#100
5
214 * WDT_CLK
#101
6
216 * WDT_CLK
#110
7
218 * WDT_CLK
#111
WDTEN
WDT Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enabe/disable command is completed or not.
Note 3: If CWDTEN[2:0] (combined with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
Set WDT counter stop, and internal up counter value will be reset also
#0
1
Set WDT counter start
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protect)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Chip can be woken up while WDT time-out interrupt signal is generated only if WDT clock source is selected to LIRC (10 kHz) or LXT (32 kHz).
4
1
read-write
0
Trigger wake-up event function Disabled if WDT time-out interrupt signal generated
#0
1
Trigger wake-up event function Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protect)
This bit indicates the WDT time-out event has triggered chip wake-up or not.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode when WDT time-out interrupt signal is generated
#1
RSTCNT
WDT_RSTCNT
WDT Reset Counter Register
0x8
-1
write-only
n
0x0
0x0
RSTCNT
WDT Reset Counter Register
Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
0
32
write-only
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value
CNTDAT will be updated continuously.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Value
Set this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT. If user writes 0x00005AA5 in WWDT_RLDCNT register when the current CNTDAT is greater than CMPDAT, WWDT reset system event will be generated immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit
The WWDT down counter will keep counting no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counter counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit
If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.
1
1
read-write
0
WWDT counter compare match interrupt disabled
#0
1
WWDT counter compare match interrupt enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Bit
Set this bit to start WWDT counter counting.
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter is starting counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
-1
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register
Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note 1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT (WWDT_CTL[21:16]). If user writes 0x00005AA5 in WWDT_RLDCNT register when the current CNTDAT is greater than CMPDAT, WWDT reset system event will be generated immediately.
Note 2: Executing WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
-1
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag
This bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16]).
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT CNTDAT matches the CMPDAT
#1
WWDTRF
WWDT Timer-out Reset System Flag
If this bit is set to 1, it indicates that system has been reset by WWDT counter time-out reset system event.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset system event did not occur
#0
1
WWDT time-out reset system event occurred
#1