nuvoTon NUC1311AE_v1 2024.04.27 NUC1311AE_v1 SVD file 8 32 ADC ADC Register Map ADC 0x0 0x0 0x30 registers n ADCHER ADCHER ADC Channel Enable Register 0x24 read-write n 0x0 0x0 CHEN Analog Input Channel Enable Control\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled.\n 0 8 read-write 0 ADC input channel Disabled 0 1 ADC input channel Enabled 1 PRESEL Analog Input Channel 7 Selection\n 8 2 read-write 0 External analog input #00 1 Internal band-gap voltage #01 2 Reserved #10 3 Reserved #11 ADCMPR0 ADCMPR0 ADC Compare Register 0 0x28 read-write n 0x0 0x0 CMPCH Compare Channel Selection\n 3 3 read-write 0 Channel 0 conversion result is selected to be compared #000 1 Channel 1 conversion result is selected to be compared #001 2 Channel 2 conversion result is selected to be compared #010 3 Channel 3 conversion result is selected to be compared #011 4 Channel 4 conversion result is selected to be compared #100 5 Channel 5 conversion result is selected to be compared #101 6 Channel 6 conversion result is selected to be compared #110 7 Channel 7 conversion result is selected to be compared #111 CMPCOND Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) + 1), the CMPF0/1 bit (ADSR[1]/[2]) will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one #1 CMPD Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit (ADCR[31]) is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit (ADCR[31]) is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format. 16 12 read-write CMPEN Compare Enable Control\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register. 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIE Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]), CMPF0/1 bit (ADSR[1]/[2]) will be asserted, in the meanwhile, if CMPIE (ADCMPR0/1[1]) is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]), the internal match counter will increase 1, The comparing data must successively matched with the compare condition. Once any comparing data does not match during the comparing, the internal counter will clear to 0. When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) +1), the CMPF0/1 bit (ADSR[1]/[2]) will be set. 8 4 read-write ADCMPR1 ADCMPR1 ADC Compare Register 1 0x2C read-write n 0x0 0x0 ADCR ADCR ADC Control Register 0x20 read-write n 0x0 0x0 ADEN A/D Converter Enable Control\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption. 0 1 read-write 0 Disabled #0 1 Enabled #1 ADIE A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1. 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit (ADCR[11]) firstly. 2 2 read-write 0 Single conversion #00 1 Reserved #01 2 Single-cycle scan #10 3 Continuous scan #11 ADST A/D Conversion Start\nADST bit can be set to 1 from three sources: software, PWM Center-aligned trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset. 11 1 read-write 0 Conversion stops and A/D converter enter idle state #0 1 Conversion starts #1 DIFFEN Differential Input Mode Control\n 10 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF A/D Differential Input Mode Output Format\n 31 1 read-write 0 A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format #0 1 A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format #1 TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN Hardware Trigger Enable Control\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode, the ADST bit (ADCR[11]) can be set to 1 by the selected hardware trigger source. 8 1 read-write 0 Disabled #0 1 Enabled #1 TRGS Hardware Trigger Source\nSoftware should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 3 A/D conversion is started by PWM Center-aligned trigger #11 ADDR0 ADDR0 ADC Data Register 0 0x0 read-only n 0x0 0x0 OVERRUN Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit. 16 1 read-only 0 Data in RSLT (ADDRx[15:0], x=0~7) is recent conversion result #0 1 Data in RSLT (ADDRx[15:0], x=0~7) is overwritten #1 RSLT A/D Conversion Result\nThis field contains conversion result of ADC.\n 0 16 read-only VALID Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit. 17 1 read-only 0 Data in RSLT bits (ADDRx[15:0], x=0~7) is not valid #0 1 Data in RSLT bits (ADDRx[15:0], x=0~7) is valid #1 ADDR1 ADDR1 ADC Data Register 1 0x4 read-write n 0x0 0x0 ADDR2 ADDR2 ADC Data Register 2 0x8 read-write n 0x0 0x0 ADDR3 ADDR3 ADC Data Register 3 0xC read-write n 0x0 0x0 ADDR4 ADDR4 ADC Data Register 4 0x10 read-write n 0x0 0x0 ADDR5 ADDR5 ADC Data Register 5 0x14 read-write n 0x0 0x0 ADDR6 ADDR6 ADC Data Register 6 0x18 read-write n 0x0 0x0 ADDR7 ADDR7 ADC Data Register 7 0x1C read-write n 0x0 0x0 ADSR ADSR ADC Status Register 0x30 read-write n 0x0 0x0 ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself. 0 1 read-write BUSY BUSY/IDLE\nThis bit is mirror of as ADST bit (ADCR[11]).\nIt is read only. 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel\nIt is read only. 4 3 read-write CMPF0 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n 1 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0 setting #0 1 Conversion result in ADDR meets ADCMPR0 setting #1 CMPF1 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n 2 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 OVERRUN Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR0~7[16]).\nIt is read only. 16 8 read-write VALID Data Valid Flag\nIt is a mirror of VALID bit (ADDR0~7[17]).\nIt is read only. 8 8 read-write BPWM0 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_ADCTS0 BPWM_ADCTS0 BPWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger ADC Enable Control 7 1 read-write TRGEN1 BPWM_CH1 Trigger ADC Enable Control 15 1 read-write TRGEN2 BPWM_CH2 Trigger ADC Enable Control 23 1 read-write TRGEN3 BPWM_CH3 Trigger ADC Enable Control 31 1 read-write TRGSEL0 BPWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL1 BPWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL2 BPWM_CH2 Trigger ADC Source Select\nOthers reserved. 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 TRGSEL3 BPWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 BPWM_ADCTS1 BPWM_ADCTS1 BPWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger ADC Enable Control 7 1 read-write TRGEN5 BPWM_CH5 Trigger ADC Enable Control 15 1 read-write TRGSEL4 BPWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 TRGSEL5 BPWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn BPWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn BPWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin 1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Pre-scale Register 0x14 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Pre-Scale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH01 External Clock Source Select\n 0 3 read-write 0 BPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.\nIn independent mode, BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode, BPWM_CMPDAT0, 2, 4 denote as first compared point, and BPWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs BPWM_CH0 and BPWM_CH1, BPWM_CH2 and BPWM_CH3, BPWM_CH4 and BPWM_CH5. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 read-write n 0x0 0x0 BPWM_CNT0 BPWM_CNT0 BPWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 BPWM Counter Enable 0\n 0 1 read-write 0 BPWM Counter and clock prescaler Stop Running #0 1 BPWM Counter and clock prescaler Start Running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-Load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 read-write n 0x0 0x0 CMPDIENn BPWM Compare Down Count Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn BPWM Compare Up Count Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 BPWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS0 BPWM_INTSTS0 BPWM Interrupt Flag Register 0xE8 read-write n 0x0 0x0 CMPDIFn BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Output logic low to BPWMn 0 1 Output logic high to BPWMn 1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn BPWM Mask Enable Control\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. \n 0 6 read-write 0 BPWM output signal is non-masked 0 1 BPWM output signal is masked and output MSKDATn data 1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 read-only n 0x0 0x0 PBUF BPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 read-write n 0x0 0x0 PERIOD BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn BPWM Pin Output Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM pin at tri-state 0 1 BPWM pin in output mode 1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM output polar inverse Disabled 0 1 BPWM output polar inverse Enabled 1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from BPWM0 #00 1 Synchronous start source come from BPWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected BPWM channels (include BPWM0_CHx and BPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated BPWM channel counter synchronous start function is enabled.\nNote: This bit only present in BPWM0_BA. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start Of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-Base Counter 0 Equal To 0xFFFF Latched Status\n 0 1 read-write 0 Indicates the time-base counter never reached its maximum value 0xFFFF #0 1 Indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIODn+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 BPWM period (center) point output Low 01 10 BPWM period (center) point output High 10 11 BPWM period (center) point output Toggle 11 ZPCTLn BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 BPWM zero point output Low 01 10 BPWM zero point output High 10 11 BPWM zero point output Toggle 11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 BPWM compare down point output Low 01 10 BPWM compare down point output High 10 11 BPWM compare down point output Toggle 11 CMPUCTLn BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 BPWM compare up point output Low 01 10 BPWM compare up point output High 10 11 BPWM compare up point output Toggle 11 BPWM1 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_ADCTS0 BPWM_ADCTS0 BPWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger ADC Enable Control 7 1 read-write TRGEN1 BPWM_CH1 Trigger ADC Enable Control 15 1 read-write TRGEN2 BPWM_CH2 Trigger ADC Enable Control 23 1 read-write TRGEN3 BPWM_CH3 Trigger ADC Enable Control 31 1 read-write TRGSEL0 BPWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL1 BPWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL2 BPWM_CH2 Trigger ADC Source Select\nOthers reserved. 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 TRGSEL3 BPWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 BPWM_ADCTS1 BPWM_ADCTS1 BPWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger ADC Enable Control 7 1 read-write TRGEN5 BPWM_CH5 Trigger ADC Enable Control 15 1 read-write TRGSEL4 BPWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 TRGSEL5 BPWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn BPWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn BPWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin 1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Pre-scale Register 0x14 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Pre-Scale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH01 External Clock Source Select\n 0 3 read-write 0 BPWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.\nIn independent mode, BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.\nIn complementary mode, BPWM_CMPDAT0, 2, 4 denote as first compared point, and BPWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs BPWM_CH0 and BPWM_CH1, BPWM_CH2 and BPWM_CH3, BPWM_CH4 and BPWM_CH5. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 read-write n 0x0 0x0 BPWM_CNT0 BPWM_CNT0 BPWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 BPWM Counter Enable 0\n 0 1 read-write 0 BPWM Counter and clock prescaler Stop Running #0 1 BPWM Counter and clock prescaler Start Running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-Load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 read-write n 0x0 0x0 CMPDIENn BPWM Compare Down Count Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn BPWM Compare Up Count Interrupt Enable Control\nEach bit n controls the corresponding BPWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 BPWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS0 BPWM_INTSTS0 BPWM Interrupt Flag Register 0xE8 read-write n 0x0 0x0 CMPDIFn BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Output logic low to BPWMn 0 1 Output logic high to BPWMn 1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn BPWM Mask Enable Control\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. \n 0 6 read-write 0 BPWM output signal is non-masked 0 1 BPWM output signal is masked and output MSKDATn data 1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 read-only n 0x0 0x0 PBUF BPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 read-write n 0x0 0x0 PERIOD BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn BPWM Pin Output Enable Control\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM pin at tri-state 0 1 BPWM pin in output mode 1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM output polar inverse Disabled 0 1 BPWM output polar inverse Enabled 1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from BPWM0 #00 1 Synchronous start source come from BPWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected BPWM channels (include BPWM0_CHx and BPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated BPWM channel counter synchronous start function is enabled.\nNote: This bit only present in BPWM0_BA. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start Of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-Base Counter 0 Equal To 0xFFFF Latched Status\n 0 1 read-write 0 Indicates the time-base counter never reached its maximum value 0xFFFF #0 1 Indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIODn+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 BPWM period (center) point output Low 01 10 BPWM period (center) point output High 10 11 BPWM period (center) point output Toggle 11 ZPCTLn BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 BPWM zero point output Low 01 10 BPWM zero point output High 10 11 BPWM zero point output Toggle 11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 BPWM compare down point output Low 01 10 BPWM compare down point output High 10 11 BPWM compare down point output Toggle 11 CMPUCTLn BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 BPWM compare up point output Low 01 10 BPWM compare up point output High 10 11 BPWM compare up point output Toggle 11 CAN0 CAN Register Map CAN 0x0 0x0 0x1C registers n 0x100 0x8 registers n 0x120 0x8 registers n 0x140 0x8 registers n 0x160 0x10 registers n 0x20 0x2C registers n 0x80 0x2C registers n CAN_BRPE CAN_BRPE Baud Rate Prescaler Extension Register 0x18 read-write n 0x0 0x0 BRPE Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. 0 4 read-write CAN_BTIME CAN_BTIME Bit Timing Register 0xC read-write n 0x0 0x0 BRP Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quantum. Valid values for the Baud Rate Prescaler are [0...63]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 0 6 read-write SJW (Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0...3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 6 2 read-write TSeg1 Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1...15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used. 8 4 read-write TSeg2 Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0...7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 12 3 read-write CAN_CON CAN_CON Control Register 0x0 read-write n 0x0 0x0 CCE Configuration Change Enable Control\n 6 1 read-write 0 No write access to the Bit Timing Register #0 1 Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1) #1 DAR Automatic Re-Transmission Disable Control\n 5 1 read-write 0 Automatic Retransmission of disturbed messages Enabled #0 1 Automatic Retransmission Disabled #1 EIE Error Interrupt Enable Control\n 3 1 read-write 0 Disabled - No Error Status Interrupt will be generated #0 1 Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt #1 IE Module Interrupt Enable Control\n 1 1 read-write 0 Disabled #0 1 Enabled #1 Init Init Initialization\n 0 1 read-write 0 Normal Operation #0 1 Initialization is started #1 SIE Status Change Interrupt Enable Control\n 2 1 read-write 0 Disabled - No Status Change Interrupt will be generated #0 1 Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected #1 Test Test Mode Enable Control\n 7 1 read-write 0 Normal Operation #0 1 Test Mode #1 CAN_ERR CAN_ERR Error Counter Register 0x8 read-only n 0x0 0x0 REC Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127. 8 7 read-only RP Receive Error Passive\n 15 1 read-only 0 The Receive Error Counter is below the error passive level #0 1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification #1 TEC Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255. 0 8 read-only CAN_IF1_ARB1 CAN_IF1_ARB1 IF1 Arbitration 1 Register 0x30 read-write n 0x0 0x0 ID15_0 Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame"). 0 16 read-write CAN_IF1_ARB2 CAN_IF1_ARB2 IF1 Arbitration 2 Register 0x34 read-write n 0x0 0x0 Dir Message Direction\n 13 1 read-write 0 Direction is receive #0 1 Direction is transmit #1 ID28_16 Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame"). 0 13 read-write MsgVal Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. 15 1 read-write 0 The Message Object is ignored by the Message Handler #0 1 The Message Object is configured and should be considered by the Message Handler #1 Xtd Extended Identifier\n 14 1 read-write 0 The 11-bit ("standard") Identifier will be used for this Message Object #0 1 The 29-bit ("extended") Identifier will be used for this Message Object #1 CAN_IF1_CMASK CAN_IF1_CMASK IF1 Command Mask Register 0x24 read-write n 0x0 0x0 Arb Access Arbitration Bits\nWrite Operation:\n 5 1 read-write 0 Arbitration bits unchanged #0 1 Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register #1 ClrIntPnd Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation:\n 3 1 read-write 0 IntPnd bit (CAN_IFn_MCON[13]) remains unchanged #0 1 Clear IntPnd bit in the Message Object #1 Control Control Access Control Bit\nWrite Operation:\n 4 1 read-write 0 Control Bits unchanged #0 1 Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register #1 DAT_A Access Data Bytes [3:0]\nWrite Operation:\n 1 1 read-write 0 Data Bytes [3:0] unchanged #0 1 Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register #1 DAT_B Access Data Bytes [7:4]\nWrite Operation: \n 0 1 read-write 0 Data Bytes [7:4] unchanged #0 1 Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register #1 Mask Access Mask Bits\nWrite Operation:\n 6 1 read-write 0 Mask bits unchanged #0 1 Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register #1 TxRqst_NewDat Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. 2 1 read-write 0 TxRqst bit unchanged.\nNewDat bit remains unchanged #0 1 Set TxRqst bit.\nClear NewDat bit in the Message Object #1 WR_RD Write / Read Mode\n 7 1 read-write 0 Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers #0 1 Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register #1 CAN_IF1_CREQ CAN_IF1_CREQ IF1 (Register Map Note 2) Command Request Registers 0x20 read-write n 0x0 0x0 Busy Busy Flag\n 15 1 read-write 0 Read/write action has finished #0 1 Writing to the IFn Command Request Register is in progress. This bit can only be read by the software #1 MessageNumber Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message.\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. 0 6 read-write CAN_IF1_DAT_A1 CAN_IF1_DAT_A1 IF1 Data A1 Register (Register Map Note 3) 0x3C read-write n 0x0 0x0 Data_0 Data Byte 0\n1st data byte of a CAN Data Frame. 0 8 read-write Data_1 Data Byte 1\n2nd data byte of a CAN Data Frame. 8 8 read-write CAN_IF1_DAT_A2 CAN_IF1_DAT_A2 IF1 Data A2 Register (Register Map Note 3) 0x40 read-write n 0x0 0x0 Data_2 Data Byte 2\n3rd data byte of CAN Data Frame. 0 8 read-write Data_3 Data Byte 3\n4th data byte of CAN Data Frame. 8 8 read-write CAN_IF1_DAT_B1 CAN_IF1_DAT_B1 IF1 Data B1 Register (Register Map Note 3) 0x44 read-write n 0x0 0x0 Data_4 Data Byte 4\n5th data byte of CAN Data Frame. 0 8 read-write Data_5 Data Byte 5\n6th data byte of CAN Data Frame. 8 8 read-write CAN_IF1_DAT_B2 CAN_IF1_DAT_B2 IF1 Data B2 Register (Register Map Note 3) 0x48 read-write n 0x0 0x0 Data_6 Data Byte 6\n7th data byte of CAN Data Frame. 0 8 read-write Data_7 Data Byte 7\n8th data byte of CAN Data Frame. 8 8 read-write CAN_IF1_MASK1 CAN_IF1_MASK1 IF1 Mask 1 Register 0x28 read-write n 0x0 0x0 Msk15_0 Identifier Mask 15-0\n 0 16 read-write 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 0 1 The corresponding identifier bit is used for acceptance filtering 1 CAN_IF1_MASK2 CAN_IF1_MASK2 IF1 Mask 2 Register 0x2C read-write n 0x0 0x0 MDir Mask Message Direction\n 14 1 read-write 0 The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering #0 1 The message direction bit (Dir) is used for acceptance filtering #1 Msk28_16 Identifier Mask 28-16\n 0 13 read-write 0 The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering 0 1 The corresponding identifier bit is used for acceptance filtering 1 MXtd Mask Extended Identifier\nNote: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. 15 1 read-write 0 The extended identifier bit (IDE) has no effect on the acceptance filtering #0 1 The extended identifier bit (IDE) is used for acceptance filtering #1 CAN_IF1_MCON CAN_IF1_MCON IF1 Message Control Register 0x38 read-write n 0x0 0x0 DLC Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData(0): 1st data byte of a CAN Data Frame\nData(1): 2nd data byte of a CAN Data Frame\nData(2): 3rd data byte of a CAN Data Frame\nData(3): 4th data byte of a CAN Data Frame\nData(4): 5th data byte of a CAN Data Frame\nData(5): 6th data byte of a CAN Data Frame\nData(6): 7th data byte of a CAN Data Frame\nData(7): 8th data byte of a CAN Data Frame\nNote: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. 0 4 read-write EoB End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. 7 1 read-write 0 Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer #0 1 Single Message Object or last Message Object of a FIFO Buffer #1 IntPnd Interrupt Pending\n 13 1 read-write 0 This message object is not the source of an interrupt #0 1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority #1 MsgLst None 14 1 read-write 0 No message lost since last time this bit was reset by the CPU #0 1 The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message #1 NewDat New Data\n 15 1 read-write 0 No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software #0 1 The Message Handler or the application software has written new data into the data portion of this Message Object #1 RmtEn Remote Enable Control\n 9 1 read-write 0 At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged #0 1 At the reception of a Remote Frame, TxRqst is set #1 RxIE Receive Interrupt Enable Control\n 10 1 read-write 0 IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame #0 1 IntPnd will be set after a successful reception of a frame #1 TxIE Transmit Interrupt Enable Control\n 11 1 read-write 0 IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame #0 1 IntPnd will be set after a successful transmission of a frame #1 TxRqst Transmit Request\n 8 1 read-write 0 This Message Object is not waiting for transmission #0 1 The transmission of this Message Object is requested and is not yet done #1 UMask Use Acceptance Mask\nNote: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. 12 1 read-write 0 Mask ignored #0 1 Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering #1 CAN_IF2_ARB1 CAN_IF2_ARB1 IF2 Arbitration 1 Register 0x90 read-write n 0x0 0x0 CAN_IF2_ARB2 CAN_IF2_ARB2 IF2 Arbitration 2 Register 0x94 read-write n 0x0 0x0 CAN_IF2_CMASK CAN_IF2_CMASK IF2 Command Mask Register 0x84 read-write n 0x0 0x0 CAN_IF2_CREQ CAN_IF2_CREQ IF2 (Register Map Note 2) Command Request Registers 0x80 read-write n 0x0 0x0 CAN_IF2_DAT_A1 CAN_IF2_DAT_A1 IF2 Data A1 Register (Register Map Note 3) 0x9C read-write n 0x0 0x0 CAN_IF2_DAT_A2 CAN_IF2_DAT_A2 IF2 Data A2 Register (Register Map Note 3) 0xA0 read-write n 0x0 0x0 CAN_IF2_DAT_B1 CAN_IF2_DAT_B1 IF2 Data B1 Register (Register Map Note 3) 0xA4 read-write n 0x0 0x0 CAN_IF2_DAT_B2 CAN_IF2_DAT_B2 IF2 Data B2 Register (Register Map Note 3) 0xA8 read-write n 0x0 0x0 CAN_IF2_MASK1 CAN_IF2_MASK1 IF2 Mask 1 Register 0x88 read-write n 0x0 0x0 CAN_IF2_MASK2 CAN_IF2_MASK2 IF2 Mask 2 Register 0x8C read-write n 0x0 0x0 CAN_IF2_MCON CAN_IF2_MCON IF2 Message Control Register 0x98 read-write n 0x0 0x0 CAN_IIDR CAN_IIDR Interrupt Identifier Register 0x10 read-only n 0x0 0x0 IntId Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). The Status Interrupt is cleared by reading the Status Register. 0 16 read-only CAN_IPND1 CAN_IPND1 Interrupt Pending Register 1 0x140 read-only n 0x0 0x0 IntPnd16_1 Interrupt Pending Bits 16-1 (Of All Message Objects)\n 0 16 read-only 0 This message object is not the source of an interrupt 0 1 This message object is the source of an interrupt 1 CAN_IPND2 CAN_IPND2 Interrupt Pending Register 2 0x144 read-only n 0x0 0x0 IntPnd32_17 Interrupt Pending Bits 32-17 (Of All Message Objects)\n 0 16 read-only 0 This message object is not the source of an interrupt 0 1 This message object is the source of an interrupt 1 CAN_MVLD1 CAN_MVLD1 Message Valid Register 1 0x160 read-only n 0x0 0x0 MsgVal16_1 Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured. 0 16 read-only 0 This Message Object is ignored by the Message Handler 0 1 This Message Object is configured and should be considered by the Message Handler 1 CAN_MVLD2 CAN_MVLD2 Message Valid Register 2 0x164 read-only n 0x0 0x0 MsgVal32_17 Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured. 0 16 read-only 0 This Message Object is ignored by the Message Handler 0 1 This Message Object is configured and should be considered by the Message Handler 1 CAN_NDAT1 CAN_NDAT1 New Data Register 1 0x120 read-only n 0x0 0x0 NewData16_1 New Data Bits 16-1 (Of All Message Objects)\n 0 16 read-only 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 0 1 The Message Handler or the application software has written new data into the data portion of this Message Object 1 CAN_NDAT2 CAN_NDAT2 New Data Register 2 0x124 read-only n 0x0 0x0 NewData32_17 New Data Bits 32-17 (Of All Message Objects)\n 0 16 read-only 0 No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software 0 1 The Message Handler or the application software has written new data into the data portion of this Message Object 1 CAN_STATUS CAN_STATUS Status Register 0x4 read-write n 0x0 0x0 BOff Bus-Off Status (Read Only) \n 7 1 read-only 0 The CAN module is not in bus-off state #0 1 The CAN module is in bus-off state #1 EPass Error Passive (Read Only)\n 5 1 read-only 0 The CAN Core is error active #0 1 The CAN Core is in the error passive state as defined in the CAN Specification #1 EWarn Error Warning Status (Read Only)\n 6 1 read-only 0 Both error counters are below the error warning limit of 96 #0 1 At least one of the error counters in the EML has reached the error warning limit of 96 #1 LEC Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. The following table describes the error code. 0 3 read-write RxOK Received A Message Successfully\n 4 1 read-write 0 No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core #0 1 A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering) #1 TxOK Transmitted A Message Successfully\n 3 1 read-write 0 Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core #0 1 Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted #1 CAN_TEST CAN_TEST Test Register (Register Map Note 1) 0x14 read-write n 0x0 0x0 Basic Basic Mode\n 2 1 read-write 0 Basic Mode Disabled #0 1 IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer #1 LBack Loop Back Mode Enable Control\n 4 1 read-write 0 Loop Back Mode is Disabled #0 1 Loop Back Mode is Enabled #1 Rx Monitors The Actual Value Of CAN_RX Pin (Read Only) \n 7 1 read-only 0 The CAN bus is dominant (CAN_RX = '0') #0 1 The CAN bus is recessive (CAN_RX = '1') #1 Silent Silent Mode\n 3 1 read-write 0 Normal operation #0 1 The module is in Silent Mode #1 Tx Tx[1:0]: Control Of CAN_TX Pin\n 5 2 read-write 0 Reset value, CAN_TX pin is controlled by the CAN Core #00 1 Sample Point can be monitored at CAN_TX pin #01 2 CAN_TX pin drives a dominant ('0') value #10 3 CAN_TX pin drives a recessive ('1') value #11 CAN_TXREQ1 CAN_TXREQ1 Transmission Request Register 1 0x100 read-only n 0x0 0x0 TxRqst16_1 Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only. 0 16 read-only 0 This Message Object is not waiting for transmission 0 1 The transmission of this Message Object is requested and is not yet done 1 CAN_TXREQ2 CAN_TXREQ2 Transmission Request Register 2 0x104 read-only n 0x0 0x0 TxRqst32_17 Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only. 0 16 read-only 0 This Message Object is not waiting for transmission 0 1 The transmission of this Message Object is requested and is not yet done 1 CAN_WU_EN CAN_WU_EN Wake-up Enable Register 0x168 read-write n 0x0 0x0 WAKUP_EN Wake-Up Enable Control\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin. 0 1 read-write 0 The wake-up function Disabled #0 1 The wake-up function Enabled #1 CAN_WU_STATUS CAN_WU_STATUS Wake-up Status Register 0x16C read-write n 0x0 0x0 WAKUP_STS Wake-Up Status \nNote: This bit can be cleared by writing '0'. 0 1 read-write 0 No wake-up event occurred #0 1 Wake-up event occurred #1 CLK CLK Register Map CLK 0x0 0x0 0x28 registers n 0x30 0x8 registers n 0x70 0x10 registers n AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 read-write n 0x0 0x0 ISP_EN Flash ISP Controller Clock Enable Control\n 2 1 read-write 0 Flash ISP peripherial clock Disabled #0 1 Flash ISP peripherial clock Enabled #1 APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 read-write n 0x0 0x0 ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control\n 28 1 read-write 0 ADC clock Disabled #0 1 ADC clock Enabled #1 CAN0_EN CAN Bus Controller-0 Clock Enable Control\n 24 1 read-write 0 CAN0 clock Disabled #0 1 CAN0 clock Enabled #1 FDIV_EN Frequency Divider Output Clock Enable Control\n 6 1 read-write 0 FDIV clock Disabled #0 1 FDIV clock Enabled #1 I2C0_EN I2C0 Clock Enable Control\n 8 1 read-write 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 I2C1_EN I2C1 Clock Enable Control\n 9 1 read-write 0 I2C1 clock Disabled #0 1 I2C1 clock Enabled #1 SPI0_EN SPI0 Clock Enable Control\n 12 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 TMR0_EN Timer0 Clock Enable Control\n 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1_EN Timer1 Clock Enable Control\n 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2_EN Timer2 Clock Enable Control\n 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3_EN Timer3 Clock Enable Control\n 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0_EN UART0 Clock Enable Control\n 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1_EN UART1 Clock Enable Control\n 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 UART2_EN UART2 Clock Enable Control\n 18 1 read-write 0 UART2 clock Disabled #0 1 UART2 clock Enabled #1 WDT_EN Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Watchdog Timer clock Disabled #0 1 Watchdog Timer clock Enabled #1 APBCLK1 APBCLK1 APB Devices Clock Enable Control Register 1 0x30 read-write n 0x0 0x0 BPWM0_EN BPWM0 Clock Enable Control\n 18 1 read-write 0 BPWM0 clock Disabled #0 1 BPWM0 clock Enabled #1 BPWM1_EN BPWM1 Clock Enable Control\n 19 1 read-write 0 BPWM1 clock Disabled #0 1 BPWM1 clock Enabled #1 PWM0_EN PWM0 Clock Enable Control\n 16 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 PWM1_EN PWM1 Clock Enable Control\n 17 1 read-write 0 PWM1 clock Disabled #0 1 PWM1 clock Enabled #1 UART3_EN UART3 Clock Enable Control\n 8 1 read-write 0 UART3 clock Disabled #0 1 UART3 clock Enabled #1 UART4_EN UART4 Clock Enable Control\n 9 1 read-write 0 UART4 clock Disabled #0 1 UART4 clock Enabled #1 UART5_EN UART5 Clock Enable Control\n 10 1 read-write 0 UART5 clock Disabled #0 1 UART5 clock Enabled #1 CDLOWB CDLOWB Clock Frequency Detector Lower Boundary Register 0x7C read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor values lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CDUPB CDUPB Clock Frequency Detector Upper Boundary Register 0x78 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CLKDCTL CLKDCTL Clock Fail Detector Control Register 0x70 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Control\n 4 1 read-write 0 HXT clock Fail detector Disabled #0 1 HXT clock Fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Control\n 5 1 read-write 0 HXT clock Fail interrupt Disabled #0 1 HXT clock Fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Monitor Enable Control\n 16 1 read-write 0 HXT clock frequency monitor Disabled #0 1 HXT clock frequency monitor Enabled #1 HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Control\n 17 1 read-write 0 HXT clock frequency monitor fail interrupt Disabled #0 1 HXT clock frequency monitor fail interrupt Enabled #1 CLKDIV CLKDIV Clock Divider Number Register 0x18 read-write n 0x0 0x0 ADC_N ADC Clock Divide Number From ADC Clock Source\n 16 8 read-write HCLK_N HCLK Clock Divide Number From HCLK Clock Source\n 0 4 read-write UART_N UART Clock Divide Number From UART Clock Source\n 8 4 read-write CLKDSTS CLKDSTS Clock Fail Detector Status Register 0x74 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag\n 0 1 read-write 0 HXT clock normal #0 1 HXT clock stop (write "1" to clear) #1 HXTFQIF HXT Clock Frequency Monitor Interrupt Flag\n 8 1 read-write 0 HXT clock normal #0 1 HXT clock frequency abnormal (write "1" to clear) #1 CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 read-write n 0x0 0x0 HCLK_S HCLK Clock Source Select (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be enabled\nThe 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Reserved #001 2 Clock source from PLL #010 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #011 7 Clock source from 22.1184 MHz internalhigh speed RC oscillator (HIRC) #111 STCLK_S Cortex-M0 SysTick Clock Source Select (Write Protect)\n 3 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Reserved #001 2 Clock source from 4~24 MHz external high speed crystal oscillator (HXT)/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC)/2 #111 CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 read-write n 0x0 0x0 ADC_S ADC Clock Source Select\n 2 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from HCLK #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 SPI0_S SPI0 Clock Source Selection\n 4 1 read-write 0 Clock source from PLL #0 1 Clock source from HCLK #1 TMR0_S TIMER0 Clock Source Selection\n 8 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Reserved #001 2 Clock source from HCLK #010 3 Clock source from external trigger #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 TMR1_S TIMER1 Clock Source Selection\n 12 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Reserved #001 2 Clock source from HCLK #010 3 Clock source from external trigger #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 TMR2_S TIMER2 Clock Source Selection\n 16 3 read-write 0 Clock source from external 4~24 MHz high speed crystal oscillator (HXT) #000 1 Reserved #001 2 Clock source from HCLK #010 3 Clock source from external trigger #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 TMR3_S TIMER3 Clock Source Selection\n 20 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #000 1 Reserved #001 2 Clock source from HCLK #010 3 Clock source from external trigger #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 UART_S UART Clock Source Selection\n 24 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 WDT_S Watchdog Timer Clock Source Select (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 2 read-write 0 Reserved #00 1 Reserved #01 2 Clock source from HCLK/2048 #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x1C read-write n 0x0 0x0 FRQDIV_S Clock Divider Clock Source Selection\n 2 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator clock #11 WWDT_S Window Watchdog Timer Clock Source Selection\n 16 2 read-write 2 Clock source from HCLK/2048 clock #10 3 Clock source from 10 kHz internal low speed RC oscillator clock #11 CLKSEL3 CLKSEL3 Clock Source Select Control Register 3 0x34 read-write n 0x0 0x0 BPWM0_S BPWM0 Clock Source Selection\nThe Engine clock source of BPWM0 is defined by BPWM0_S.\n 18 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK #1 BPWM1_S BPWM1 Clock Source Selection\nThe Engine clock source of BPWM1 is defined by BPWM1_S.\n 19 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK #1 PWM0_S PWM0 Clock Source Selection\nThe Engine clock source of PWM0 is defined by PWM0_S.\n 16 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK #1 PWM1_S PWM1 Clock Source Selection\nThe Engine clock source of PWM1 is defined by PWM1_S.\n 17 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK #1 CLKSTATUS CLKSTATUS Clock Status Monitor Register 0xC read-write n 0x0 0x0 CLK_SW_FAIL Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switchs system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 OSC10K_STB Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)\n 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 OSC22M_STB 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Clock Source Stable Flag (Read Only)\n 4 1 read-only 0 22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled #1 PLL_STB Internal PLL Clock Source Stable Flag (Read Only)\n 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable in normal mode #1 XTL12M_STB 4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)\n 0 1 read-only 0 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled #1 FRQDIV FRQDIV Frequency Divider Control Register 0x24 read-write n 0x0 0x0 DIVIDER1 Frequency Divider One Enable Control\n 5 1 read-write 0 Frequency divider will output clock with source frequency divided by FSEL #0 1 Frequency divider will output clock with source frequency #1 DIVIDER_EN Frequency Divider Enable Control\n 4 1 read-write 0 Frequency divider function Disabled #0 1 Frequency divider function Enabled #1 FSEL Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]. 0 4 read-write PLLCON PLLCON PLL Control Register 0x20 read-write n 0x0 0x0 BP PLL Bypass Control\n 17 1 read-write 0 PLL is in Normal mode (default) #0 1 PLL clock output is same as PLL source clock input #1 FB_DV PLL Feedback Divider Control Bits\nRefer to the formulas below the table. 0 9 read-write IN_DV PLL Input Divider Control Bits\nRefer to the formulas below the table. 9 5 read-write OE PLL OE (FOUT Enable) Pin Control\n 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUT_DV PLL Output Divider Control Bits\nRefer to the formulas below the table. 14 2 read-write PD Power-Down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n 16 1 read-write 0 PLL is in Normal mode #0 1 PLL is in Power-down mode (default) #1 PLL_SRC PLL Source Clock Selection\n 19 1 read-write 0 PLL source clock from 4~24 MHz external high speed crystal oscillator #0 1 PLL source clock from 22.1184 MHz internal high speed RC oscillator #1 PWRCON PWRCON System Power-down Control Register 0x0 read-write n 0x0 0x0 OSC10K_EN 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 OSC22M_EN 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 2 1 read-write 0 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled #1 PD_WAIT_CPU Power-Down Entry Condition Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 8 1 read-write 0 Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1 #0 1 Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU runs WFI instruction #1 PD_WU_DLY Wake-Up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 22.1184 MHz internal high speed oscillator (HIRC).\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PD_WU_INT_EN Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PD_WU_STS Power-Down Mode Wake-Up Interrupt Status\nSet by "Power-down wake-up event", it indicates that resume from Power-down mode".\nThe flag is set if the GPIO, UART, WDT, I2C, TIMER, CAN, or BOD wake-up occurred.\nWrite 1 to clear the bit to 0.\nNote: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1. 6 1 read-write PWR_DOWN_EN System Power-Down Enable Control (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed RC oscillator (HIRC) will be disabled in this mode, but the 10 kHz internal low speed RC oscillator (LIRC) is not controlled by Power-down mode.\nIn Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the 10 kHz internal low speed RC oscillator (LIRC).\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 7 1 read-write 0 Chip operating normally or chip in Idle mode because of WFI command #0 1 Chip enters Power-down mode instantly or waits CPU sleep command WFI #1 XTL12M_EN 4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Control (Write Protect)\nThe bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from 4~24 MHz external high speed crystal oscillator, this bit is set to 1 automatically.\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 4 ~ 24 MHz external high speed crystal oscillator (HXT) Disabled #0 1 4 ~ 24 MHz external high speed crystal oscillator (HXT) Enabled #1 FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n DFBADR DFBADR Data Flash Base Address 0x14 read-only n 0x0 0x0 DFBADR Data Flash Base Address\nThis register indicates Data Flash start address. It is read only.\nWhen DFVSEN is set to 0, the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is loaded from Config1.\nWhen DFVSEN is set to 1, the data flash size is fixed as 4K and the start address can be read from this register is fixed at 0x0001_F000. 0 32 read-only FATCON FATCON Flash Access Time Control Register 0x18 read-write n 0x0 0x0 FOMSEL0 Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)\nWhen CPU frequency is lower than 25 MHz, user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance.\n 4 1 read-write FOMSEL1 Chip Frequency Optimization Mode Select1 (Write-protection Bit) 6 1 read-write ISPADR ISPADR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address\nThe NuMicro( NUC1311 series has a maximum of 17Kx32 (68 KB) embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 ISPCMD ISP Command\nISP command table is shown below:\n 0 6 read-write 0 Read 0x00 4 Read Unique ID 0x04 11 Read Company ID (0xDA) 0x0b 33 Program 0x21 34 Page Erase 0x22 46 Set Vector Page Re-Map 0x2e ISPCON ISPCON ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Control (Write Protect)\n 3 1 read-write 0 APROM cannot be updated when chip runs in APROM #0 1 APROM can be updated when chip runs in APROM #1 BS Boot Select (Write Protect )\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.\n 1 1 read-write 0 Boot from APROM #0 1 Boot from LDROM #1 CFGUEN Enable Config Update By ISP (Write Protect)\n 4 1 read-write 0 ISP update config-bit Disabled #0 1 ISP update config-bit Enabled #1 ISPEN ISP Enable Control (Write Protect )\nISP function enable bit. Set this bit to enable ISP function.\n 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear to this bit to 0. 6 1 read-write LDUEN LDROM Update Enable Control (Write Protect)\n 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when chip runs in APROM #1 ISPDAT ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTA ISPSTA ISP Status Register 0x40 read-write n 0x0 0x0 CBS Chip Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0. 1 2 read-only ISPFF ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear this bit.\nNote: The function of this bit is the same as ISPCON bit6. 6 1 read-write ISPGO ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0. 0 1 read-only 0 ISP operation finished #0 1 ISP operation progressed #1 VECMAP Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}. 9 12 read-only ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 ISP operation finished #0 1 ISP is in progress #1 GCR GCR Register Map GCR 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x18 0x4 registers n 0x24 0x8 registers n 0x30 0x18 registers n 0x50 0x4 registers n 0x5C 0xC registers n ALT_MFP ALT_MFP Alternative Multiple Function Pin Control Register 0x50 read-write n 0x0 0x0 PB15_T0EX PB.15 Pin Alternative Function Selection Bits PB15_BPWM15 (ALT_MFP3[23]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function. (PB15_BPWM15, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list. 24 1 read-write PB2_T2EX PB.2 Pin Alternative Function Selection Bits PB2_TM2 (ALT_MFP2[4]), PB2_PWM1BK1 (ALT_MFP3[31]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function. (PB2_TM2, PB2_PWM1BK1, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. 26 1 read-write PB3_T3EX PB.3 Pin Alternative Function Selection Bits PB3_TM3 (ALT_MFP2[5]), PB3_PWM1BK0 (ALT_MFP3[30]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function. (PB3_TM3, PB3_PWM1BK0, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. 27 1 read-write PB8_CLKO PB.8 Pin Alternative Function Selection Bits PB8_BPWM12 (ALT_MFP3[20]), PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function. (PB8_BPWM12, PB8_CLKO, GPB_MFP8) value and function mapping is as following list. 29 1 read-write PE5_T1EX PE.5 Pin Alternative Function Selection Bits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function. (PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list. 25 1 read-write ALT_MFP2 ALT_MFP2 Alternative Multiple Function Pin Control Register 2 0x5C read-write n 0x0 0x0 PB15_TM0 PB.15 Pin Alternative Function Selection Bits PB15_BPWM15 (ALT_MFP3[23]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function. (PB15_BPWM15, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list. 2 1 read-write PB2_TM2 PB.2 Pin Alternative Function Selection Bits PB2_TM2 (ALT_MFP2[4]), PB2_PWM1BK1 (ALT_MFP3[31]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function. (PB2_TM2, PB2_PWM1BK1, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. 4 1 read-write PB3_TM3 PB.3 Pin Alternative Function Selection Bits PB3_TM3 (ALT_MFP2[5]), PB3_PWM1BK0 (ALT_MFP3[30]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function. (PB3_TM3, PB3_PWM1BK0, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. 5 1 read-write PE5_TM1 PE.5 Pin Alternative Function Selection Bits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function. (PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list. 3 1 read-write ALT_MFP3 ALT_MFP3 Alternative Multiple Function Pin Control Register 3 0x60 read-write n 0x0 0x0 PA0_PWM04 PA.0 Pin Alternative Function Selection Bits PA0_PWM04 (ALT_MFP3[4]), PA0_UR5TXD (ALT_MFP4[7]), PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function. (PA0_PWM04, PA0_UR5TXD, PA0_I2C1SCL, GPA_MFP0) value and function mapping is as following list. 4 1 read-write PA10_PWM12 PA.10 Pin Alternative Function Selection Bits PA10_PWM12 (ALT_MFP3[8]) and GPA_MFP10 determine the PA.10 function. (PA10_PWM12, GPA_MFP10) value and function mapping is as following list. 8 1 read-write PA11_PWM13 PA.11 Pin Alternative Function Selection Bits PA11_PWM13 (ALT_MFP3[9]) and GPA_MFP11 determine the PA.11 function. (PA11_PWM13, GPA_MFP11) value and function mapping is as following list. 9 1 read-write PA1_PWM05 PA.1 Pin Alternative Function Selection Bits PA1_PWM05 (ALT_MFP3[5]), PA1_UR5RXD (ALT_MFP4[6]), PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function. (PA1_PWM05, PA1_UR5RXD , PA1_I2C1SDA, GPA_MFP1) value and function mapping is as following list. 5 1 read-write PA2_PWM10 PA.2 Pin Alternative Function Selection Bits PA2_PWM10 (ALT_MFP3[6]), PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function. (PA2_PWM10, PA2_UR3TXD, GPA_MFP2) value and function mapping is as following list. 6 1 read-write PA3_PWM11 PA.3 Pin Alternative Function Selection Bits PA3_PWM11 (ALT_MFP3[7]), PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function. (PA3_PWM11, PA3_UR3RXD, GPA_MFP3) value and function mapping is as following list. 7 1 read-write PB11_PWM04 PB.11 Pin Alternative Function Selection Bits PB11_PWM04 (ALT_MFP3[24]) and GPB_MFP11 determine the PB.11 function. (PB11_PWM04, GPB_MFP11) value and function mapping is as following list. 24 1 read-write PB12_BPWM13 PB.12 Pin Alternative Function Selection Bits PB12_BPWM13 (ALT_MFP3[21]) and GPB_MFP12 determine the PB.12 function. (PB12_BPWM13, GPB_MFP12) value and function mapping is as following list. 21 1 read-write PB15_BPWM15 PB.15 Pin Function Selection Bits PB15_BPWM15 (ALT_MFP3[23]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function. (PB15_BPWM15, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list. 23 1 read-write PB2_PWM1BK1 PB.2 Pin Alternative Function Selection Bits PB2_TM2 (ALT_MFP2[4]), PB2_PWM1BK1 (ALT_MFP3[31]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function. (PB2_TM2, PB2_PWM1BK1, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. 31 1 read-write PB3_PWM1BK0 PB.3 Pin Alternative Function Selection Bits PB3_TM3 (ALT_MFP2[5]), PB3_PWM1BK0 (ALT_MFP3[30]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function. (PB3_TM3, PB3_PWM1BK0, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. 30 1 read-write PB8_BPWM12 PB.8 Pin Alternative Function Selection Bits PB8_BPWM12 (ALT_MFP3[20]), PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function. (PB8_BPWM12, PB8_CLKO, GPB_MFP8) value and function mapping is as following list. 20 1 read-write PC0_BPWM00 PC.0 Pin Alternative Function Selection Bits PC0_BPWM00 (ALT_MFP3[12]) and GPC_MFP0 determine the PC.0 function. (PC0_BPWM00, GPC_MFP0) value and function mapping is as following list. 12 1 read-write PC1_BPWM01 PC.1 Pin Alternative Function Selection Bits PC1_BPWM01 (ALT_MFP3[13]) and GPC_MFP1 determine the PC.1 function. (PC1_BPWM01, GPC_MFP1) value and function mapping is as following list. 13 1 read-write PC2_BPWM02 PC.2 Pin Alternative Function Selection Bits PC2_BPWM02 (ALT_MFP3[14]) and GPC_MFP2 determine the PC.2 function. (PC2_BPWM02, GPC_MFP2) value and function mapping is as following list. 14 1 read-write PC3_BPWM03 PC.3 Pin Alternative Function Selection Bits PC3_BPWM03 (ALT_MFP3[15]) and GPC_MFP3 determine the PC.3 function. (PC3_BPWM03, GPC_MFP3) value and function mapping is as following list. 15 1 read-write PC6_PWM0BK0 PC.6 Pin Alternative Function Selection Bits PC6_PWM0BK0 (ALT_MFP3[28]), PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function. (PC6_PWM0BK0, PC6_I2C0SDA, GPB_MFP6) value and function mapping is as following list. 28 1 read-write PC7_PWM0BK1 PC.7 Pin Alternative Function Selection Bits PC7_PWM0BK1 (ALT_MFP3[29]), PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function. (PC7_PWM0BK1, PC7_I2C0SCL, GPC_MFP7) value and function mapping is as following list. 29 1 read-write PD14_BPWM05 PD.14 Pin Alternative Function Selection Bits PD14_BPWM05 (ALT_MFP3[17]) and GPD_MFP14 determine the PD.14 function. (PD14_BPWM05, GPD_MFP14) value and function mapping is as following list. 17 1 read-write PD15_BPWM04 PD.15 Pin Alternative Function Selection Bits PD15_BPWM04 (ALT_MFP3[16]) and GPD_MFP15 determine the PD.15 function. (PD15_BPWM04, GPD_MFP15) value and function mapping is as following list. 16 1 read-write PD6_BPWM11 PD.6 Pin Alternative Function Selection Bits PD6_BPWM11 (ALT_MFP3[19]) and GPD_MFP6 determine the PD.6 function. (PD6_BPWM11, GPD_MFP6) value and function mapping is as following list. 19 1 read-write PD7_BPWM10 PD.7 Pin Alternative Function Selection Bits PD7_BPWM10 (ALT_MFP3[18]) and GPD_MFP7 determine the PD.7 function. (PD7_BPWM10, GPD_MFP7) value and function mapping is as following list. 18 1 read-write PF4_PWM14 PF.4 Pin Alternative Function Selection Bits PF4_PWM14 (ALT_MFP3[10]) and GPF_MFP4 determine the PF.4 function. (PF4_PWM14, GPF_MFP4) value and function mapping is as following list. 10 1 read-write PF5_PWM15 PF.5 Pin Alternative Function Selection Bits PF5_PWM15 (ALT_MFP3[11]) and GPF_MFP5 determine the PF.5 function. (PF5_PWM15, GPF_MFP5) value and function mapping is as following list. 11 1 read-write PF8_BPWM14 PF.8 Pin Function Selection Bit PF8_BPWM14 (ALT_MFP3[22]), GPF_MFP8 determines the PF.8 function. (PF8_BPWM14, GPF_MFP8) value and function mapping is as following list. 22 1 read-write ALT_MFP4 ALT_MFP4 Alternative Multiple Function Pin Control Register 4 0x64 read-write n 0x0 0x0 PA0_I2C1SCL PA.0 Pin Alternative Function Selection Bits PA0_PWM04 (ALT_MFP3[4]), PA0_UR5TXD (ALT_MFP4[7]), PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function. (PA0_PWM04, PA0_UR5TXD, PA0_I2C1SCL, GPA_MFP0) value and function mapping is as following list. 12 1 read-write PA0_UR5TXD PA.0 Pin Alternative Function Selection Bits PA0_PWM04 (ALT_MFP3[4]), PA0_UR5TXD (ALT_MFP4[7]), PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function. (PA0_PWM04, PA0_UR5TXD, PA0_I2C1SCL, GPA_MFP0) value and function mapping is as following list. 7 1 read-write PA12_UR5RXD PA.12 Pin Alternative Function Selection Bits PA12_UR5RXD (ALT_MFP4[8]) and GPA_MFP12 determine the PA.12 function. (PA12_UR5RXD, GPA_MFP12) value and function mapping is as following list. 8 1 read-write PA13_UR5TXD PA.13 Pin Alternative Function Selection Bits PA13_UR5TXD (ALT_MFP4[9]) and GPA_MFP13 determine the PA.13 function. (PA13_UR5TXD, GPA_MFP13) value and function mapping is as following list. 9 1 read-write PA1_I2C1SDA PA.1 Pin Alternative Function Selection Bits PA1_PWM05 (ALT_MFP3[5]), PA1_UR5RXD (ALT_MFP4[6]), PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function. (PA1_PWM05, PA1_UR5RXD, PA1_I2C1SDA, GPA_MFP1) value and function mapping is as following list. 13 1 read-write PA1_UR5RXD PA.1 Pin Alternative Function Selection Bits PA1_PWM05 (ALT_MFP3[5]), PA1_UR5RXD (ALT_MFP4[6]), PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function. (PA1_PWM05, PA1_UR5RXD, PA1_I2C1SDA, GPA_MFP1) value and function mapping is as following list. 6 1 read-write PA2_UR3TXD PA.2 Pin Alternative Function Selection Bits PA2_PWM10 (ALT_MFP3[6]), PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function. (PA2_PWM10, PA2_UR3TXD, GPA_MFP2) value and function mapping is as following list. 3 1 read-write PA3_UR3RXD PA.3 Pin Alternative Function Selection Bits PA3_PWM11 (ALT_MFP3[7]), PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function. (PA3_PWM11, PA3_UR3RXD, GPA_MFP3) value and function mapping is as following list. 2 1 read-write PA5_UR3RXD PA.5 Pin Alternative Function Selection Bits PA5_UR3RXD (ALT_MFP4[4]) and GPA_MFP5 determine the PA.5 function. (PA5_UR3RXD, GPA_MFP5) value and function mapping is as following list. 4 1 read-write PA6_UR3TXD PA.6 Pin Alternative Function Selection Bits PA6_UR3TXD (ALT_MFP4[5]) and GPA_MFP6 determine the PA.6 function. (PA6_UR3TXD, GPA_MFP6) value and function mapping is as following list. 5 1 read-write PA7_VREF PA.7 Pin Alternative Function Selection Bits PA7_VREF (ALT_MFP4[14]) and GPA_MFP7 determine the PA.7 function. (PA7_VREF, GPA_MFP7) value and function mapping is as following list. 14 1 read-write PA8_UR1RTS PA.8 Pin Alternative Function Selection Bits PA8_UR1RTS (ALT_MFP4[0]) and GPA_MFP8 determine the PA.8 function. (PA8_UR1RTS, GPA_MFP8) value and function mapping is as following list. 0 1 read-write PA9_UR1CTS PA.9 Pin Alternative Function Selection Bits PA9_UR1CTS (ALT_MFP4[1]) and GPA_MFP9 determine the PA.9 function. (PA9_UR1CTS, GPA_MFP9) value and function mapping is as following list. 1 1 read-write PC6_I2C0SDA PC.6 Pin Alternative Function Selection Bits PC6_PWM0BK0 (ALT_MFP3[28]), PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function. (PC6_PWM0BK0, PC6_I2C0SDA, GPC_MFP6) value and function mapping is as following list. 10 1 read-write PC7_I2C0SCL PC.7 Pin Alternative Function Selection Bits PC7_PWM0BK1 (ALT_MFP3[29]), PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function. (PC7_PWM0BK1, PC7_I2C0SCL, GPC_MFP7) value and function mapping is as following list. 11 1 read-write BODCR BODCR Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-Out Detector Output De-Glitch Time Select (Write Protect) Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 8 3 read-write 0 BOD output is sampled by RC10K clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BOD_EN Brown-Out Detector Enable Control (Write Protect) The default value is set by flash memory controller user configuration register CBODEN (CONFIG0[23]) bit. Note: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BOD_INTF Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled #1 BOD_LPM Brown-Out Detector Low Power Mode (Write Protect) Note1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response. Note2: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 5 1 read-write 0 BOD operated in Normal mode (default) #0 1 BOD Low Power mode Enabled #1 BOD_OUT Brown-Out Detector Output Status 6 1 read-write 0 Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 #0 1 Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled, this bit always responds to 0 #1 BOD_RSTEN Brown-Out Reset Enable Control (Write Protect) While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high). Note1: While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low). Note2: The default value is set by flash controller user configuration register CBORST (CONFIG0[20]) bit. Note3: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 3 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BOD_VL Brown-Out Detector Threshold Voltage Selection (Write Protect) The default value is set by flash memory controller user configuration register CBOV (CONFIG0[22:21]) bit. Note: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 1 2 read-write 0 Brown-out voltage is 2.2V #00 1 Brown-out voltage is 2.7V #01 2 Brown-out voltage is 3.7V #10 3 Brown-out voltage is 4.4V #11 LVRDGSEL LVR Output De-Glitch Time Select (Write Protect) Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 12 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVR_EN Low Voltage Reset Enable Control (Write Protect) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default) #1 GPA_MFP GPA_MFP GPIOA Multiple Function and Input Type Control Register 0x30 read-write n 0x0 0x0 GPA_MFP0 PA.0 Pin Function Selection Bits PA0_PWM04 (ALT_MFP3[4]), PA0_UR5TXD (ALT_MFP4[7]), PA0_I2C1SCL (ALT_MFP4[12]) and GPA_MFP0 determine the PA.0 function. (PA0_PWM04, PA0_UR5TXD, PA0_I2C1SCL, GPA_MFP0) value and function mapping is as following list. 0 1 read-write GPA_MFP1 PA.1 Pin Function Selection Bits PA1_PWM05 (ALT_MFP3[5]), PA1_UR5RXD (ALT_MFP4[6]), PA1_I2C1SDA (ALT_MFP4[13]) and GPA_MFP1 determine the PA.1 function. (PA1_PWM05, PA1_UR5RXD, PA1_I2C1SDA, GPA_MFP1) value and function mapping is as following list. 1 1 read-write GPA_MFP10 PA.10 Pin Function Selection Bits PA10_PWM12 (ALT_MFP3[8]) and GPA_MFP10 determine the PA.10 function. (PA10_PWM12, GPA_MFP10) value and function mapping is as following list. 10 1 read-write GPA_MFP11 PA.11 Pin Function Selection Bits PA11_PWM13 (ALT_MFP3[9]) and GPA_MFP11 determine the PA.11 function. (PA11_PWM13, GPA_MFP11) value and function mapping is as following list. 11 1 read-write GPA_MFP12 PA.12 Pin Function Selection Bits PA12_UR5RXD (ALT_MFP4[8]) and GPA_MFP12 determine the PA.12 function. (PA12_UR5RXD, GPA_MFP12) value and function mapping is as following list. 12 1 read-write GPA_MFP13 PA.13 Pin Function Selection Bits PA13_UR5TXD (ALT_MFP4[9]) and GPA_MFP13 determine the PA.13 function. (PA13_UR5TXD, GPA_MFP13) value and function mapping is as following list. 13 1 read-write GPA_MFP14 PA.14 Pin Function Selection Bit GPA_MFP14 determines the PA.14 function. 14 1 read-write 0 GPIO function is selected #0 1 PWM0_CH2 function is selected #1 GPA_MFP15 PA.15 Pin Function Selection Bit GPA_MFP15 determines the PA.15 function. 15 1 read-write 0 GPIO function is selected #0 1 PWM0_CH3 function is selected #1 GPA_MFP2 PA.2 Pin Function Selection Bits PA2_PWM10 (ALT_MFP3[6]), PA2_UR3TXD (ALT_MFP4[3]) and GPA_MFP2 determine the PA.2 function. (PA2_PWM10, PA2_UR3TXD, GPA_MFP2) value and function mapping is as following list. 2 1 read-write GPA_MFP3 PA.3 Pin Function Selection Bits PA3_PWM11 (ALT_MFP3[7]), PA3_UR3RXD (ALT_MFP4[2]) and GPA_MFP3 determine the PA.3 function. (PA3_PWM11, PA3_UR3RXD, GPA_MFP3) value and function mapping is as following list. 3 1 read-write GPA_MFP4 PA.4 Pin Function Selection Bit GPA_MFP4 determines the PA.4 function. 4 1 read-write 0 GPIO function is selected #0 1 ADC4 function is selected #1 GPA_MFP5 PA.5 Pin Function Selection Bits PA5_UR3RXD (ALT_MFP4[4]) and GPA_MFP5 determine the PA.5 function. (PA5_UR3RXD, GPA_MFP5) value and function mapping is as following list. 5 1 read-write GPA_MFP6 PA.6 Pin Function Selection Bits PA6_UR3TXD (ALT_MFP4[5]) and GPA_MFP6 determine the PA.6 function. (PA6_UR3TXD, GPA_MFP6) value and function mapping is as following list. 6 1 read-write GPA_MFP7 PA.7 Pin Function Selection Bits PA7_VREF (ALT_MFP4[14]) and GPA_MFP7 determine the PA.7 function. (PA7_VREF, GPA_MFP7) value and function mapping is as following list. 7 1 read-write GPA_MFP8 PA.8 Pin Function Selection Bits PA8_UR1RTS (ALT_MFP4[0]) and GPA_MFP8 determine the PA.8 function. (PA8_UR1RTS, GPA_MFP8) value and function mapping is as following list. 8 1 read-write GPA_MFP9 PA.9 Pin Function Selection Bits PA9_UR1CTS (ALT_MFP4[1]) and GPA_MFP9 determine the PA.9 function. (PA9_UR1CTS, GPA_MFP9) value and function mapping is as following list. 9 1 read-write GPA_TYPEn Trigger Function Selection 16 16 read-write 0 GPIOA[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOA[15:0] I/O input Schmitt Trigger function Enabled 1 GPB_MFP GPB_MFP GPIOB Multiple Function and Input Type Control Register 0x34 read-write n 0x0 0x0 GPB_MFP0 PB.0 Pin Function Selection Bit GPB_MFP0 determines the PB.0 function. 0 1 read-write 0 GPIO function is selected #0 1 UART0_RXD function is selected #1 GPB_MFP1 PB.1 Pin Function Selection Bit GPB_MFP1 determines the PB.1 function. 1 1 read-write 0 GPIO function is selected #0 1 UART0_TXD function is selected #1 GPB_MFP10 PB.10 Pin Function Selection Bit GPB_MFP10 determines the PB.10 function. 10 1 read-write 0 GPIO function is selected #0 1 TM2 function is selected #1 GPB_MFP11 PB.11 Pin Function Selection Bits PB11_PWM04 (ALT_MFP3[24]) and GPB_MFP11 determine the PB.11 function. (PB11_PWM04, GPB_MFP11) value and function mapping is as following list. 11 1 read-write GPB_MFP12 PB.12 Pin Function Selection Bits PB12_BPWM13 (ALT_MFP3[21]) and GPB_MFP12 determine the PB.12 function. (PB12_BPWM13, GPB_MFP12) value and function mapping is as following list. 12 1 read-write GPB_MFP14 PB.14 Pin Function Selection Bit GPB_MFP14 determines the PB.14 function. 14 1 read-write 0 GPIO function is selected #0 1 INT0 function is selected #1 GPB_MFP15 PB.15 Pin Function Selection Bits PB15_BPWM15 (ALT_MFP3[23]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP15 determine the PB.15 function. (PB15_BPWM15, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list. 15 1 read-write GPB_MFP2 PB.2 Pin Function Selection Bits PB2_TM2 (ALT_MFP2[4]), PB2_PWM1BK1 (ALT_MFP3[31]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP2 determine the PB.2 function. (PB2_TM2, PB2_PWM1BK1, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. 2 1 read-write GPB_MFP3 PB.3 Pin Function Selection Bits PB3_TM3 (ALT_MFP2[5]), PB3_PWM1BK0 (ALT_MFP3[30]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP3 determine the PB.3 function. (PB3_TM3, PB3_PWM1BK0, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. 3 1 read-write GPB_MFP4 PB.4 Pin Function Selection Bit GPB_MFP4 determines the PB.4 function. 4 1 read-write 0 GPIO function is selected #0 1 UART1_RXD function is selected #1 GPB_MFP5 PB 5 Pin Function Selection Bit GPB_MFP5 determines the PB.5 function. 5 1 read-write 0 GPIO function is selected #0 1 UART1_TXD function is selected #1 GPB_MFP6 PB.6 Pin Function Selection Bit GPB_MFP6 determines the PB.6 function. 6 1 read-write 0 GPIO function is selected #0 1 UART1_nRTS function is selected #1 GPB_MFP7 PB.7 Pin Function Selection Bit GPB_MFP7 determines the PB.7 function. 7 1 read-write 0 GPIO function is selected #0 1 UART1_nCTS function is selected #1 GPB_MFP8 PB.8 Pin Function Selection Bits PB8_BPWM12 (ALT_MFP3[20]), PB8_CLKO (ALT_MFP[29]) and GPB_MFP8 determine the PB.8 function. (PB8_BPWM12, PB8_CLKO, GPB_MFP8) value and function mapping is as following list. 8 1 read-write GPB_MFP9 PB.9 Pin Function Selection Bit GPB_MFP9 determines the PB.9 function. 9 1 read-write 0 GPIO function is selected #0 1 TM1 function is selected #1 GPB_TYPEn Trigger Function Selection 16 16 read-write 0 GPIOB[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOB[15:0] I/O input Schmitt Trigger function Enabled 1 GPC_MFP GPC_MFP GPIOC Multiple Function and Input Type Control Register 0x38 read-write n 0x0 0x0 GPC_MFP0 PC.0 Pin Function Selection Bits PC0_BPWM00 (ALT_MFP3[12]) and GPC_MFP0 determine the PC.0 function. (PC0_BPWM00, GPC_MFP0) value and function mapping is as following list. 0 1 read-write GPC_MFP1 PC.1 Pin Function Selection Bits PC1_BPWM01 (ALT_MFP3[13]) and GPC_MFP1 determine the PC.1 function. (PC1_BPWM01, GPC_MFP1) value and function mapping is as following list. 1 1 read-write GPC_MFP10 PC.10 Pin Function Selection Bit GPC_MFP10 determines the PC.10 function. 10 1 read-write 0 GPIO function is selected #0 1 PWM1_BRAKE0 function is selected #1 GPC_MFP11 PC.11 Pin Function Selection Bit GPC_MFP11 determines the PC.11 function. 11 1 read-write 0 GPIO function is selected #0 1 PWM1_BRAKE1 function is selected #1 GPC_MFP2 PC.2 Pin Function Selection Bits PC2_BPWM02 (ALT_MFP3[14]) and GPC_MFP2 determine the PC.2 function. (PC2_BPWM02, GPC_MFP2) value and function mapping is as following list. 2 1 read-write GPC_MFP3 PC.3 Pin Function Selection Bits PC3_BPWM03 (ALT_MFP3[15]) and GPC_MFP3 determine the PC.3 function. (PC3_BPWM03, GPC_MFP3) value and function mapping is as following list. 3 1 read-write GPC_MFP6 PC.6 Pin Function Selection Bits PC6_PWM0BK0 (ALT_MFP3[28]), PC6_I2C0SDA (ALT_MFP4[10]) and GPC_MFP6 determine the PC.6 function. (PC6_PWM0BK0, PC6_I2C0SDA, GPC_MFP6) value and function mapping is as following list. 6 1 read-write GPC_MFP7 PC.7 Pin Function Selection Bits PC7_PWM0BK1 (ALT_MFP3[29]), PC7_I2C0SCL (ALT_MFP4[11]) and GPC_MFP7 determine the PC.7 function. (PC7_PWM0BK1, PC7_I2C0SCL, GPC_MFP7) value and function mapping is as following list. 7 1 read-write GPC_MFP8 PC.8 Pin Function Selection Bit GPC_MFP8 determines the PC.8 function. 8 1 read-write 0 GPIO function is selected #0 1 PWM0_BRAKE0 function is selected #1 GPC_MFP9 PC.9 Pin Function Selection Bit GPC_MFP9 determines the PC.9 function. 9 1 read-write 0 GPIO function is selected #0 1 PWM0_BRAKE1 function is selected #1 GPC_TYPEn Trigger Function Selection 16 16 read-write 0 GPIOC[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOC[15:0] I/O input Schmitt Trigger function Enabled 1 GPD_MFP GPD_MFP GPIOD Multiple Function and Input Type Control Register 0x3C read-write n 0x0 0x0 GPD_MFP14 PD.14 Pin Function Selection Bits PD14_BPWM05 (ALT_MFP3[17]) and GPD_MFP14 determine the PD.14 function. (PD14_BPWM05, GPD_MFP14) value and function mapping is as following list. 14 1 read-write GPD_MFP15 PD.15 Pin Function Selection Bits PD15_BPWM04 (ALT_MFP3[16]) and GPD_MFP15 determine the PD.15 function. (PD15_BPWM04, GPD_MFP15) value and function mapping is as following list. 15 1 read-write GPD_MFP6 PD.6 Pin Function Selection Bits PD6_BPWM11 (ALT_MFP3[19]) and GPD_MFP6 determine the PD.6 function. (PD6_BPWM11, GPD_MFP6) value and function mapping is as following list. 6 1 read-write GPD_MFP7 PD.7 Pin Function Selection Bits PD7_BPWM10 (ALT_MFP3[18]) and GPD_MFP7 determine the PD.7 function. (PD7_BPWM10, GPD_MFP7) value and function mapping is as following list. 7 1 read-write GPD_TYPEn Trigger Function Selection 16 16 read-write 0 GPIOD[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOD[15:0] I/O input Schmitt Trigger function Enabled 1 GPE_MFP GPE_MFP GPIOE Multiple Function and Input Type Control Register 0x40 read-write n 0x0 0x0 GPE_MFP5 PE.5 Pin Function Selection Bits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function. (PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list. 5 1 read-write GPE_TYPE5 Trigger Function Selection 21 1 read-write 0 GPIOE[5] I/O input Schmitt Trigger function Disabled #0 1 GPIOE[5] I/O input Schmitt Trigger function Enabled #1 GPF_MFP GPF_MFP GPIOF Multiple Function and Input Type Control Register 0x44 -1 read-write n 0x0 0x0 GPF_MFP0 PF.0 Pin Function Selection\nBit GPF_MFP0 determines the PF.0 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27]). 0 1 read-write 0 GPIO function is selected #0 1 XT1_OUT function is selected #1 GPF_MFP1 PF.1 Pin Function Selection \nBit GPF_MFP1 determine the PF.1 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27]). 1 1 read-write 0 GPIO function is selected #0 1 XT1_IN function is selected #1 GPF_MFP4 PF.4 Pin Function Selection Bits PF4_PWM14 (ALT_MFP3[10]) and GPF_MFP4 determine the PF.4 function. (PF4_PWM14, GPF_MFP4) value and function mapping is as following list. 4 1 read-write GPF_MFP5 PF.5 Pin Function Selection Bits PF5_PWM15 (ALT_MFP3[11]) and GPF_MFP5 determine the PF.5 function. (PF5_PWM15, GPF_MFP5) value and function mapping is as following list. 5 1 read-write GPF_MFP6 PF.6 Pin Function Selection Bit GPF_MFP6 determines the PF.6 function. 6 1 read-write 0 GPIO function is selected #0 1 ICE_CLK function is selected #1 GPF_MFP7 PF.7 Pin Function Selection Bit GPF_MFP7 determines the PF.7 function. 7 1 read-write 0 GPIO function is selected #0 1 ICE_DAT function is selected #1 GPF_MFP8 PF.8 Pin Function Selection Bit PF8_BPWM14 (ALT_MFP3[22]), GPF_MFP8 determines the PF.8 function. (PF8_BPWM14, GPF_MFP8) value and function mapping is as following list. 8 1 read-write GPF_TYPEn Trigger Function Selection 16 9 read-write 0 GPIOF[8:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOF[8:0] I/O input Schmitt Trigger function Enabled 1 IPRSTC1 IPRSTC1 Peripheral Reset Control Register 1 0x8 read-write n 0x0 0x0 CHIP_RST CHIP One-Shot Reset (Write Protect) Setting this bit will reset the whole chip, including CPU coreand all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload. For the difference between CHIP_RST and SYSRESETREQ, please refer to section 6.2.2. Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 CHIP normal operation #0 1 CHIP one-shot reset #1 CPU_RST CPU Kernel One-Shot Reset (Write Protect) Setting this bit will only reset the CPU coreand Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles. Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 1 1 read-write 0 CPU normal operation #0 1 CPU one-shot reset #1 IPRSTC2 IPRSTC2 Peripheral Reset Control Register 2 0xC read-write n 0x0 0x0 ADC_RST ADC Controller Reset 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 CAN0_RST CAN0 Controller Reset 24 1 read-write 0 CAN0 controller normal operation #0 1 CAN0 controller reset #1 GPIO_RST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0_RST I2C0 Controller Reset 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1_RST I2C1 Controller Reset 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 SPI0_RST SPI0 Controller Reset 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 TMR0_RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1_RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2_RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3_RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0_RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1_RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 UART2_RST UART2 Controller Reset 18 1 read-write 0 UART2 controller normal operation #0 1 UART2 controller reset #1 IPRSTC3 IPRSTC3 Peripheral Reset Control Register 3 0x10 read-write n 0x0 0x0 BPWM0_RST BPWM0 Controller Reset 18 1 read-write 0 BPWM0 controller normal operation #0 1 BPWM0 controller reset #1 BPWM1_RST BPWM1 Controller Reset 19 1 read-write 0 BPWM1 controller normal operation #0 1 BPWM1 controller reset #1 PWM0_RST PWM0 Controller Reset 16 1 read-write 0 PWM0 controller normal operation #0 1 PWM0 controller reset #1 PWM1_RST PWM1 Controller Reset 17 1 read-write 0 PWM1 controller normal operation #0 1 PWM1 controller reset #1 UART3_RST UART3 Controller Reset 8 1 read-write 0 UART3 controller normal operation #0 1 UART3 controller reset #1 UART4_RST UART4 Controller Reset 9 1 read-write 0 UART4 controller normal operation #0 1 UART4 controller reset #1 UART5_RST UART5 Controller Reset 10 1 read-write 0 UART5 controller normal operation #0 1 UART5 controller reset #1 PDID PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCR PORCR Power-on-reset Controller Register 0x24 read-write n 0x0 0x0 POR_DIS_CODE Power-On-Reset Enable Control (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog Timer reset, Window Watchdog Timer reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function Note: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 16 read-write REGWRPROT REGWRPROT Register Write Protection Register 0x100 read-write n 0x0 0x0 REGPROTDIS Register Write-Protection Disable Index (Read Only) The Protected registers are: IPRSTC1: address 0x5000_0008 BODCR: address 0x5000_0018 PORCR: address 0x5000_0024 VREFCR: address 0x5000_0028 PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) APBCLK bit[0]: address 0x5000_0208 (bit[0] is Watchdog Timer clock enable) CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source selection) CLKSEL1 bit[1:0]: address 0x5000_0214 (for Watchdog Timer clock source selection) NMI_SEL bit[8]: address 0x5000_0380 (for NMI_EN clock source selection) ISPCON: address 0x5000_C000 (Flash ISP Control register) ISPTRG: address 0x5000_C010 (ISP Trigger Control register) FATCON: address 0x5000_C018 WTCR: address 0x4000_4000 WTCRALT: address 0x4000_4004 PWM_CTL0: address 0x4004_0000, 0x4014_0000 PWM_DTCTL0_1: address 0x4004_0070, 0x4014_0070 PWM_DTCTL2_3: address 0x4004_0074, 0x4014_0074 PWM_DTCTL4_5: address 0x4004_0078, 0x4014_0078 PWM_BRKCTL0_1: address 0x4004_00C8, 0x4014_00C8 PWM_BRKCTL2_3: address 0x4004_00CC, 0x4014_00CC PWM_BRKCTL4_5: address 0x4004_00D0, 0x4014_00D0 PWM_SWBRK: address 0x4004_00DC, 0x4014_00DC PWM_INTEN1: address 0x4004_00E4, 0x4014_00E4 PWM_INTSTS1: address 0x4004_00EC, 0x4014_00EC BPWM_CTL0: address 0x4004_4000, 0x4014_4000 Note: The bits which are write-protected will be noted as' (Write Protect)' beside the description. 0 1 read-only 0 Write-protection is enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection is disabled for writing protected registers #1 REGWRPROT Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. 1 7 write-only RSTSRC RSTSRC System Reset Source Register 0x4 read-write n 0x0 0x0 RSTS_BOD Brown-Out Detector Reset Flag The RSTS_BOD flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 RSTS_CPU CPU Reset Flag\nThe RSTS_CPU flag Is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 To reset Cortex-M0 coreand flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 Cortex-M0 CPU core and FMC are reset by software setting CPU_RST (IPRSTC1[1]) to 1 #1 RSTS_LVR Low Voltage Reset Flag The RSTS_LVR flag is set by the 'Reset Signal' from the Low-Voltage-Reset controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 The LVR controller had issued the reset signal to reset the system #1 RSTS_POR Power-On Reset Flag The RSTS_POR Flag is set by the 'Reset Signal' from the Power-On Reset (POR) vontroller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIP_RST (IPRSTC1[0]) #0 1 Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]) had issued the reset signal to reset the system #1 RSTS_RESET Reset Pin Reset Flag The RSTS_RESET flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 The Pin nRESET had issued the reset signal to reset the system #1 RSTS_SYS SYS Reset Flag The RSTS_SYS flag Is set by the 'Reset Signal' from the Cortex-M0 coreto indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel #1 RSTS_WDT Watchdog Timer Reset Flag The RSTS_WDT flag is set by the 'Reset Signal' from the watchdog timer or window watchdog timer to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: Watchdog Timer register WTRF (WTCR[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF (WWDTSR) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 VREFCR VREFCR VREF Controller Register 0x28 -1 read-write n 0x0 0x0 ADC_VREFSEL ADC VREF Path Control (Write Protect) Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 4 1 read-write 0 ADC VREF is from VREF pin #0 1 ADC VREF is from AVDD #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x24 registers n 0x180 0x4 registers n 0x200 0x90 registers n 0x298 0x18 registers n 0x2B8 0x8 registers n 0x2D8 0x8 registers n 0x2F8 0x8 registers n 0x314 0x4 registers n 0x340 0x8 registers n 0x350 0x14 registers n 0x40 0x24 registers n 0x80 0x24 registers n 0xC0 0x24 registers n DBNCECON DBNCECON External Interrupt De-bounce Control 0x180 read-write n 0x0 0x0 DBCLKSEL De-Bounce Sampling Cycle Selection\n 0 4 read-write DBCLKSRC De-Bounce Counter Clock Source Selection\n 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10 kHz low speed oscillator #1 ICLK_ON Interrupt Clock On Mode\nIt is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 GPIOA_DBEN GPIOA_DBEN GPIO Port A De-bounce Enable 0x14 read-write n 0x0 0x0 DBEN0 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 0 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN1 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 1 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN10 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 10 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN11 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 11 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN12 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 12 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN13 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 13 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN14 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 14 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN15 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 15 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN2 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 2 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN3 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 3 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN4 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 4 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN5 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 5 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN6 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 6 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN7 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 7 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN8 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 8 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 DBEN9 Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Control\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\n 9 1 read-write 0 Bit[n] de-bounce function Disabled #0 1 Bit[n] de-bounce function Enabled #1 GPIOA_DMASK GPIOA_DMASK GPIO Port A Data Output Write Mask 0xC read-write n 0x0 0x0 DMASK0 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 0 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK1 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 1 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK10 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 10 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK11 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 11 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK12 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 12 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK13 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 13 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK14 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 14 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK15 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 15 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK2 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 2 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK3 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 3 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK4 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 4 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK5 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 5 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK6 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 6 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK7 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 7 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK8 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 8 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 DMASK9 Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n 9 1 read-write 0 Corresponding GPIOx_DOUT[n] bit can be updated #0 1 Corresponding GPIOx_DOUT[n] bit protected #1 GPIOA_DOUT GPIOA_DOUT GPIO Port A Data Output Value 0x8 read-write n 0x0 0x0 DOUT0 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 0 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 1 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 10 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 11 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 12 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 13 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 14 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 15 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 2 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 3 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 4 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 5 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 6 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 7 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 8 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n 9 1 read-write 0 GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode #1 GPIOA_IEN GPIOA_IEN GPIO Port A Interrupt Enable 0x1C read-write n 0x0 0x0 IF_EN0 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 0 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN1 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 1 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN10 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 10 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN11 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 11 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN12 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 12 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN13 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 13 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN14 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 14 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN15 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 15 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN2 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 2 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN3 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 3 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN4 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 4 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN5 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 5 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN6 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 6 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN7 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 7 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN8 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 8 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IF_EN9 Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n 9 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 IR_EN0 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 16 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN1 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 17 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN10 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 26 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN11 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 27 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN12 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 28 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN13 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 29 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN14 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 30 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN15 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 31 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN2 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 18 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN3 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 19 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN4 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 20 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN5 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 21 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN6 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 22 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN7 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 23 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN8 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 24 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 IR_EN9 Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n 25 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 GPIOA_IMD GPIOA_IMD GPIO Port A Interrupt Mode Control 0x18 read-write n 0x0 0x0 IMD0 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD1 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD10 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD11 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD12 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD13 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD14 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD15 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD2 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD3 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD4 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD5 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD6 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD7 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD8 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD9 Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 GPIOA_ISRC GPIOA_ISRC GPIO Port A Interrupt Source Flag 0x20 read-write n 0x0 0x0 ISRC0 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 0 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC1 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 1 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC10 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 10 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC11 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 11 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC12 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 12 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC13 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 13 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC14 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 14 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC15 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 15 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC2 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 2 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC3 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 3 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC4 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 4 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC5 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 5 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC6 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 6 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC7 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 7 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC8 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 8 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 ISRC9 Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n 9 1 read-write 0 No interrupt at GPIOx[n].\nNo action #0 1 GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt #1 GPIOA_OFFD GPIOA_OFFD GPIO Port A Pin Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 OFFD0 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 16 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD1 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 17 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD10 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 26 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD11 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 27 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD12 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 28 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD13 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 29 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD14 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 30 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD15 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 31 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD2 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 18 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD3 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 19 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD4 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 20 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD5 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 21 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD6 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 22 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD7 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 23 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD8 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 24 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 OFFD9 GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n 25 1 read-write 0 I/O digital input path Enabled #0 1 I/O digital input path Disabled (digital input tied to low) #1 GPIOA_PIN GPIOA_PIN GPIO Port A Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 0 1 read-only PIN1 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 1 1 read-only PIN10 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 10 1 read-only PIN11 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 11 1 read-only PIN12 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 12 1 read-only PIN13 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 13 1 read-only PIN14 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 14 1 read-only PIN15 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 15 1 read-only PIN2 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 2 1 read-only PIN3 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 3 1 read-only PIN4 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 4 1 read-only PIN5 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 5 1 read-only PIN6 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 6 1 read-only PIN7 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 7 1 read-only PIN8 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 8 1 read-only PIN9 Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\nNote:\n 9 1 read-only GPIOA_PMD GPIOA_PMD GPIO Port A Pin I/O Mode Control 0x0 read-write n 0x0 0x0 PMD0 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 0 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD1 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 2 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD10 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 20 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD11 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 22 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD12 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 24 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD13 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 26 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD14 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 28 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD15 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 30 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD2 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 4 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD3 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 6 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD4 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 8 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD5 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 10 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD6 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 12 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD7 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 14 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD8 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 16 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 PMD9 GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nNote2:\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on. 18 2 read-write 0 GPIO port [n] pin is in Input mode #00 1 GPIO port [n] pin is in Push-pull Output mode #01 2 GPIO port [n] pin is in Open-drain Output mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 GPIOB_DBEN GPIOB_DBEN GPIO Port B De-bounce Enable 0x54 read-write n 0x0 0x0 GPIOB_DMASK GPIOB_DMASK GPIO Port B Data Output Write Mask 0x4C read-write n 0x0 0x0 GPIOB_DOUT GPIOB_DOUT GPIO Port B Data Output Value 0x48 read-write n 0x0 0x0 GPIOB_IEN GPIOB_IEN GPIO Port B Interrupt Enable 0x5C read-write n 0x0 0x0 GPIOB_IMD GPIOB_IMD GPIO Port B Interrupt Mode Control 0x58 read-write n 0x0 0x0 GPIOB_ISRC GPIOB_ISRC GPIO Port B Interrupt Source Flag 0x60 read-write n 0x0 0x0 GPIOB_OFFD GPIOB_OFFD GPIO Port B Pin Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 GPIOB_PIN GPIOB_PIN GPIO Port B Pin Value 0x50 read-write n 0x0 0x0 GPIOB_PMD GPIOB_PMD GPIO Port B Pin I/O Mode Control 0x40 read-write n 0x0 0x0 GPIOC_DBEN GPIOC_DBEN GPIO Port C De-bounce Enable 0x94 read-write n 0x0 0x0 GPIOC_DMASK GPIOC_DMASK GPIO Port C Data Output Write Mask 0x8C read-write n 0x0 0x0 GPIOC_DOUT GPIOC_DOUT GPIO Port C Data Output Value 0x88 read-write n 0x0 0x0 GPIOC_IEN GPIOC_IEN GPIO Port C Interrupt Enable 0x9C read-write n 0x0 0x0 GPIOC_IMD GPIOC_IMD GPIO Port C Interrupt Mode Control 0x98 read-write n 0x0 0x0 GPIOC_ISRC GPIOC_ISRC GPIO Port C Interrupt Source Flag 0xA0 read-write n 0x0 0x0 GPIOC_OFFD GPIOC_OFFD GPIO Port C Pin Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 GPIOC_PIN GPIOC_PIN GPIO Port C Pin Value 0x90 read-write n 0x0 0x0 GPIOC_PMD GPIOC_PMD GPIO Port C Pin I/O Mode Control 0x80 read-write n 0x0 0x0 GPIOD_DBEN GPIOD_DBEN GPIO Port D De-bounce Enable 0xD4 read-write n 0x0 0x0 GPIOD_DMASK GPIOD_DMASK GPIO Port D Data Output Write Mask 0xCC read-write n 0x0 0x0 GPIOD_DOUT GPIOD_DOUT GPIO Port D Data Output Value 0xC8 read-write n 0x0 0x0 GPIOD_IEN GPIOD_IEN GPIO Port D Interrupt Enable 0xDC read-write n 0x0 0x0 GPIOD_IMD GPIOD_IMD GPIO Port D Interrupt Mode Control 0xD8 read-write n 0x0 0x0 GPIOD_ISRC GPIOD_ISRC GPIO Port D Interrupt Source Flag 0xE0 read-write n 0x0 0x0 GPIOD_OFFD GPIOD_OFFD GPIO Port D Pin Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 GPIOD_PIN GPIOD_PIN GPIO Port D Pin Value 0xD0 read-write n 0x0 0x0 GPIOD_PMD GPIOD_PMD GPIO Port D Pin I/O Mode Control 0xC0 read-write n 0x0 0x0 GPIOE_DBEN GPIOE_DBEN GPIO Port E De-bounce Enable 0x114 read-write n 0x0 0x0 GPIOE_DMASK GPIOE_DMASK GPIO Port E Data Output Write Mask 0x10C read-write n 0x0 0x0 GPIOE_DOUT GPIOE_DOUT GPIO Port E Data Output Value 0x108 read-write n 0x0 0x0 GPIOE_IEN GPIOE_IEN GPIO Port E Interrupt Enable 0x11C read-write n 0x0 0x0 GPIOE_IMD GPIOE_IMD GPIO Port E Interrupt Mode Control 0x118 read-write n 0x0 0x0 GPIOE_ISRC GPIOE_ISRC GPIO Port E Interrupt Source Flag 0x120 read-write n 0x0 0x0 GPIOE_OFFD GPIOE_OFFD GPIO Port E Pin Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 GPIOE_PIN GPIOE_PIN GPIO Port E Pin Value 0x110 read-write n 0x0 0x0 GPIOE_PMD GPIOE_PMD GPIO Port E Pin I/O Mode Control 0x100 read-write n 0x0 0x0 GPIOF_DBEN GPIOF_DBEN GPIO Port F De-bounce Enable 0x154 read-write n 0x0 0x0 GPIOF_DMASK GPIOF_DMASK GPIO Port F Data Output Write Mask 0x14C read-write n 0x0 0x0 GPIOF_DOUT GPIOF_DOUT GPIO Port F Data Output Value 0x148 read-write n 0x0 0x0 GPIOF_IEN GPIOF_IEN GPIO Port F Interrupt Enable 0x15C read-write n 0x0 0x0 GPIOF_IMD GPIOF_IMD GPIO Port F Interrupt Mode Control 0x158 read-write n 0x0 0x0 GPIOF_ISRC GPIOF_ISRC GPIO Port F Interrupt Source Flag 0x160 read-write n 0x0 0x0 GPIOF_OFFD GPIOF_OFFD GPIO Port F Pin Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 GPIOF_PIN GPIOF_PIN GPIO Port F Pin Value 0x150 read-write n 0x0 0x0 GPIOF_PMD GPIOF_PMD GPIO Port F Pin I/O Mode Control 0x140 read-write n 0x0 0x0 PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output 0x200 read-write n 0x0 0x0 Pxn_PDIO GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0], read PA0_PDIO will return the value of GPIOA_PIN[0].\nNote: The write operation will not be affected by register GPIOx_DMASK. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output 0x228 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output 0x22C read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output 0x230 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output 0x234 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output 0x238 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output 0x23C read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output 0x204 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output 0x208 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output 0x20C read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output 0x210 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output 0x214 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output 0x218 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output 0x21C read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output 0x220 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output 0x224 read-write n 0x0 0x0 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output 0x240 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output 0x268 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output 0x26C read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output 0x270 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output 0x274 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output 0x278 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output 0x27C read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output 0x244 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output 0x248 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output 0x24C read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output 0x250 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output 0x254 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output 0x258 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output 0x25C read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output 0x260 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output 0x264 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output 0x280 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output 0x2A8 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output 0x2AC read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.n Pin Data Input/Output 0x2B8 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.n Pin Data Input/Output 0x2BC read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output 0x284 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output 0x288 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output 0x28C read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output 0x298 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output 0x29C read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output 0x2A0 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output 0x2A4 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output 0x2F8 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output 0x2FC read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output 0x2D8 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output 0x2DC read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.n Pin Data Input/Output 0x314 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output 0x340 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output 0x344 read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output 0x350 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.n Pin Data Input/Output 0x354 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.n Pin Data Input/Output 0x358 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.n Pin Data Input/Output 0x35C read-write n 0x0 0x0 PF8_PDIO PF8_PDIO GPIO PF.n Pin Data Input/Output 0x360 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x8 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 GC General Call Function\n 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 I2CADM I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2CADM1 I2CADM1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C Data Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divided Register 0x10 read-write n 0x0 0x0 I2CLK I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4. 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control\n 2 1 read-write EI Interrupt Enable Control\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 ENS1 I2C Controller Enable Control\n 6 1 read-write 0 Disabled #0 1 Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC read-only n 0x0 0x0 I2CSTATUS I2C Status Register\nThere are 26 possible status codes. \nWhen I2CSTATUS contains 0xF8, no serial interrupt is requested. \nIn addition, states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 0 8 read-only I2CTOC I2CTOC I2C Time-out Counter Register 0x14 read-write n 0x0 0x0 DIV4 Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times. 1 1 read-write 0 Disabled #0 1 Enabled #1 ENTI Time-Out Counter Enable Control \nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared. 2 1 read-write 0 Disabled #0 1 Enabled #1 TIF Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI (I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit. 0 1 read-write I2CWKUPCON I2CWKUPCON I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 WKUPEN I2C Wake-Up Enable Control\n 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2CWKUPSTS I2CWKUPSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKUPIF I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit. 0 1 read-write 0 Chip is not woken-up from Power-down mode by I2C #0 1 Chip is woken-up from Power-down mode by I2C #1 I2C1 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x8 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 GC General Call Function\n 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 I2CADM I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2CADM1 I2CADM1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C Data Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divided Register 0x10 read-write n 0x0 0x0 I2CLK I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4. 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control\n 2 1 read-write EI Interrupt Enable Control\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 ENS1 I2C Controller Enable Control\n 6 1 read-write 0 Disabled #0 1 Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC read-only n 0x0 0x0 I2CSTATUS I2C Status Register\nThere are 26 possible status codes. \nWhen I2CSTATUS contains 0xF8, no serial interrupt is requested. \nIn addition, states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 0 8 read-only I2CTOC I2CTOC I2C Time-out Counter Register 0x14 read-write n 0x0 0x0 DIV4 Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times. 1 1 read-write 0 Disabled #0 1 Enabled #1 ENTI Time-Out Counter Enable Control \nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared. 2 1 read-write 0 Disabled #0 1 Enabled #1 TIF Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI (I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit. 0 1 read-write I2CWKUPCON I2CWKUPCON I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 WKUPEN I2C Wake-Up Enable Control\n 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2CWKUPSTS I2CWKUPSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKUPIF I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit. 0 1 read-write 0 Chip is not woken-up from Power-down mode by I2C #0 1 Chip is woken-up from Power-down mode by I2C #1 INT INT Register Map INT 0x0 0x0 0x8C registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source\nDefine the interrupt sources for interrupt event. 0 4 read-only IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) Interrupt Source Identity 0x28 read-write n 0x0 0x0 IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) Interrupt Source Identity 0x2C read-write n 0x0 0x0 IRQ12_SRC IRQ12_SRC IRQ12 (UART0/2) Interrupt Source Identity 0x30 read-write n 0x0 0x0 IRQ13_SRC IRQ13_SRC IRQ13 (UART1) Interrupt Source Identity 0x34 read-write n 0x0 0x0 IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity 0x38 read-write n 0x0 0x0 IRQ15_SRC IRQ15_SRC IRQ15 (UART3) Interrupt Source Identity 0x3C read-write n 0x0 0x0 IRQ16_SRC IRQ16_SRC IRQ16 (UART4) Interrupt Source Identity 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC IRQ17 (UART5) Interrupt Source Identity 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) Interrupt Source Identity 0x48 read-write n 0x0 0x0 IRQ19_SRC IRQ19_SRC IRQ19 (I2C1) Interrupt Source Identity 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity 0x4 read-write n 0x0 0x0 IRQ20_SRC IRQ20_SRC IRQ20 (CAN0) Interrupt Source Identity 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC Reserved 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC IRQ22 (PWM0) Interrupt Source Identity 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC IRQ23 (PWM1) Interrupt Source Identity 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC IRQ24 (BPWM0) Interrupt Source Identity 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC IRQ25 (BPWM1) Interrupt Source Identity 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC IRQ26 (BRAKE0) Interrupt Source Identity 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC IRQ27 (BRAKE1) Interrupt Source Identity 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) Interrupt Source Identity 0x70 read-write n 0x0 0x0 IRQ29_SRC IRQ29_SRC IRQ29 (ADC) Interrupt Source Identity 0x74 read-write n 0x0 0x0 IRQ2_SRC IRQ2_SRC IRQ2 (EINT0) Interrupt Source Identity 0x8 read-write n 0x0 0x0 IRQ30_SRC IRQ30_SRC IRQ30 (CKD) Interrupt Source Identity 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC Reserved 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC IRQ3 (EINT1) Interrupt Source Identity 0xC read-write n 0x0 0x0 IRQ4_SRC IRQ4_SRC IRQ4 (GPA/B) Interrupt Source Identity 0x10 read-write n 0x0 0x0 IRQ5_SRC IRQ5_SRC IRQ5 (GPC/D/E/F) Interrupt Source Identity 0x14 read-write n 0x0 0x0 IRQ6_SRC IRQ6_SRC Reserved 0x18 read-write n 0x0 0x0 IRQ7_SRC IRQ7_SRC Reserved 0x1C read-write n 0x0 0x0 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity 0x20 read-write n 0x0 0x0 IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity 0x24 read-write n 0x0 0x0 MCU_IRQ MCU_IRQ MCU Interrupt Request Source Register 0x84 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0: has no effect. 0 32 read-write MCU_IRQCR MCU_IRQCR MCU Interrupt Request Control Register 0x88 read-write n 0x0 0x0 FAST_IRQ Fast IRQ Latency Enable Control\n 0 1 read-write 0 MCU IRQ latency is fixed at 13 clock cycles of HCLK, MCU will enter IRQ handler after this fixed latency when interrupt happened #0 1 MCU IRQ latency will not fixed, MCU will enter IRQ handler as soon as possible when interrupt happened #1 NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_EN NMI Interrupt Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 8 1 read-write 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. 0 5 read-write PWM0 PWM Register Map PWM 0x0 0x0 0x8 registers n 0x10 0x18 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x30C 0x4 registers n 0x314 0x4 registers n 0x31C 0x18 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x90 0x4 registers n 0x98 0x4 registers n 0xA0 0x4 registers n 0xB0 0x40 registers n 0xF8 0x8 registers n PWM_ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC Enable Control 7 1 read-write TRGEN1 PWM_CH1 Trigger ADC Enable Control 15 1 read-write TRGEN2 PWM_CH2 Trigger ADC Enable Control 23 1 read-write TRGEN3 PWM_CH3 Trigger ADC Enable Control 31 1 read-write TRGSEL0 PWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL1 PWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL2 PWM_CH2 Trigger ADC Source Select\n 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 TRGSEL3 PWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 PWM_ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC Enable Control 7 1 read-write TRGEN5 PWM_CH5 Trigger ADC Enable Control 15 1 read-write TRGSEL4 PWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 TRGSEL5 PWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting:\n 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting:\n 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0FCS Brake 0 Edge Detector Filter Clock Selection\n 1 3 read-write 0 Filter clock is HCLK #000 1 Filter clock is HCLK/2 #001 2 Filter clock is HCLK/4 #010 3 Filter clock is HCLK/8 #011 4 Filter clock is HCLK/16 #100 5 Filter clock is HCLK/32 #101 6 Filter clock is HCLK/64 #110 7 Filter clock is HCLK/128 #111 BRK0FEN PWM Brake 0 Noise Filter Enable Control\n 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0PINV Brake 0 Pin Inverse\n 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1FCS Brake 1 Edge Detector Filter Clock Selection\n 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1FEN PWM Brake 1 Noise Filter Enable Control\n 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1PINV Brake 1 Pin Inverse\n 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0_1 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select For Even Channel (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select For Odd Channel (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEEN Enable System Fail As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLEN Enable System Fail As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2_3 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4_5 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Control\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Control\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Control\nEach bit n controls the corresponding PWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Control\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM Capture Falling Latch Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM Capture Rising Latch Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin 1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0_1 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-Scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2_3 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4_5 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select\n 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select\n 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select\n 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR2 Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.\n 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR4 Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.\n 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable 0\n 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable 2\n 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable 4\n 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-Load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to REGWRPROT register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to REGWRPROT register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDENn Immediately Load Enable control\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 PWM Counter Behavior Type 0\nEach bit n controls corresponding PWM channel n.\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 PWM Counter Behavior Type 2\nEach bit n controls corresponding PWM channel n.\n 4 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 PWM Counter Behavior Type 4\nEach bit n controls corresponding PWM channel n.\n 8 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 PWMMODEn PWM Mode\nEach bit n controls the corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0_1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-Time Clock Select (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-Time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to REGWRPROT register. 0 12 read-write DTEN Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to REGWRPROT register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2_3 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4_5 0x78 read-write n 0x0 0x0 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-Out Detection Trigger PWM Brake Function 0 Enable Control\n 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Control\n 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Control\n 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM Compare Down Count Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM Compare Up Count Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 PWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable 2\nNote: When up-down counter type period point means center point. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable 4\nNote: When up-down counter type period point means center point. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable 2\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable 4\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write PIF2 PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2, software can write 1 to clear this bit to zero. 10 1 read-write PIF4 PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4, software can write 1 to clear this bit to zero. 12 1 read-write ZIF0 PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF2 PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF4 PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 0 1 read-write 0 PWM channel0 edge-detect brake event do not happened #0 1 When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 1 1 read-write 0 PWM channel1 edge-detect brake event do not happened #0 1 When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 2 1 read-write 0 PWM channel2 edge-detect brake event do not happened #0 1 When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 3 1 read-write 0 PWM channel3 edge-detect brake event do not happened #0 1 When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 4 1 read-write 0 PWM channel4 edge-detect brake event do not happened #0 1 When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 5 1 read-write 0 PWM channel5 edge-detect brake event do not happened #0 1 When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel0 Edge-Detect Brake Status\n 16 1 read-write 0 PWM channel0 edge-detect brake state is released #0 1 When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear #1 BRKESTS1 PWM Channel1 Edge-Detect Brake Status\n 17 1 read-write 0 PWM channel1 edge-detect brake state is released #0 1 When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear #1 BRKESTS2 PWM Channel2 Edge-Detect Brake Status\n 18 1 read-write 0 PWM channel2 edge-detect brake state is released #0 1 When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear #1 BRKESTS3 PWM Channel3 Edge-Detect Brake Status\n 19 1 read-write 0 PWM channel3 edge-detect brake state is released #0 1 When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear #1 BRKESTS4 PWM Channel4 Edge-Detect Brake Status\n 20 1 read-write 0 PWM channel4 edge-detect brake state is released #0 1 When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear #1 BRKESTS5 PWM Channel5 Edge-Detect Brake Status\n 21 1 read-write 0 PWM channel5 edge-detect brake state is released #0 1 When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear #1 BRKLIF0 PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 8 1 read-write 0 PWM channel0 level-detect brake event do not happened #0 1 When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 9 1 read-write 0 PWM channel1 level-detect brake event do not happened #0 1 When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 10 1 read-write 0 PWM channel2 level-detect brake event do not happened #0 1 When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 11 1 read-write 0 PWM channel3 level-detect brake event do not happened #0 1 When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 12 1 read-write 0 PWM channel4 level-detect brake event do not happened #0 1 When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 13 1 read-write 0 PWM channel5 level-detect brake event do not happened #0 1 When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel0 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel0 level-detect brake state is released #0 1 When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKLSTS1 PWM Channel1 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel1 level-detect brake state is released #0 1 When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKLSTS2 PWM Channel2 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel2 level-detect brake state is released #0 1 When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKLSTS3 PWM Channel3 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel3 level-detect brake state is released #0 1 When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKLSTS4 PWM Channel4 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel4 level-detect brake state is released #0 1 When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKLSTS5 PWM Channel5 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel5 level-detect brake state is released #0 1 When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Output logic low to PWMn 0 1 Output logic high to PWMn 1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM Mask Enable Control\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. \n 0 6 read-write 0 PWM output signal is non-masked 0 1 PWM output signal is masked and output MSKDATn data 1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM Pin Output Enable Control\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM pin at tri-state 0 1 PWM pin in output mode 1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM output polar inverse Disabled 0 1 PWM output polar inverse Enabled 1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.\nNote: This bit only present in PWM0_BA. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start Of Conversion Status\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-Base Counter 0 Equal To 0xFFFF Latched Status\n 0 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX2 Time-Base Counter 2 Equal To 0xFFFF Latched Status\n 2 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX4 Time-Base Counter 4 Equal To 0xFFFF Latched Status\n 4 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to REGWRPROT register. 0 3 write-only BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to REGWRPROT register. 8 3 write-only PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 PWM period (center) point output Low 01 10 PWM period (center) point output High 10 11 PWM period (center) point output Toggle 11 ZPCTLn PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 PWM zero point output Low 01 10 PWM zero point output High 10 11 PWM zero point output Toggle 11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 PWM compare down point output Low 01 10 PWM compare down point output High 10 11 PWM compare down point output Toggle 11 CMPUCTLn PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 PWM compare up point output Low 01 10 PWM compare up point output High 10 11 PWM compare up point output Toggle 11 PWM1 PWM Register Map PWM 0x0 0x0 0x8 registers n 0x10 0x18 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x30C 0x4 registers n 0x314 0x4 registers n 0x31C 0x18 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x90 0x4 registers n 0x98 0x4 registers n 0xA0 0x4 registers n 0xB0 0x40 registers n 0xF8 0x8 registers n PWM_ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC Enable Control 7 1 read-write TRGEN1 PWM_CH1 Trigger ADC Enable Control 15 1 read-write TRGEN2 PWM_CH2 Trigger ADC Enable Control 23 1 read-write TRGEN3 PWM_CH3 Trigger ADC Enable Control 31 1 read-write TRGSEL0 PWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL1 PWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL2 PWM_CH2 Trigger ADC Source Select\n 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 TRGSEL3 PWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 PWM_ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC Enable Control 7 1 read-write TRGEN5 PWM_CH5 Trigger ADC Enable Control 15 1 read-write TRGSEL4 PWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 TRGSEL5 PWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting:\n 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting:\n 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0FCS Brake 0 Edge Detector Filter Clock Selection\n 1 3 read-write 0 Filter clock is HCLK #000 1 Filter clock is HCLK/2 #001 2 Filter clock is HCLK/4 #010 3 Filter clock is HCLK/8 #011 4 Filter clock is HCLK/16 #100 5 Filter clock is HCLK/32 #101 6 Filter clock is HCLK/64 #110 7 Filter clock is HCLK/128 #111 BRK0FEN PWM Brake 0 Noise Filter Enable Control\n 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0PINV Brake 0 Pin Inverse\n 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1FCS Brake 1 Edge Detector Filter Clock Selection\n 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1FEN PWM Brake 1 Noise Filter Enable Control\n 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1PINV Brake 1 Pin Inverse\n 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0_1 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select For Even Channel (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select For Odd Channel (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEEN Enable System Fail As Edge-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLEN Enable System Fail As Level-Detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2_3 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4_5 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Control\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Control\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Control\nEach bit n controls the corresponding PWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Control\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM Capture Falling Latch Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM Capture Rising Latch Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin 1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0_1 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-Scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2_3 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4_5 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select\n 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select\n 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select\n 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR2 Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.\n 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR4 Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.\n 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable 0\n 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable 2\n 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable 4\n 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-Load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to REGWRPROT register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to REGWRPROT register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDENn Immediately Load Enable control\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 PWM Counter Behavior Type 0\nEach bit n controls corresponding PWM channel n.\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 PWM Counter Behavior Type 2\nEach bit n controls corresponding PWM channel n.\n 4 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 PWM Counter Behavior Type 4\nEach bit n controls corresponding PWM channel n.\n 8 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 PWMMODEn PWM Mode\nEach bit n controls the corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0_1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-Time Clock Select (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-Time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to REGWRPROT register. 0 12 read-write DTEN Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to REGWRPROT register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2_3 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4_5 0x78 read-write n 0x0 0x0 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-Out Detection Trigger PWM Brake Function 0 Enable Control\n 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Control\n 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Control\n 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM Compare Down Count Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM Compare Up Count Interrupt Enable Control\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 PWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable 2\nNote: When up-down counter type period point means center point. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable 4\nNote: When up-down counter type period point means center point. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable 2\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable 4\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write PIF2 PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2, software can write 1 to clear this bit to zero. 10 1 read-write PIF4 PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4, software can write 1 to clear this bit to zero. 12 1 read-write ZIF0 PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF2 PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF4 PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 0 1 read-write 0 PWM channel0 edge-detect brake event do not happened #0 1 When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 1 1 read-write 0 PWM channel1 edge-detect brake event do not happened #0 1 When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 2 1 read-write 0 PWM channel2 edge-detect brake event do not happened #0 1 When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 3 1 read-write 0 PWM channel3 edge-detect brake event do not happened #0 1 When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 4 1 read-write 0 PWM channel4 edge-detect brake event do not happened #0 1 When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 5 1 read-write 0 PWM channel5 edge-detect brake event do not happened #0 1 When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel0 Edge-Detect Brake Status\n 16 1 read-write 0 PWM channel0 edge-detect brake state is released #0 1 When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear #1 BRKESTS1 PWM Channel1 Edge-Detect Brake Status\n 17 1 read-write 0 PWM channel1 edge-detect brake state is released #0 1 When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear #1 BRKESTS2 PWM Channel2 Edge-Detect Brake Status\n 18 1 read-write 0 PWM channel2 edge-detect brake state is released #0 1 When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear #1 BRKESTS3 PWM Channel3 Edge-Detect Brake Status\n 19 1 read-write 0 PWM channel3 edge-detect brake state is released #0 1 When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear #1 BRKESTS4 PWM Channel4 Edge-Detect Brake Status\n 20 1 read-write 0 PWM channel4 edge-detect brake state is released #0 1 When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear #1 BRKESTS5 PWM Channel5 Edge-Detect Brake Status\n 21 1 read-write 0 PWM channel5 edge-detect brake state is released #0 1 When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear #1 BRKLIF0 PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 8 1 read-write 0 PWM channel0 level-detect brake event do not happened #0 1 When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 9 1 read-write 0 PWM channel1 level-detect brake event do not happened #0 1 When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 10 1 read-write 0 PWM channel2 level-detect brake event do not happened #0 1 When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 11 1 read-write 0 PWM channel3 level-detect brake event do not happened #0 1 When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 12 1 read-write 0 PWM channel4 level-detect brake event do not happened #0 1 When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 13 1 read-write 0 PWM channel5 level-detect brake event do not happened #0 1 When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel0 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel0 level-detect brake state is released #0 1 When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKLSTS1 PWM Channel1 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel1 level-detect brake state is released #0 1 When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKLSTS2 PWM Channel2 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel2 level-detect brake state is released #0 1 When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKLSTS3 PWM Channel3 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel3 level-detect brake state is released #0 1 When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKLSTS4 PWM Channel4 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel4 level-detect brake state is released #0 1 When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKLSTS5 PWM Channel5 Level-Detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel5 level-detect brake state is released #0 1 When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Output logic low to PWMn 0 1 Output logic high to PWMn 1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM Mask Enable Control\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. \n 0 6 read-write 0 PWM output signal is non-masked 0 1 PWM output signal is masked and output MSKDATn data 1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM Pin Output Enable Control\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM pin at tri-state 0 1 PWM pin in output mode 1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM output polar inverse Disabled 0 1 PWM output polar inverse Enabled 1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.\nNote: This bit only present in PWM0_BA. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start Of Conversion Status\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-Base Counter 0 Equal To 0xFFFF Latched Status\n 0 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX2 Time-Base Counter 2 Equal To 0xFFFF Latched Status\n 2 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX4 Time-Base Counter 4 Equal To 0xFFFF Latched Status\n 4 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to REGWRPROT register. 0 3 write-only BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to REGWRPROT register. 8 3 write-only PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 PWM period (center) point output Low 01 10 PWM period (center) point output High 10 11 PWM period (center) point output Toggle 11 ZPCTLn PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 PWM zero point output Low 01 10 PWM zero point output High 10 11 PWM zero point output Toggle 11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 PWM compare down point output Low 01 10 PWM compare down point output High 10 11 PWM compare down point output Toggle 11 CMPUCTLn PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 PWM compare up point output Low 01 10 PWM compare up point output High 10 11 PWM compare up point output Toggle 11 SCS SYST_NVIC_SCS Register Map SYST_NVIC_SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C read-write n 0x0 0x0 SYSRESETREQ System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable. 1 1 read-write VECTORKEY Register Access Key\nWrite Operation:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead Operation:\nRead as 0xFA05. 16 16 read-write CPUID CPUID CPUID Register 0xD00 read-only n 0x0 0x0 IMPLEMENTER Implementer Code Assigned By ARM\n 24 8 read-only PART Architecture Of The Processor\nRead as 0xC for ARMv6-M parts. 16 4 read-only PARTNO Part Number Of The Processor\nRead as 0xC20. 4 12 read-only REVISION Revision Number\nRead as 0x0. 0 4 read-only ICSR ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI And Faults:\nThis bit is read only. 22 1 read-write 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT If Set, A Pending Exception Will Be Serviced On Exit From The Debug Halt State\nThis bit is read only. 23 1 read-write NMIPENDSET NMI Set-Pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect.\nNMI exception not pending #0 1 Changes NMI exception state to pending.\nNMI exception pending #1 PENDSTCLR SysTick Exception Clear-Pending Bit\nWrite Operation:\nThis is a write only bit. When you want to clear PENDST bit, you must "write 0 to PENDSTSET and write 1 to PENDSTCLR" at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-Pending Bit\nWrite Operation:\n 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-Pending Bit\nWrite Operation:\nThis is a write only bit. When you want to clear PENDSV bit, you must "write 0 to PENDSVSET and write 1 to PENDSVCLR" at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-Pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains The Active Exception Number\n 0 6 read-write 0 Thread mode 0 VECTPENDING Indicates The Exception Number Of The Highest Priority Pending Enabled Exception:\n 12 6 read-write 0 No pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Interrupt Disable Control\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority Of IRQ0\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_1 Priority Of IRQ1\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_2 Priority Of IRQ2\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_3 Priority Of IRQ3\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority Of IRQ4\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_5 Priority Of IRQ5\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_6 Priority Of IRQ6\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_7 Priority Of IRQ7\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority Of IRQ10\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_11 Priority Of IRQ11\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write PRI_8 Priority Of IRQ8\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_9 Priority Of IRQ9\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority Of IRQ12\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_13 Priority Of IRQ13\n"0" denotes the highest priority and "3" denotes the lowest priority 14 2 read-write PRI_14 Priority Of IRQ14\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_15 Priority Of IRQ15\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority Of IRQ16\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_17 Priority Of IRQ17\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_18 Priority Of IRQ18\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_19 Priority Of IRQ19\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority Of IRQ20\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_21 Priority Of IRQ21\n"0" denotes the highest priority and "3" denotes the lowest priority 14 2 read-write PRI_22 Priority Of IRQ22\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_23 Priority Of IRQ23\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority Of IRQ24\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_25 Priority Of IRQ25\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_26 Priority Of IRQ26\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_27 Priority Of IRQ27\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority Of IRQ28\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_29 Priority Of IRQ29\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_30 Priority Of IRQ30\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_31 Priority Of IRQ31\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-enable Control Register 0x100 read-write n 0x0 0x0 SETENA Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Set Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event On Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLEEPDEEP Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-On-Exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep or Deep Sleep when returning from ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority Of System Handler 11 - SVCall\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority Of System Handler 14 - PendSV\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_15 Priority Of System Handler 15 - SysTick\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write SYST_CSR SYST_CSR SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection\n 2 1 read-write 0 Clock source is (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled\n 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled\n 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD Value to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n 0x3C 0xC registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 FIFO FIFO Mode Enable Control\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.\nAfter clearing this bit to 0, user must wait for at least 2 peripheral clock periods before setting this bit to 1 again. 21 1 read-write 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 GO_BUSY SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote: When FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit. 0 1 read-write 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Unit Transfer Interrupt EnableBit\n 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 LSB Send LSB First\n 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) #1 REORDER Byte Reorder Function EnableBit\nNote:\nByte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe Byte Reorder function is not supported when the variable bus clock function or Dual I/O mode is enabled. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n 25 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RX_NEG Receive On Negative Edge\n 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 SLAVE Slave Mode EnableBit\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPI bus clock cycle. 12 4 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_NEG Transmit On Negative Edge\n 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 VARCLK_EN Variable Clock Enable Control (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). 23 1 read-write 0 SPI clock output frequency is fixed and decided only by the value of DIVIDER #0 1 SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C read-write n 0x0 0x0 BCn SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. 31 1 read-write 0 Backward compatible clock configuration #0 1 Clock configuration is not backward compatible #1 DUAL_IO_DIR Dual I/O Mode Direction Control\n 12 1 read-write 0 Dual Input mode #0 1 Dual Output mode #1 DUAL_IO_EN Dual I/O Mode EnableBit\n 13 1 read-write 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 NOSLVSEL Slave 3-Wire Mode Enable Control\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO0 and SPI0_MOSI0 pins.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. 8 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLV_ABORT Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write SLV_START_INTSTS Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 SSTA_INTEN Slave 3-Wire Mode Start Interrupt Enable Control\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 read-write 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register. 0 8 read-write DIVIDER2 Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. 16 8 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 read-write n 0x0 0x0 RXOV_INTEN Receive FIFO Overrun Interrupt Enable Control\n 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RX_CLR Clear Receive FIFO Buffer\n 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 RX_INTEN Receive Threshold Interrupt Enable Control\n 2 1 read-write 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TIMEOUT_INTEN Receive FIFO Time-Out Interrupt Enable Control\n 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TX_CLR Clear Transmit FIFO Buffer\n 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 TX_INTEN Transmit Threshold Interrupt Enable Control\n 3 1 read-write 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable Control (Master Only)\n 3 1 read-write 0 If this bit is cleared, slave select signal will be asserted/de-asserted by setting /clearing the corresponding bit of SPI_SSR[0] #0 1 If this bit is set, SPI0_SPISS0 signal will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. 5 1 read-write 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN #1 SSR Slave Select Control Bit (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPI0_SPISS0 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI0_SPISS0 line at inactive state; writing 1 to any bit location of this field will select appropriate SPI0_SPISS0 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI0_SPISS0 is specified in SS_LVL. \nNote: SPI0_SPISS0 is defined as the slave select input in Slave mode. 0 1 read-write SS_LTRIG Slave Select Level Trigger Enable Control (Slave Only)\n 4 1 read-write 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI0_SPISS0).\n 2 1 read-write 0 The slave select signal SPI0_SPISS0 is active on low-level/falling-edge #0 1 The slave select signal SPI0_SPISS0 is active on high-level/rising-edge #1 SPI_STATUS SPI_STATUS SPI Status Register 0x44 read-write n 0x0 0x0 IF SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n 25 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 read-only 0 The valid data count within the Rx FIFO buffer is less than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 read-write 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 TIMEOUT Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n 26 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n 27 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote 1: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1.\nNote 2: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles since user wrote to this register. 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register 0x34 read-write n 0x0 0x0 VARCLK Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. 0 32 read-write TMR01 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TCAP0 TCAP0 Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 TCAP Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately. 0 24 read-only TCAP1 TCAP1 Timer1 Capture Data Register 0x30 read-write n 0x0 0x0 TCMPR0 TCMPR0 Timer0 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if user writes a new value into TCMP field. 0 24 read-write TCMPR1 TCMPR1 Timer1 Compare Register 0x24 read-write n 0x0 0x0 TCSR0 TCSR0 Timer0 Control and Status Register 0x0 read-write n 0x0 0x0 CACT Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CEN Timer Enable Control\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset\n 26 1 read-write 0 No effect #0 1 Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1 #1 CTB Counter Mode Enable Control \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.6.5.6 for detail description.\n 24 1 read-write 0 External counter mode Disabled #0 1 External counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 IE Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag TIF (TISR[0]) is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt function Disabled #0 1 Timer Interrupt function Enabled #1 MODE Timer Operating Mode\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PRESCALE Prescale Counter\n 0 8 read-write TDR_EN Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while Timer counter is active #1 TRG_PWM_EN Trigger PWM Enable Control\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.\n 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 If TRG_SRC_SEL (TCSR[18]) = 0, time-out interrupt signal will trigger PWM #1 TRG_SRC_SEL Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.\n 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM #0 1 Capture interrupt signal is used to trigger PWM #1 WAKE_EN Wake Up Function Enable Control\n 23 1 read-write 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 TCSR1 TCSR1 Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TDR0 TDR0 Timer0 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR register will be updated continuously to monitor 24-bit up counter value. 0 24 read-only TDR1 TDR1 Timer1 Data Register 0x2C read-write n 0x0 0x0 TEXCON0 TEXCON0 Timer0 External Control Register 0x14 read-write n 0x0 0x0 RSTCAPSEL Timer External Reset Counter / Timer External Capture Mode Selection\n 4 1 read-write 0 Transition on TMx_EXT pin is using to save the TDR value into TCAP.(event capture function) #0 1 Transition on TMx_EXT pin is using to reset the 24-bit up counter.(event reset counter function) #1 TCDB Timer External Counter Input Pin De-Bounce Enable Control\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx pin de-bounce Disabled #0 1 TMx pin de-bounce Enabled #1 TEXDB Timer External Capture Input Pin De-Bounce Enable Control\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT pin de-bounce Disabled #0 1 TMx_EXT pin de-bounce Enabled #1 TEXEN Timer External Pin Function Enable Control\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n 3 1 read-write 0 RSTCAPSEL function of TMx_EXT pin will be ignored #0 1 RSTCAPSEL function of TMx_EXT pin is active #1 TEXIEN Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1. 5 1 read-write 0 TMx_EXT pin detection Interrupt Disabled #0 1 TMx_EXT pin detection Interrupt Enabled #1 TEX_EDGE Timer External Capture Pin Edge Detect Selection\n 1 2 read-write 0 A 1 to 0 transition on TMx_EXT pin will be detected #00 1 A 0 to 1 transition on TMx_EXT pin will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected #10 3 Reserved #11 TX_PHASE Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n 0 1 read-write 0 A falling edge of TMx_EXT pin will be counted #0 1 A rising edge of TMx_EXT pin will be counted #1 TEXCON1 TEXCON1 Timer1 External Control Register 0x34 read-write n 0x0 0x0 TEXISR0 TEXISR0 Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 TEXIF Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled, TMx_EXT pin selected as external capture function, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1]) setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 TMx_EXT pin interrupt did not occur #0 1 TMx_EXT pin interrupt occurred #1 TEXISR1 TEXISR1 Timer1 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TISR0 TISR0 Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 TDR value matches the TCMP value #1 TWF Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated #1 TISR1 TISR1 Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TCAP2 TCAP2 Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 TCAP Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately. 0 24 read-only TCAP3 TCAP3 Timer3 Capture Data Register 0x30 read-write n 0x0 0x0 TCMPR2 TCMPR2 Timer2 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if user writes a new value into TCMP field. 0 24 read-write TCMPR3 TCMPR3 Timer3 Compare Register 0x24 read-write n 0x0 0x0 TCSR2 TCSR2 Timer2 Control and Status Register 0x0 read-write n 0x0 0x0 CACT Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CEN Timer Enable Control\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset\n 26 1 read-write 0 No effect #0 1 Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1 #1 CTB Counter Mode Enable Control \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.6.5.6 for detail description.\n 24 1 read-write 0 External counter mode Disabled #0 1 External counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 IE Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag TIF (TISR[0]) is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt function Disabled #0 1 Timer Interrupt function Enabled #1 MODE Timer Operating Mode\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PRESCALE Prescale Counter\n 0 8 read-write TDR_EN Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while Timer counter is active #1 TRG_PWM_EN Trigger PWM Enable Control\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.\n 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 If TRG_SRC_SEL (TCSR[18]) = 0, time-out interrupt signal will trigger PWM #1 TRG_SRC_SEL Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.\n 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM #0 1 Capture interrupt signal is used to trigger PWM #1 WAKE_EN Wake Up Function Enable Control\n 23 1 read-write 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 TCSR3 TCSR3 Timer3 Control and Status Register 0x20 read-write n 0x0 0x0 TDR2 TDR2 Timer2 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR register will be updated continuously to monitor 24-bit up counter value. 0 24 read-only TDR3 TDR3 Timer3 Data Register 0x2C read-write n 0x0 0x0 TEXCON2 TEXCON2 Timer2 External Control Register 0x14 read-write n 0x0 0x0 RSTCAPSEL Timer External Reset Counter / Timer External Capture Mode Selection\n 4 1 read-write 0 Transition on TMx_EXT pin is using to save the TDR value into TCAP.(event capture function) #0 1 Transition on TMx_EXT pin is using to reset the 24-bit up counter.(event reset counter function) #1 TCDB Timer External Counter Input Pin De-Bounce Enable Control\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 7 1 read-write 0 TMx pin de-bounce Disabled #0 1 TMx pin de-bounce Enabled #1 TEXDB Timer External Capture Input Pin De-Bounce Enable Control\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit. 6 1 read-write 0 TMx_EXT pin de-bounce Disabled #0 1 TMx_EXT pin de-bounce Enabled #1 TEXEN Timer External Pin Function Enable Control\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n 3 1 read-write 0 RSTCAPSEL function of TMx_EXT pin will be ignored #0 1 RSTCAPSEL function of TMx_EXT pin is active #1 TEXIEN Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1. 5 1 read-write 0 TMx_EXT pin detection Interrupt Disabled #0 1 TMx_EXT pin detection Interrupt Enabled #1 TEX_EDGE Timer External Capture Pin Edge Detect Selection\n 1 2 read-write 0 A 1 to 0 transition on TMx_EXT pin will be detected #00 1 A 0 to 1 transition on TMx_EXT pin will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected #10 3 Reserved #11 TX_PHASE Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n 0 1 read-write 0 A falling edge of TMx_EXT pin will be counted #0 1 A rising edge of TMx_EXT pin will be counted #1 TEXCON3 TEXCON3 Timer3 External Control Register 0x34 read-write n 0x0 0x0 TEXISR2 TEXISR2 Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 TEXIF Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled, TMx_EXT pin selected as external capture function, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1]) setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 TMx_EXT pin interrupt did not occur #0 1 TMx_EXT pin interrupt occurred #1 TEXISR3 TEXISR3 Timer3 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TISR2 TISR2 Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 TDR value matches the TCMP value #1 TWF Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated #1 TISR3 TISR3 Timer3 Interrupt Status Register 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x3C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]). 17 1 read-only ADDR_MATCH Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Control (Available In UART0/UART1/UART2)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte.\nRX Buffer Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='1') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty.\nRX Buffer is not empty #0 1 RX FIFO is empty.\nRX Buffer is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full.\nRX buffer is not full #0 1 RX FIFO is full.\nRX bufferis full #1 RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 RX FIFO is not overflow.\nRX Buffer is not overflow #0 1 RX FIFO is overflow.\nRX Buffer is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full.\nTX Buffer is not full #0 1 TX FIFO is full.\nTX Buffer is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it. 24 1 read-only 0 TX FIFO is not overflow.\nTX Buffer is not overflow #0 1 TX FIFO is overflow.\nTX Buffer is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Control\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled. (Available in UART0/UART1/UART2) #01 2 IrDA function Enabled #10 3 RS-485 function Enabled. (Available in UART0/UART1) #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-Baud Rate Interrupt Enable Control\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 AUTO_CTS_EN CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 AUTO_RTS_EN RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_IEN LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-Out Counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOUT_IEN RX Time-Out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 WKCTSIEN NCTS Wake-Up Interrupt Enable Control\n 6 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal Control\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal #1 INV_TX IrDA Inverse Transmitting Output Signal Control\n 5 1 read-write 0 None inverse transmitting signal #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Control\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 LIN_IF LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 WKIF UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of "STOP Bit"\n 2 1 read-write 0 One " STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_LIN_CTL UA_LIN_CTL UART LIN Control Register 0x34 read-write n 0x0 0x0 BIT_ERR_EN Bit Error Detect Enable Control\n 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection Enabled #1 LINS_ARS_EN LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in section 6.11.5.8.4. (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 LINS_DUM_EN LIN Slave Divider Update Method Enable Control\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in section 6.11.5.8.4. (Slave mode with automatic resynchronization). 3 1 read-write 0 UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UA_BAUD is updated at the next received character. User must set the bit before checksum reception #1 LINS_EN LIN Slave Mode Enable Control\n 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 LINS_HDET_EN LIN Slave Header Detection Enable Control\n 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 LIN_BKDET_EN LIN Break Detection Enable Control\n 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 LIN_BKFL LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This break field length is LIN_BKFL + 1.\n 16 4 read-write LIN_BS_LEN LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1 bit time #00 2 The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time #10 3 The LIN break/sync delimiter length is 4 bit time #11 LIN_HEAD_SEL LIN Header Select\n 22 2 read-write 0 The LIN header includes "break field" #00 1 The LIN header includes "break field" and "sync field" #01 2 The LIN header includes "break field", "sync field" and "frame ID field" #10 3 Reserved #11 LIN_IDPEN LIN ID Parity Enable Control\n 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LIN_MUTE_EN LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 LIN_PID LIN PID Register\nIf the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write LIN_RX_DIS LIN Receiver Disable Control\n 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 LIN_SHD LIN TX Send Header Enable Control\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 UA_LIN_SR UA_LIN_SR UART LIN Status Register 0x38 read-write n 0x0 0x0 BIT_ERR_F Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n 9 1 read-only LINS_HDET_F LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not. 0 1 read-only 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 LINS_HERR_F LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".\n 1 1 read-only 0 LIN header error not detected #0 1 LIN header error detected #1 LINS_IDPERR_F LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n 2 1 read-only 0 No active #0 1 Receipted frame ID parity is not correct #1 LINS_SYNC_F LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 LIN_BKDET_F LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n 8 1 read-only 0 LIN break not detected #0 1 LIN break detected #1 UA_MCR UA_MCR UART Modem Control Register 0x10 read-write n 0x0 0x0 LEV_RTS RTS Pin Active Level ( Available In UART0/UART1 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 692 and Figure 693 for UART function mode.\nNote2: Refer to Figure 6103 and Figure 6104 for RS-485 function mode. 9 1 read-write 0 RTS pin output is high level active #0 1 RTS pin output is low level active #1 RTS RTS (Request-To-Send) Signal Control (Available In UART0/UART1 Channel)\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 RTS signal is active #0 1 RTS signal is inactive #1 RTS_ST RTS Pin State (Read Only) ( Available In UART0/UART1 Channel)\nThis bit mirror from RTS pin output of voltage logic status.\n 13 1 read-only 0 RTS pin output is low level voltage logic state #0 1 RTS pin output is high level voltage logic state #1 UA_MSR UA_MSR UART Modem Status Register 0x14 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read Only) \nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. 4 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 DCTSF Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 CTS input has not change state #0 1 CTS input has change state #1 LEV_CTS CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 691 for more information. 8 1 read-write 0 CTS pin input is high level active #0 1 CTS pin input is low level active #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin. 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator\n 0 8 read-write UART1 UART Register Map UART 0x0 0x0 0x3C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]). 17 1 read-only ADDR_MATCH Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Control (Available In UART0/UART1/UART2)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte.\nRX Buffer Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='1') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty.\nRX Buffer is not empty #0 1 RX FIFO is empty.\nRX Buffer is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full.\nRX buffer is not full #0 1 RX FIFO is full.\nRX bufferis full #1 RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 RX FIFO is not overflow.\nRX Buffer is not overflow #0 1 RX FIFO is overflow.\nRX Buffer is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full.\nTX Buffer is not full #0 1 TX FIFO is full.\nTX Buffer is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it. 24 1 read-only 0 TX FIFO is not overflow.\nTX Buffer is not overflow #0 1 TX FIFO is overflow.\nTX Buffer is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Control\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled. (Available in UART0/UART1/UART2) #01 2 IrDA function Enabled #10 3 RS-485 function Enabled. (Available in UART0/UART1) #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-Baud Rate Interrupt Enable Control\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 AUTO_CTS_EN CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 AUTO_RTS_EN RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_IEN LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-Out Counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOUT_IEN RX Time-Out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 WKCTSIEN NCTS Wake-Up Interrupt Enable Control\n 6 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal Control\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal #1 INV_TX IrDA Inverse Transmitting Output Signal Control\n 5 1 read-write 0 None inverse transmitting signal #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Control\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 LIN_IF LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 WKIF UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of "STOP Bit"\n 2 1 read-write 0 One " STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_LIN_CTL UA_LIN_CTL UART LIN Control Register 0x34 read-write n 0x0 0x0 BIT_ERR_EN Bit Error Detect Enable Control\n 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection Enabled #1 LINS_ARS_EN LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in section 6.11.5.8.4. (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 LINS_DUM_EN LIN Slave Divider Update Method Enable Control\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in section 6.11.5.8.4. (Slave mode with automatic resynchronization). 3 1 read-write 0 UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UA_BAUD is updated at the next received character. User must set the bit before checksum reception #1 LINS_EN LIN Slave Mode Enable Control\n 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 LINS_HDET_EN LIN Slave Header Detection Enable Control\n 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 LIN_BKDET_EN LIN Break Detection Enable Control\n 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 LIN_BKFL LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This break field length is LIN_BKFL + 1.\n 16 4 read-write LIN_BS_LEN LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1 bit time #00 2 The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time #10 3 The LIN break/sync delimiter length is 4 bit time #11 LIN_HEAD_SEL LIN Header Select\n 22 2 read-write 0 The LIN header includes "break field" #00 1 The LIN header includes "break field" and "sync field" #01 2 The LIN header includes "break field", "sync field" and "frame ID field" #10 3 Reserved #11 LIN_IDPEN LIN ID Parity Enable Control\n 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LIN_MUTE_EN LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 LIN_PID LIN PID Register\nIf the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write LIN_RX_DIS LIN Receiver Disable Control\n 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 LIN_SHD LIN TX Send Header Enable Control\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 UA_LIN_SR UA_LIN_SR UART LIN Status Register 0x38 read-write n 0x0 0x0 BIT_ERR_F Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n 9 1 read-only LINS_HDET_F LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not. 0 1 read-only 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 LINS_HERR_F LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".\n 1 1 read-only 0 LIN header error not detected #0 1 LIN header error detected #1 LINS_IDPERR_F LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n 2 1 read-only 0 No active #0 1 Receipted frame ID parity is not correct #1 LINS_SYNC_F LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 LIN_BKDET_F LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n 8 1 read-only 0 LIN break not detected #0 1 LIN break detected #1 UA_MCR UA_MCR UART Modem Control Register 0x10 read-write n 0x0 0x0 LEV_RTS RTS Pin Active Level ( Available In UART0/UART1 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 692 and Figure 693 for UART function mode.\nNote2: Refer to Figure 6103 and Figure 6104 for RS-485 function mode. 9 1 read-write 0 RTS pin output is high level active #0 1 RTS pin output is low level active #1 RTS RTS (Request-To-Send) Signal Control (Available In UART0/UART1 Channel)\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 RTS signal is active #0 1 RTS signal is inactive #1 RTS_ST RTS Pin State (Read Only) ( Available In UART0/UART1 Channel)\nThis bit mirror from RTS pin output of voltage logic status.\n 13 1 read-only 0 RTS pin output is low level voltage logic state #0 1 RTS pin output is high level voltage logic state #1 UA_MSR UA_MSR UART Modem Status Register 0x14 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read Only) \nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. 4 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 DCTSF Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 CTS input has not change state #0 1 CTS input has change state #1 LEV_CTS CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 691 for more information. 8 1 read-write 0 CTS pin input is high level active #0 1 CTS pin input is low level active #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin. 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator\n 0 8 read-write UART2 UART Register Map UART 0x0 0x0 0x10 registers n 0x18 0x24 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]). 17 1 read-only ADDR_MATCH Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Control (Available In UART0/UART1/UART2)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte.\nRX Buffer Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='1') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty.\nRX Buffer is not empty #0 1 RX FIFO is empty.\nRX Buffer is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full.\nRX buffer is not full #0 1 RX FIFO is full.\nRX bufferis full #1 RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 RX FIFO is not overflow.\nRX Buffer is not overflow #0 1 RX FIFO is overflow.\nRX Buffer is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full.\nTX Buffer is not full #0 1 TX FIFO is full.\nTX Buffer is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it. 24 1 read-only 0 TX FIFO is not overflow.\nTX Buffer is not overflow #0 1 TX FIFO is overflow.\nTX Buffer is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Control\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled. (Available in UART0/UART1/UART2) #01 2 IrDA function Enabled #10 3 RS-485 function Enabled. (Available in UART0/UART1) #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-Baud Rate Interrupt Enable Control\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 AUTO_CTS_EN CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 AUTO_RTS_EN RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_IEN LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-Out Counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOUT_IEN RX Time-Out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 WKCTSIEN NCTS Wake-Up Interrupt Enable Control\n 6 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal Control\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal #1 INV_TX IrDA Inverse Transmitting Output Signal Control\n 5 1 read-write 0 None inverse transmitting signal #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Control\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 LIN_IF LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 WKIF UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of "STOP Bit"\n 2 1 read-write 0 One " STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_LIN_CTL UA_LIN_CTL UART LIN Control Register 0x34 read-write n 0x0 0x0 BIT_ERR_EN Bit Error Detect Enable Control\n 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection Enabled #1 LINS_ARS_EN LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in section 6.11.5.8.4. (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 LINS_DUM_EN LIN Slave Divider Update Method Enable Control\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in section 6.11.5.8.4. (Slave mode with automatic resynchronization). 3 1 read-write 0 UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UA_BAUD is updated at the next received character. User must set the bit before checksum reception #1 LINS_EN LIN Slave Mode Enable Control\n 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 LINS_HDET_EN LIN Slave Header Detection Enable Control\n 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 LIN_BKDET_EN LIN Break Detection Enable Control\n 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 LIN_BKFL LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This break field length is LIN_BKFL + 1.\n 16 4 read-write LIN_BS_LEN LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1 bit time #00 2 The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time #10 3 The LIN break/sync delimiter length is 4 bit time #11 LIN_HEAD_SEL LIN Header Select\n 22 2 read-write 0 The LIN header includes "break field" #00 1 The LIN header includes "break field" and "sync field" #01 2 The LIN header includes "break field", "sync field" and "frame ID field" #10 3 Reserved #11 LIN_IDPEN LIN ID Parity Enable Control\n 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LIN_MUTE_EN LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 LIN_PID LIN PID Register\nIf the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write LIN_RX_DIS LIN Receiver Disable Control\n 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 LIN_SHD LIN TX Send Header Enable Control\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 UA_LIN_SR UA_LIN_SR UART LIN Status Register 0x38 read-write n 0x0 0x0 BIT_ERR_F Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n 9 1 read-only LINS_HDET_F LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not. 0 1 read-only 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 LINS_HERR_F LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".\n 1 1 read-only 0 LIN header error not detected #0 1 LIN header error detected #1 LINS_IDPERR_F LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n 2 1 read-only 0 No active #0 1 Receipted frame ID parity is not correct #1 LINS_SYNC_F LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 LIN_BKDET_F LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n 8 1 read-only 0 LIN break not detected #0 1 LIN break detected #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin. 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator\n 0 8 read-write UART3 UART Register Map UART 0x0 0x0 0x10 registers n 0x18 0x1C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]). 17 1 read-only ADDR_MATCH Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Control (Available In UART0/UART1/UART2)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte.\nRX Buffer Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='1') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty.\nRX Buffer is not empty #0 1 RX FIFO is empty.\nRX Buffer is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full.\nRX buffer is not full #0 1 RX FIFO is full.\nRX bufferis full #1 RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 RX FIFO is not overflow.\nRX Buffer is not overflow #0 1 RX FIFO is overflow.\nRX Buffer is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full.\nTX Buffer is not full #0 1 TX FIFO is full.\nTX Buffer is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it. 24 1 read-only 0 TX FIFO is not overflow.\nTX Buffer is not overflow #0 1 TX FIFO is overflow.\nTX Buffer is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Control\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled. (Available in UART0/UART1/UART2) #01 2 IrDA function Enabled #10 3 RS-485 function Enabled. (Available in UART0/UART1) #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-Baud Rate Interrupt Enable Control\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 AUTO_CTS_EN CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 AUTO_RTS_EN RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_IEN LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-Out Counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOUT_IEN RX Time-Out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 WKCTSIEN NCTS Wake-Up Interrupt Enable Control\n 6 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal Control\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal #1 INV_TX IrDA Inverse Transmitting Output Signal Control\n 5 1 read-write 0 None inverse transmitting signal #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Control\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 LIN_IF LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 WKIF UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of "STOP Bit"\n 2 1 read-write 0 One " STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin. 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator\n 0 8 read-write UART4 UART Register Map UART 0x0 0x0 0x10 registers n 0x18 0x1C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]). 17 1 read-only ADDR_MATCH Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Control (Available In UART0/UART1/UART2)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte.\nRX Buffer Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='1') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty.\nRX Buffer is not empty #0 1 RX FIFO is empty.\nRX Buffer is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full.\nRX buffer is not full #0 1 RX FIFO is full.\nRX bufferis full #1 RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 RX FIFO is not overflow.\nRX Buffer is not overflow #0 1 RX FIFO is overflow.\nRX Buffer is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full.\nTX Buffer is not full #0 1 TX FIFO is full.\nTX Buffer is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it. 24 1 read-only 0 TX FIFO is not overflow.\nTX Buffer is not overflow #0 1 TX FIFO is overflow.\nTX Buffer is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Control\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled. (Available in UART0/UART1/UART2) #01 2 IrDA function Enabled #10 3 RS-485 function Enabled. (Available in UART0/UART1) #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-Baud Rate Interrupt Enable Control\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 AUTO_CTS_EN CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 AUTO_RTS_EN RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_IEN LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-Out Counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOUT_IEN RX Time-Out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 WKCTSIEN NCTS Wake-Up Interrupt Enable Control\n 6 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal Control\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal #1 INV_TX IrDA Inverse Transmitting Output Signal Control\n 5 1 read-write 0 None inverse transmitting signal #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Control\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 LIN_IF LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 WKIF UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of "STOP Bit"\n 2 1 read-write 0 One " STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin. 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator\n 0 8 read-write UART5 UART Register Map UART 0x0 0x0 0x10 registers n 0x18 0x1C registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]). 17 1 read-only ADDR_MATCH Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_BKFL UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n 0 4 read-write LIN_RX_EN LIN RX Enable Control (Available In UART0/UART1/UART2)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation mode (AUO) Disabled #0 1 RS-485 Auto Direction Operation mode (AUO) Enabled #1 RS485_NMM RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte.\nRX Buffer Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='1') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty.\nRX Buffer is not empty #0 1 RX FIFO is empty.\nRX Buffer is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full.\nRX buffer is not full #0 1 RX FIFO is full.\nRX bufferis full #1 RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it. 0 1 read-only 0 RX FIFO is not overflow.\nRX Buffer is not overflow #0 1 RX FIFO is overflow.\nRX Buffer is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty.\nTX Buffer is not empty #0 1 TX FIFO is empty.\nTX Buffer is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full.\nTX Buffer is not full #0 1 TX FIFO is full.\nTX Buffer is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it. 24 1 read-only 0 TX FIFO is not overflow.\nTX Buffer is not overflow #0 1 TX FIFO is overflow.\nTX Buffer is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select Enable Control\n 0 2 read-write 0 UART function Enabled #00 1 LIN function Enabled. (Available in UART0/UART1/UART2) #01 2 IrDA function Enabled #10 3 RS-485 function Enabled. (Available in UART0/UART1) #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-Baud Rate Interrupt Enable Control\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 AUTO_CTS_EN CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 AUTO_RTS_EN RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal. 12 1 read-write 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_IEN LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode. 8 1 read-write 0 Lin bus interrupt Disabled #0 1 Lin bus interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-Out Counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOUT_IEN RX Time-Out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 WKCTSIEN NCTS Wake-Up Interrupt Enable Control\n 6 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write n 0x0 0x0 INV_RX IrDA Inverse Receive Input Signal Control\n 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal #1 INV_TX IrDA Inverse Transmitting Output Signal Control\n 5 1 read-write 0 None inverse transmitting signal #0 1 Inverse transmitting output signal #1 TX_SELECT IrDA Receiver/Transmitter Selection Enable Control\n 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared. 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 LIN_IF LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared. 7 1 read-only 0 None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #0 1 At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated #1 LIN_INT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 WKIF UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number Of "STOP Bit"\n 2 1 read-write 0 One " STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin. 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-Out Interrupt Comparator\n 0 8 read-write WDT WDT Register Map WDT 0x0 0x0 0x8 registers n WTCR WTCR Watchdog Timer Control Register 0x0 read-write n 0x0 0x0 DBGACK_WDT ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 WTE Watchdog Timer Enable Control (Write Protect)\nNote: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 WDT Disabled. (This action will reset the internal up counter value.) #0 1 WDT Enabled #1 WTIE Watchdog Timer Time-Out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.\n 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 WTIF Watchdog Timer Time-Out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 WTIS Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\n 8 3 read-write 0 24 *TWDT #000 1 26 * TWDT #001 2 28 * TWDT #010 3 210 * TWDT #011 4 212 * TWDT #100 5 214 * TWDT #101 6 216 * TWDT #110 7 218 * TWDT #111 WTR Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 WTRE Watchdog Timer Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\n 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 WTRF Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 WTWKE Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WTWKF Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 WTCRALT WTCRALT Watchdog Timer Alternative Control Register 0x4 read-write n 0x0 0x0 WTRDSEL Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. User can select a suitable value of WDT Reset Delay Period for different WDT time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nNote: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 Watchdog Timer Reset Delay Period is 1026 * WDT_CLK #00 1 Watchdog Timer Reset Delay Period is 130 * WDT_CLK #01 2 Watchdog Timer Reset Delay Period is 18 * WDT_CLK #10 3 Watchdog Timer Reset Delay Period is 3 * WDT_CLK #11 WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n WWDTCR WWDTCR Window Watchdog Timer Control Register 0x4 read-write n 0x0 0x0 DBGACK_WWDT ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 PERIODSEL WWDT Counter Prescale Period Selection\n 8 4 read-write 0 Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT #0000 1 Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT #0001 2 Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT #0010 3 Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT #0011 4 Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT #0100 5 Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT #0101 6 Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT #0110 7 Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT #0111 8 Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT #1000 9 Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT #1001 10 Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT #1010 11 Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT #1011 12 Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT #1100 13 Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT #1101 14 Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT #1110 15 Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT #1111 WINCMP WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately. 16 6 read-write WWDTEN WWDT Enable Control\nSet this bit to enable WWDT counter counting.\n 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter is starting counting #1 WWDTIE WWDT Interrupt Enable Control\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 WWDTCVR WWDTCVR Window Watchdog Timer Counter Value Register 0xC read-only n 0x0 0x0 WWDTCVAL WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value. 0 6 read-only WWDTRLD WWDTRLD Window Watchdog Timer Reload Counter Register 0x0 write-only n 0x0 0x0 WWDTRLD WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value is larger than WINCMP, WWDT reset signal will generate immediately. 0 32 write-only WWDTSR WWDTSR Window Watchdog Timer Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches WINCMP value #1 WWDTRF WWDT Time-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1