nuvoTon
NUC200AE_v1
2024.04.28
NUC200AE_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0xC
registers
n
CMPCR0
CMPCR0
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
CMPCN
Comparator Negative Input Selection\n
4
1
read-write
0
The source of the negative comparator input is from ACMPn_N pin (n = 0, 1)
#0
1
Internal band-gap reference voltage is selected as the source of negative comparator input
#1
CMPEN
Comparator Enable Bit\n
0
1
read-write
0
Comparator Disabled
#0
1
Comparator Enabled
#1
CMPIE
Comparator Interrupt Enable Bit\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CMPINV
Comparator Output Inverse Enable Bit\n
6
1
read-write
0
Comparator analog output inverse is Disabled
#0
1
Comparator analog output inverse is Enabled
#1
CMP_HYSEN
Comparator Hysteresis Enable Bit\n
2
1
read-write
0
Hysteresis function Disabled (Default)
#0
1
Hysteresis function Enabled
#1
CMPCR1
CMPCR1
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
CMPSR
CMPSR
Analog Comparator Status Register
0x8
read-write
n
0x0
0x0
CMPF0
Comparator 0 Interrupt Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if CMPCR0[1] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
CMPF1
Comparator 1 Interrupt Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if CMPCR1[1] is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
CO0
Comparator 0 Output\n
2
1
read-write
CO1
Comparator 1 Output\n
3
1
read-write
ADC
ADC Register Map
ADC
0x0
0x0
0x30
registers
n
0x40
0x4
registers
n
ADCHER
ADCHER
ADC Channel Enable Register
0x24
read-write
n
0x0
0x0
CHEN
Analog Input Channel Enable Bit\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled.\n
0
8
read-write
0
ADC input channel Disabled
0
1
ADC input channel Enabled
1
PRESEL
Analog Input Channel 7 Selection\n
8
2
read-write
0
External analog input
#00
1
Internal band-gap voltage
#01
2
Internal temperature sensor
#10
3
Reserved
#11
ADCMPR0
ADCMPR0
ADC Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection\n
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Channel 4 conversion result is selected to be compared
#100
5
Channel 5 conversion result is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8])+1), the CMPF0/1 bit (ADSR[1]/[2]) will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit (ADCR[31]) is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit (ADCR[31]) is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
16
12
read-write
CMPEN
Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]), CMPF0/1 bit (ADSR[1]/[2]) will be asserted, in the meanwhile, if CMPIE (ADCMPR0/1[1]) is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]), the internal match counter will increase 1, The comparing data must successively matched with the compare condition. Once any comparing data does not match during the comparing, the internal counter will clear to 0. When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) +1), the CMPF0/1 bit (ADSR[1]/[2]) will be set.
8
4
read-write
ADCMPR1
ADCMPR1
ADC Compare Register 1
0x2C
read-write
n
0x0
0x0
ADCR
ADCR
ADC Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable Bit\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADIE
A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADMD
A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit (ADCR[11]) firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
ADST
A/D Conversion Start\nADST bit can be set to 1 from three sources: software, PWM Center-aligned trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
11
1
read-write
0
Conversion stops and A/D converter enter idle state
#0
1
Conversion starts
#1
DIFFEN
Differential Input Mode Control\n
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
A/D Differential Input Mode Output Format\n
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format
#0
1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format
#1
PTEN
PDMA Transfer Enable Bit\n
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADDR 0~7 Enabled
#1
TRGCOND
External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
Hardware Trigger Enable Bit\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode, the ADST bit (ADCR[11]) can be set to 1 by the selected hardware trigger source.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGS
Hardware Trigger Source\nSoftware should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
3
A/D conversion is started by PWM Center-aligned trigger
#11
ADDR0
ADDR0
ADC Data Register 0
0x0
read-only
n
0x0
0x0
OVERRUN
Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit.
16
1
read-only
0
Data in RSLT (ADDRx[15:0], x=0~7) is recent conversion result
#0
1
Data in RSLT (ADDRx[15:0], x=0~7) is overwritten
#1
RSLT
A/D Conversion Result\nThis field contains conversion result of ADC.\n
0
16
read-only
VALID
Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit
17
1
read-only
0
Data in RSLT bits (ADDRx[15:0], x=0~7) is not valid
#0
1
Data in RSLT bits (ADDRx[15:0], x=0~7) is valid
#1
ADDR1
ADDR1
ADC Data Register 1
0x4
read-write
n
0x0
0x0
ADDR2
ADDR2
ADC Data Register 2
0x8
read-write
n
0x0
0x0
ADDR3
ADDR3
ADC Data Register 3
0xC
read-write
n
0x0
0x0
ADDR4
ADDR4
ADC Data Register 4
0x10
read-write
n
0x0
0x0
ADDR5
ADDR5
ADC Data Register 5
0x14
read-write
n
0x0
0x0
ADDR6
ADDR6
ADC Data Register 6
0x18
read-write
n
0x0
0x0
ADDR7
ADDR7
ADC Data Register 7
0x1C
read-write
n
0x0
0x0
ADPDMA
ADPDMA
ADC PDMA Current Transfer Data Register
0x40
read-only
n
0x0
0x0
AD_PDMA
ADC PDMA Current Transfer Data Register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data is the content of ADDR0 ~ ADDR7.\nThis is a read only register.
0
18
read-only
ADSR
ADSR
ADC Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself.
0
1
read-write
BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit (ADCR[11]).\nIt is read only.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel\nIt is read only.
4
3
read-write
CMPF0
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n
1
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0 setting
#1
CMPF1
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n
2
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
OVERRUN
Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR0~7[16]).\nIt is read only.
16
8
read-write
VALID
Data Valid Flag\nIt is a mirror of VALID bit (ADDR0~7[17]).\nIt is read only.
8
8
read-write
CAN0
CAN Register Map
CAN
0x0
0x0
0x1C
registers
n
0x100
0x8
registers
n
0x120
0x8
registers
n
0x140
0x8
registers
n
0x160
0x10
registers
n
0x20
0x2C
registers
n
0x80
0x2C
registers
n
CAN_BRPE
CAN_BRPE
Baud Rate Prescaler Extension Register
0x18
read-write
n
0x0
0x0
BRPE
BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
0
4
read-write
CAN_BTIME
CAN_BTIME
Bit Timing Register
0xC
read-write
n
0x0
0x0
BRP
Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
0
6
read-write
SJW
(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
6
2
read-write
TSeg1
Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
8
4
read-write
TSeg2
Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
12
3
read-write
CAN_CON
CAN_CON
Control Register
0x0
read-write
n
0x0
0x0
CCE
Configuration Change Enable Bit\n
6
1
read-write
0
No write access to the Bit Timing Register
#0
1
Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1)
#1
DAR
Automatic Re-Transmission Disable Bit\n
5
1
read-write
0
Automatic Retransmission of disturbed messages enabled
#0
1
Automatic Retransmission disabled
#1
EIE
Error Interrupt Enable Bit\n
3
1
read-write
0
Disabled - No Error Status Interrupt will be generated
#0
1
Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt
#1
IE
Module Interrupt Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
Init
Init Initialization\n
0
1
read-write
0
Normal Operation
#0
1
Initialization is started
#1
SIE
Status Change Interrupt Enable Bit\n
2
1
read-write
0
Disabled - No Status Change Interrupt will be generated
#0
1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
#1
Test
Test Mode Enable Bit\n
7
1
read-write
0
Normal Operation
#0
1
Test Mode
#1
CAN_ERR
CAN_ERR
Error Counter Register
0x8
read-only
n
0x0
0x0
REC
Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
8
7
read-only
RP
Receive Error Passive\n
15
1
read-only
0
The Receive Error Counter is below the error passive level
#0
1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
#1
TEC
Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
0
8
read-only
CAN_IF1_ARB1
CAN_IF1_ARB1
IFn Arbitration 1 Register
0x30
read-write
n
0x0
0x0
ID
Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame")
0
16
read-write
CAN_IF1_ARB2
CAN_IF1_ARB2
IFn Arbitration 2 Register
0x34
read-write
n
0x0
0x0
Dir
Message Direction\n
13
1
read-write
0
Direction is receive
#0
1
Direction is transmit
#1
ID
Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame")
0
13
read-write
MsgVal
Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
15
1
read-write
0
The Message Object is ignored by the Message Handler
#0
1
The Message Object is configured and should be considered by the Message Handler
#1
Xtd
Extended Identifier\n
14
1
read-write
0
The 11-bit ("standard") Identifier will be used for this Message Object
#0
1
The 29-bit ("extended") Identifier will be used for this Message Object
#1
CAN_IF1_CMASK
CAN_IF1_CMASK
IFn Command Mask Register
0x24
read-write
n
0x0
0x0
Arb
Access Arbitration Bits\nWrite Operation:\n
5
1
read-write
0
Arbitration bits unchanged
#0
1
Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
#1
ClrIntPnd
Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation:\n
3
1
read-write
0
IntPnd bit (CAN_IFn_MCON[13]) remains unchanged
#0
1
Clear IntPnd bit in the Message Object
#1
Control
Control Access Control Bits\nWrite Operation:\n
4
1
read-write
0
Control Bits unchanged
#0
1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
#1
DAT_A
Access Data Bytes [3:0]\nWrite Operation:\n
1
1
read-write
0
Data Bytes [3:0] unchanged
#0
1
Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
#1
DAT_B
Access Data Bytes [7:4]\nWrite Operation: \n
0
1
read-write
0
Data Bytes [7:4] unchanged
#0
1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
#1
Mask
Access Mask Bits\nWrite Operation:\n
6
1
read-write
0
Mask bits unchanged
#0
1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
#1
TxRqst_NewDat
Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
2
1
read-write
0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#0
1
Set TxRqst bit.\nClear NewDat bit in the Message Object
#1
WR_RD
Write / Read Mode\n
7
1
read-write
0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#0
1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
#1
CAN_IF1_CREQ
CAN_IF1_CREQ
IFn (Register Map Note 2) Command Request Registers
0x20
read-write
n
0x0
0x0
Busy
Busy Flag\n
15
1
read-write
0
Read/write action has finished
#0
1
Writing to the IFn Command Request Register is in progress. This bit can only be read by the software
#1
MessageNumber
Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
0
6
read-write
CAN_IF1_DAT_A1
CAN_IF1_DAT_A1
IFn Data A1 Register (Register Map Note 3)
0x3C
read-write
n
0x0
0x0
Data0
Data Byte 0\n1st data byte of a CAN Data Frame
0
8
read-write
Data1
Data Byte 1\n2nd data byte of a CAN Data Frame
8
8
read-write
CAN_IF1_DAT_A2
CAN_IF1_DAT_A2
IFn Data A2 Register (Register Map Note 3)
0x40
read-write
n
0x0
0x0
Data2
Data Byte 2\n3rd data byte of CAN Data Frame
0
8
read-write
Data3
Data Byte 3\n4th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B1
CAN_IF1_DAT_B1
IFn Data B1 Register (Register Map Note 3)
0x44
read-write
n
0x0
0x0
Data4
Data Byte 4\n5th data byte of CAN Data Frame
0
8
read-write
Data5
Data Byte 5\n6th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B2
CAN_IF1_DAT_B2
IFn Data B2 Register (Register Map Note 3)
0x48
read-write
n
0x0
0x0
Data6
Data Byte 6\n7th data byte of CAN Data Frame.
0
8
read-write
Data7
Data Byte 7\n8th data byte of CAN Data Frame.
8
8
read-write
CAN_IF1_MASK1
CAN_IF1_MASK1
IFn Mask 1 Register
0x28
read-write
n
0x0
0x0
Msk
Identifier Mask 15-0\n
0
16
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
CAN_IF1_MASK2
CAN_IF1_MASK2
IFn Mask 2 Register
0x2C
read-write
n
0x0
0x0
MDir
Mask Message Direction\n
14
1
read-write
0
The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering
#0
1
The message direction bit (Dir) is used for acceptance filtering
#1
Msk
Identifier Mask 28-16\n
0
13
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
MXtd
Mask Extended Identifier\nNote: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
15
1
read-write
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#0
1
The extended identifier bit (IDE) is used for acceptance filtering
#1
CAN_IF1_MCON
CAN_IF1_MCON
IFn Message Control Register
0x38
read-write
n
0x0
0x0
DLC
Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData 0: 1st data byte of a CAN Data Frame\nData 1: 2nd data byte of a CAN Data Frame\nData 2: 3rd data byte of a CAN Data Frame\nData 3: 4th data byte of a CAN Data Frame\nData 4: 5th data byte of a CAN Data Frame\nData 5: 6th data byte of a CAN Data Frame\nData 6: 7th data byte of a CAN Data Frame\nData 7 : 8th data byte of a CAN Data Frame\nNote: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. I f the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
0
4
read-write
EoB
End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
7
1
read-write
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#0
1
Single Message Object or last Message Object of a FIFO Buffer
#1
IntPnd
Interrupt Pending\n
13
1
read-write
0
This message object is not the source of an interrupt
#0
1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
#1
MsgLst
None
14
1
read-write
0
No message lost since last time this bit was reset by the CPU
#0
1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
#1
NewDat
New Data\n
15
1
read-write
0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
#1
RmtEn
Remote Enable Bit\n
9
1
read-write
0
At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged
#0
1
At the reception of a Remote Frame, TxRqst is set
#1
RxIE
Receive Interrupt Enable Bit\n
10
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame
#0
1
IntPnd will be set after a successful reception of a frame
#1
TxIE
Transmit Interrupt Enable Bit\n
11
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame
#0
1
IntPnd will be set after a successful transmission of a frame
#1
TxRqst
Transmit Request\n
8
1
read-write
0
This Message Object is not waiting for transmission
#0
1
The transmission of this Message Object is requested and is not yet done
#1
UMask
Use Acceptance Mask\nNote: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
12
1
read-write
0
Mask ignored
#0
1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
#1
CAN_IF2_ARB1
CAN_IF2_ARB1
IFn Arbitration 1 Register
0x90
read-write
n
0x0
0x0
CAN_IF2_ARB2
CAN_IF2_ARB2
IFn Arbitration 2 Register
0x94
read-write
n
0x0
0x0
CAN_IF2_CMASK
CAN_IF2_CMASK
IFn Command Mask Register
0x84
read-write
n
0x0
0x0
CAN_IF2_CREQ
CAN_IF2_CREQ
IFn (Register Map Note 2) Command Request Registers
0x80
read-write
n
0x0
0x0
CAN_IF2_DAT_A1
CAN_IF2_DAT_A1
IFn Data A1 Register (Register Map Note 3)
0x9C
read-write
n
0x0
0x0
CAN_IF2_DAT_A2
CAN_IF2_DAT_A2
IFn Data A2 Register (Register Map Note 3)
0xA0
read-write
n
0x0
0x0
CAN_IF2_DAT_B1
CAN_IF2_DAT_B1
IFn Data B1 Register (Register Map Note 3)
0xA4
read-write
n
0x0
0x0
CAN_IF2_DAT_B2
CAN_IF2_DAT_B2
IFn Data B2 Register (Register Map Note 3)
0xA8
read-write
n
0x0
0x0
CAN_IF2_MASK1
CAN_IF2_MASK1
IFn Mask 1 Register
0x88
read-write
n
0x0
0x0
CAN_IF2_MASK2
CAN_IF2_MASK2
IFn Mask 2 Register
0x8C
read-write
n
0x0
0x0
CAN_IF2_MCON
CAN_IF2_MCON
IFn Message Control Register
0x98
read-write
n
0x0
0x0
CAN_IIDR
CAN_IIDR
Interrupt Identifier Register
0x10
read-only
n
0x0
0x0
IntId
Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). The Status Interrupt is cleared by reading the Status Register.
0
16
read-only
CAN_IPND1
CAN_IPND1
Interrupt Pending Register 1
0x140
read-only
n
0x0
0x0
IntPnd16_1
Interrupt Pending Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_IPND2
CAN_IPND2
Interrupt Pending Register 2
0x144
read-only
n
0x0
0x0
IntPnd32_17
Interrupt Pending Bits 32-17(Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_MVLD1
CAN_MVLD1
Message Valid Register 1
0x160
read-only
n
0x0
0x0
MsgVal16_1
Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_MVLD2
CAN_MVLD2
Message Valid Register 2
0x164
read-only
n
0x0
0x0
MsgVal32_17
Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_NDAT1
CAN_NDAT1
New Data Register 1
0x120
read-only
n
0x0
0x0
NewData16_1
New Data Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_NDAT2
CAN_NDAT2
New Data Register 2
0x124
read-only
n
0x0
0x0
NewData32_17
New Data Bits 32-17 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_STATUS
CAN_STATUS
Status Register
0x4
read-write
n
0x0
0x0
BOff
Bus-Off Status (Read Only) \n
7
1
read-only
0
The CAN module is not in bus-off state
#0
1
The CAN module is in bus-off state
#1
EPass
Error Passive (Read Only)\n
5
1
read-only
0
The CAN Core is error active
#0
1
The CAN Core is in the error passive state as defined in the CAN Specification
#1
EWarn
Error Warning Status (Read Only)\n
6
1
read-only
0
Both error counters are below the error warning limit of 96
#0
1
At least one of the error counters in the EML has reached the error warning limit of 96
#1
LEC
Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. The following table describes the error code.
0
3
read-write
RxOK
Received A Message Successfully\n
4
1
read-write
0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#0
1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
#1
TxOK
Transmitted A Message Successfully\n
3
1
read-write
0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#0
1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
#1
CAN_TEST
CAN_TEST
Test Register (Register Map Note 1)
0x14
read-write
n
0x0
0x0
Basic
Basic Mode\n
2
1
read-write
0
Basic Mode disabled
#0
1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
#1
LBack
Loop Back Mode Enable Bit\n
4
1
read-write
0
Loop Back Mode is disabled
#0
1
Loop Back Mode is enabled
#1
Res
Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
0
2
read-write
Rx
Monitors The Actual Value Of CAN_RX Pin (Read Only) \n
7
1
read-only
0
The CAN bus is dominant (CAN_RX = '0')
#0
1
The CAN bus is recessive (CAN_RX = '1')
#1
Silent
Silent Mode\n
3
1
read-write
0
Normal operation
#0
1
The module is in Silent Mode
#1
Tx
Tx[1:0]: Control Of CAN_TX Pin\n
5
2
read-write
0
Reset value, CAN_TX pin is controlled by the CAN Core
#00
1
Sample Point can be monitored at CAN_TX pin
#01
2
CAN_TX pin drives a dominant ('0') value
#10
3
CAN_TX pin drives a recessive ('1') value
#11
CAN_TXREQ1
CAN_TXREQ1
Transmission Request Register 1
0x100
read-only
n
0x0
0x0
TxRqst16_1
Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_TXREQ2
CAN_TXREQ2
Transmission Request Register 2
0x104
read-only
n
0x0
0x0
TxRqst32_17
Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_WU_EN
CAN_WU_EN
Wake-up Enable Register
0x168
read-write
n
0x0
0x0
WAKUP_EN
Wake-Up Enable Bit\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin..
0
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
CAN_WU_STATUS
CAN_WU_STATUS
Wake-up Status Register
0x16C
read-write
n
0x0
0x0
WAKUP_STS
Wake-Up Status \nNote: This bit can be cleared by writing '0'.
0
1
read-write
0
No wake-up event occurred
#0
1
Wake-up event occurred
#1
CAN1
CAN Register Map
CAN
0x0
0x0
0x1C
registers
n
0x100
0x8
registers
n
0x120
0x8
registers
n
0x140
0x8
registers
n
0x160
0x10
registers
n
0x20
0x2C
registers
n
0x80
0x2C
registers
n
CAN_BRPE
CAN_BRPE
Baud Rate Prescaler Extension Register
0x18
read-write
n
0x0
0x0
BRPE
BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
0
4
read-write
CAN_BTIME
CAN_BTIME
Bit Timing Register
0xC
read-write
n
0x0
0x0
BRP
Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
0
6
read-write
SJW
(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
6
2
read-write
TSeg1
Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
8
4
read-write
TSeg2
Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
12
3
read-write
CAN_CON
CAN_CON
Control Register
0x0
read-write
n
0x0
0x0
CCE
Configuration Change Enable Bit\n
6
1
read-write
0
No write access to the Bit Timing Register
#0
1
Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1)
#1
DAR
Automatic Re-Transmission Disable Bit\n
5
1
read-write
0
Automatic Retransmission of disturbed messages enabled
#0
1
Automatic Retransmission disabled
#1
EIE
Error Interrupt Enable Bit\n
3
1
read-write
0
Disabled - No Error Status Interrupt will be generated
#0
1
Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt
#1
IE
Module Interrupt Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
Init
Init Initialization\n
0
1
read-write
0
Normal Operation
#0
1
Initialization is started
#1
SIE
Status Change Interrupt Enable Bit\n
2
1
read-write
0
Disabled - No Status Change Interrupt will be generated
#0
1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
#1
Test
Test Mode Enable Bit\n
7
1
read-write
0
Normal Operation
#0
1
Test Mode
#1
CAN_ERR
CAN_ERR
Error Counter Register
0x8
read-only
n
0x0
0x0
REC
Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
8
7
read-only
RP
Receive Error Passive\n
15
1
read-only
0
The Receive Error Counter is below the error passive level
#0
1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
#1
TEC
Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
0
8
read-only
CAN_IF1_ARB1
CAN_IF1_ARB1
IFn Arbitration 1 Register
0x30
read-write
n
0x0
0x0
ID
Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame")
0
16
read-write
CAN_IF1_ARB2
CAN_IF1_ARB2
IFn Arbitration 2 Register
0x34
read-write
n
0x0
0x0
Dir
Message Direction\n
13
1
read-write
0
Direction is receive
#0
1
Direction is transmit
#1
ID
Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame")
0
13
read-write
MsgVal
Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
15
1
read-write
0
The Message Object is ignored by the Message Handler
#0
1
The Message Object is configured and should be considered by the Message Handler
#1
Xtd
Extended Identifier\n
14
1
read-write
0
The 11-bit ("standard") Identifier will be used for this Message Object
#0
1
The 29-bit ("extended") Identifier will be used for this Message Object
#1
CAN_IF1_CMASK
CAN_IF1_CMASK
IFn Command Mask Register
0x24
read-write
n
0x0
0x0
Arb
Access Arbitration Bits\nWrite Operation:\n
5
1
read-write
0
Arbitration bits unchanged
#0
1
Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
#1
ClrIntPnd
Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation:\n
3
1
read-write
0
IntPnd bit (CAN_IFn_MCON[13]) remains unchanged
#0
1
Clear IntPnd bit in the Message Object
#1
Control
Control Access Control Bits\nWrite Operation:\n
4
1
read-write
0
Control Bits unchanged
#0
1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
#1
DAT_A
Access Data Bytes [3:0]\nWrite Operation:\n
1
1
read-write
0
Data Bytes [3:0] unchanged
#0
1
Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
#1
DAT_B
Access Data Bytes [7:4]\nWrite Operation: \n
0
1
read-write
0
Data Bytes [7:4] unchanged
#0
1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
#1
Mask
Access Mask Bits\nWrite Operation:\n
6
1
read-write
0
Mask bits unchanged
#0
1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
#1
TxRqst_NewDat
Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
2
1
read-write
0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#0
1
Set TxRqst bit.\nClear NewDat bit in the Message Object
#1
WR_RD
Write / Read Mode\n
7
1
read-write
0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#0
1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
#1
CAN_IF1_CREQ
CAN_IF1_CREQ
IFn (Register Map Note 2) Command Request Registers
0x20
read-write
n
0x0
0x0
Busy
Busy Flag\n
15
1
read-write
0
Read/write action has finished
#0
1
Writing to the IFn Command Request Register is in progress. This bit can only be read by the software
#1
MessageNumber
Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
0
6
read-write
CAN_IF1_DAT_A1
CAN_IF1_DAT_A1
IFn Data A1 Register (Register Map Note 3)
0x3C
read-write
n
0x0
0x0
Data0
Data Byte 0\n1st data byte of a CAN Data Frame
0
8
read-write
Data1
Data Byte 1\n2nd data byte of a CAN Data Frame
8
8
read-write
CAN_IF1_DAT_A2
CAN_IF1_DAT_A2
IFn Data A2 Register (Register Map Note 3)
0x40
read-write
n
0x0
0x0
Data2
Data Byte 2\n3rd data byte of CAN Data Frame
0
8
read-write
Data3
Data Byte 3\n4th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B1
CAN_IF1_DAT_B1
IFn Data B1 Register (Register Map Note 3)
0x44
read-write
n
0x0
0x0
Data4
Data Byte 4\n5th data byte of CAN Data Frame
0
8
read-write
Data5
Data Byte 5\n6th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B2
CAN_IF1_DAT_B2
IFn Data B2 Register (Register Map Note 3)
0x48
read-write
n
0x0
0x0
Data6
Data Byte 6\n7th data byte of CAN Data Frame.
0
8
read-write
Data7
Data Byte 7\n8th data byte of CAN Data Frame.
8
8
read-write
CAN_IF1_MASK1
CAN_IF1_MASK1
IFn Mask 1 Register
0x28
read-write
n
0x0
0x0
Msk
Identifier Mask 15-0\n
0
16
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
CAN_IF1_MASK2
CAN_IF1_MASK2
IFn Mask 2 Register
0x2C
read-write
n
0x0
0x0
MDir
Mask Message Direction\n
14
1
read-write
0
The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering
#0
1
The message direction bit (Dir) is used for acceptance filtering
#1
Msk
Identifier Mask 28-16\n
0
13
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
MXtd
Mask Extended Identifier\nNote: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
15
1
read-write
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#0
1
The extended identifier bit (IDE) is used for acceptance filtering
#1
CAN_IF1_MCON
CAN_IF1_MCON
IFn Message Control Register
0x38
read-write
n
0x0
0x0
DLC
Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData 0: 1st data byte of a CAN Data Frame\nData 1: 2nd data byte of a CAN Data Frame\nData 2: 3rd data byte of a CAN Data Frame\nData 3: 4th data byte of a CAN Data Frame\nData 4: 5th data byte of a CAN Data Frame\nData 5: 6th data byte of a CAN Data Frame\nData 6: 7th data byte of a CAN Data Frame\nData 7 : 8th data byte of a CAN Data Frame\nNote: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. I f the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
0
4
read-write
EoB
End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
7
1
read-write
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#0
1
Single Message Object or last Message Object of a FIFO Buffer
#1
IntPnd
Interrupt Pending\n
13
1
read-write
0
This message object is not the source of an interrupt
#0
1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
#1
MsgLst
None
14
1
read-write
0
No message lost since last time this bit was reset by the CPU
#0
1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
#1
NewDat
New Data\n
15
1
read-write
0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
#1
RmtEn
Remote Enable Bit\n
9
1
read-write
0
At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged
#0
1
At the reception of a Remote Frame, TxRqst is set
#1
RxIE
Receive Interrupt Enable Bit\n
10
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame
#0
1
IntPnd will be set after a successful reception of a frame
#1
TxIE
Transmit Interrupt Enable Bit\n
11
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame
#0
1
IntPnd will be set after a successful transmission of a frame
#1
TxRqst
Transmit Request\n
8
1
read-write
0
This Message Object is not waiting for transmission
#0
1
The transmission of this Message Object is requested and is not yet done
#1
UMask
Use Acceptance Mask\nNote: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
12
1
read-write
0
Mask ignored
#0
1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
#1
CAN_IF2_ARB1
CAN_IF2_ARB1
IFn Arbitration 1 Register
0x90
read-write
n
0x0
0x0
CAN_IF2_ARB2
CAN_IF2_ARB2
IFn Arbitration 2 Register
0x94
read-write
n
0x0
0x0
CAN_IF2_CMASK
CAN_IF2_CMASK
IFn Command Mask Register
0x84
read-write
n
0x0
0x0
CAN_IF2_CREQ
CAN_IF2_CREQ
IFn (Register Map Note 2) Command Request Registers
0x80
read-write
n
0x0
0x0
CAN_IF2_DAT_A1
CAN_IF2_DAT_A1
IFn Data A1 Register (Register Map Note 3)
0x9C
read-write
n
0x0
0x0
CAN_IF2_DAT_A2
CAN_IF2_DAT_A2
IFn Data A2 Register (Register Map Note 3)
0xA0
read-write
n
0x0
0x0
CAN_IF2_DAT_B1
CAN_IF2_DAT_B1
IFn Data B1 Register (Register Map Note 3)
0xA4
read-write
n
0x0
0x0
CAN_IF2_DAT_B2
CAN_IF2_DAT_B2
IFn Data B2 Register (Register Map Note 3)
0xA8
read-write
n
0x0
0x0
CAN_IF2_MASK1
CAN_IF2_MASK1
IFn Mask 1 Register
0x88
read-write
n
0x0
0x0
CAN_IF2_MASK2
CAN_IF2_MASK2
IFn Mask 2 Register
0x8C
read-write
n
0x0
0x0
CAN_IF2_MCON
CAN_IF2_MCON
IFn Message Control Register
0x98
read-write
n
0x0
0x0
CAN_IIDR
CAN_IIDR
Interrupt Identifier Register
0x10
read-only
n
0x0
0x0
IntId
Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). The Status Interrupt is cleared by reading the Status Register.
0
16
read-only
CAN_IPND1
CAN_IPND1
Interrupt Pending Register 1
0x140
read-only
n
0x0
0x0
IntPnd16_1
Interrupt Pending Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_IPND2
CAN_IPND2
Interrupt Pending Register 2
0x144
read-only
n
0x0
0x0
IntPnd32_17
Interrupt Pending Bits 32-17(Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_MVLD1
CAN_MVLD1
Message Valid Register 1
0x160
read-only
n
0x0
0x0
MsgVal16_1
Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_MVLD2
CAN_MVLD2
Message Valid Register 2
0x164
read-only
n
0x0
0x0
MsgVal32_17
Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_NDAT1
CAN_NDAT1
New Data Register 1
0x120
read-only
n
0x0
0x0
NewData16_1
New Data Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_NDAT2
CAN_NDAT2
New Data Register 2
0x124
read-only
n
0x0
0x0
NewData32_17
New Data Bits 32-17 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_STATUS
CAN_STATUS
Status Register
0x4
read-write
n
0x0
0x0
BOff
Bus-Off Status (Read Only) \n
7
1
read-only
0
The CAN module is not in bus-off state
#0
1
The CAN module is in bus-off state
#1
EPass
Error Passive (Read Only)\n
5
1
read-only
0
The CAN Core is error active
#0
1
The CAN Core is in the error passive state as defined in the CAN Specification
#1
EWarn
Error Warning Status (Read Only)\n
6
1
read-only
0
Both error counters are below the error warning limit of 96
#0
1
At least one of the error counters in the EML has reached the error warning limit of 96
#1
LEC
Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. The following table describes the error code.
0
3
read-write
RxOK
Received A Message Successfully\n
4
1
read-write
0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#0
1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
#1
TxOK
Transmitted A Message Successfully\n
3
1
read-write
0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#0
1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
#1
CAN_TEST
CAN_TEST
Test Register (Register Map Note 1)
0x14
read-write
n
0x0
0x0
Basic
Basic Mode\n
2
1
read-write
0
Basic Mode disabled
#0
1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
#1
LBack
Loop Back Mode Enable Bit\n
4
1
read-write
0
Loop Back Mode is disabled
#0
1
Loop Back Mode is enabled
#1
Res
Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
0
2
read-write
Rx
Monitors The Actual Value Of CAN_RX Pin (Read Only) \n
7
1
read-only
0
The CAN bus is dominant (CAN_RX = '0')
#0
1
The CAN bus is recessive (CAN_RX = '1')
#1
Silent
Silent Mode\n
3
1
read-write
0
Normal operation
#0
1
The module is in Silent Mode
#1
Tx
Tx[1:0]: Control Of CAN_TX Pin\n
5
2
read-write
0
Reset value, CAN_TX pin is controlled by the CAN Core
#00
1
Sample Point can be monitored at CAN_TX pin
#01
2
CAN_TX pin drives a dominant ('0') value
#10
3
CAN_TX pin drives a recessive ('1') value
#11
CAN_TXREQ1
CAN_TXREQ1
Transmission Request Register 1
0x100
read-only
n
0x0
0x0
TxRqst16_1
Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_TXREQ2
CAN_TXREQ2
Transmission Request Register 2
0x104
read-only
n
0x0
0x0
TxRqst32_17
Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_WU_EN
CAN_WU_EN
Wake-up Enable Register
0x168
read-write
n
0x0
0x0
WAKUP_EN
Wake-Up Enable Bit\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin..
0
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
CAN_WU_STATUS
CAN_WU_STATUS
Wake-up Status Register
0x16C
read-write
n
0x0
0x0
WAKUP_STS
Wake-Up Status \nNote: This bit can be cleared by writing '0'.
0
1
read-write
0
No wake-up event occurred
#0
1
Wake-up event occurred
#1
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
0x30
0xC
registers
n
AHBCLK
AHBCLK
AHB Devices Clock Enable Control Register
0x4
read-write
n
0x0
0x0
EBI_EN
EBI Controller Clock Enable Control\n
3
1
read-write
0
EBI engine clock Disabled
#0
1
EBI engine clock Enabled
#1
ISP_EN
Flash ISP Controller Clock Enable Bit\n
2
1
read-write
0
Flash ISP peripherial clock Disabled
#0
1
Flash ISP peripherial clock Enabled
#1
PDMA_EN
PDMA Controller Clock Enable Bit\n
1
1
read-write
0
PDMA peripherial clock Disabled
#0
1
PDMA peripherial clock Enabled
#1
APBCLK
APBCLK
APB Devices Clock Enable Control Register
0x8
read-write
n
0x0
0x0
ACMP_EN
Analog Comparator Clock Enable Bit\n
30
1
read-write
0
Analog Comparator clock Disabled
#0
1
Analog Comparator clock Enabled
#1
ADC_EN
Analog-Digital-Converter (ADC) Clock Enable Bit\n
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
CAN0_EN
CAN Bus Controller-0 Clock Enable Bit\n
24
1
read-write
0
CAN0 clock Disabled
#0
1
CAN0 clock Enable
#1
CAN1_EN
CAN Bus Controller-1 Clock Enable Bit\n
25
1
read-write
0
CAN1 clock Disable
#0
1
CAN1 clock Enabled
#1
FDIV_EN
Frequency Divider Output Clock Enable Bit\n
6
1
read-write
0
FDIV clock Disabled
#0
1
FDIV clock Enabled
#1
I2C0_EN
I2C0 Clock Enable Bit\n
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1_EN
I2C1 Clock Enable Bit\n
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
I2S_EN
I2S Clock Enable Bit\n
29
1
read-write
0
I2S clock Disabled
#0
1
I2S clock Enabled
#1
PS2_EN
PS/2 Clock Enable Bit\n
31
1
read-write
0
PS/2 clock Disabled
#0
1
PS/2 clock Enabled
#1
PWM01_EN
PWM_01 Clock Enable Bit\n
20
1
read-write
0
PWM01 clock Disabled
#0
1
PWM01 clock Enabled
#1
PWM23_EN
PWM_23 Clock Enable Bit\n
21
1
read-write
0
PWM23 clock Disabled
#0
1
PWM23 clock Enabled
#1
PWM45_EN
PWM_45 Clock Enable Bit\n
22
1
read-write
0
PWM45 clock Disabled
#0
1
PWM45 clock Enabled
#1
PWM67_EN
PWM_67 Clock Enable Bit\n
23
1
read-write
0
PWM67 clock Disabled
#0
1
PWM67 clock Enabled
#1
RTC_EN
Real-Time-Clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only, The RTC peripheral clock source is selected from RTC_SEL_10K(CLKSEL2[18]). It can be selected to the 32.768 kHz external low speed crystal oscillator or 10 kHz internal low speed RC oscillator.\n
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0_EN
SPI0 Clock Enable Bit\n
12
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
SPI1_EN
SPI1 Clock Enable Bit\n
13
1
read-write
0
SPI1 clock Disabled
#0
1
SPI1 clock Enabled
#1
SPI2_EN
SPI2 Clock Enable Bit\n
14
1
read-write
0
SPI2 clock Disabled
#0
1
SPI2 clock Enabled
#1
SPI3_EN
SPI3 Clock Enable Bit\n
15
1
read-write
0
SPI3 clock Disabled
#0
1
SPI3 clock Enabled
#1
TMR0_EN
Timer0 Clock Enable Bit\n
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1_EN
Timer1 Clock Enable Bit\n
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2_EN
Timer2 Clock Enable Bit\n
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3_EN
Timer3 Clock Enable Bit\n
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0_EN
UART0 Clock Enable Bit\n
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1_EN
UART1 Clock Enable Bit\n
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2_EN
UART2 Clock Enable Bit\n
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
USBD_EN
USB 2.0 FS Device Controller Clock Enable Bit\n
27
1
read-write
0
USB clock Disabled
#0
1
USB clock Enabled
#1
WDT_EN
Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Watchdog Timer clock Disabled
#0
1
Watchdog Timer clock Enabled
#1
APBCLK1
APBCLK1
APB Devices Clock Enable Control Register 1
0x30
read-write
n
0x0
0x0
SC0_EN
SC0 Clock Enable Bit\n
0
1
read-write
0
SC0 Clock Disabled
#0
1
SC0 Clock Enabled
#1
SC1_EN
SC1 Clock Enable Bit\n
1
1
read-write
0
SC1 clock Disabled
#0
1
SC1 clock Enabled
#1
SC2_EN
SC2 Clock Enable Bit\n
2
1
read-write
0
SC2 clock Disabled
#0
1
SC2 clock Enabled
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC Clock Divide Number From ADC Clock Source\n
16
8
read-write
HCLK_N
HCLK Clock Divide Number From HCLK Clock Source\n
0
4
read-write
UART_N
UART Clock Divide Number From UART Clock Source\n
8
4
read-write
USB_N
USB Clock Divide Number From PLL Clock\n
4
4
read-write
CLKDIV1
CLKDIV1
Clock Divider Number Register 1
0x38
read-write
n
0x0
0x0
SC0_N
SC0 Clock Divide Number From SC0 Clock Source\n
0
8
read-write
SC1_N
SC1 Clock Divide Number From SC1 Clock Source\n
8
8
read-write
SC2_N
SC2 Clock Divide Number From SC2 Clock Source\n
16
8
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Select (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be enabled\nThe 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#001
2
Clock source from PLL clock
#010
3
Clock source from 10 kHz internal low speed RC oscillator clock
#011
7
Clock source from 22.1184 MHz internalhigh speed RC oscillator clock
#111
STCLK_S
Cortex-M0 SysTick Clock Source Select (Write Protect)\n
3
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#001
2
Clock source from 4~24 MHz external high speed crystal oscillator clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from 22.1184 MHz internal high speed RC oscillator clock/2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
read-write
n
0x0
0x0
ADC_S
ADC Clock Source Select\n
2
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
PWM01_S
PWM0 And PWM1 Clock Source Selection\nPWM0 and PWM1 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).\n
28
2
read-write
PWM23_S
PWM2 And PWM3 Clock Source Selection\nPWM2 and PWM3 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).\n
30
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock.\nReserved
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator clock.\nReserved
#01
2
Clock source from HCLK.\nReserved
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock.\nClock source from 10 kHz internal low speed RC oscillator clock
#11
SPI0_S
SPI0 Clock Source Selection\n
4
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI1_S
SPI1 Clock Source Selection\n
5
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI2_S
SPI2 Clock Source Selection\n
6
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI3_S
SPI3 Clock Source Selection\n
7
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
TMR0_S
TIMER0 Clock Source Selection\n
8
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from 10 kHz internal low speed RC oscillator clock
#101
7
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#111
TMR1_S
TIMER1 Clock Source Selection\n
12
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from 10 kHz internal low speed RC oscillator clock
#101
7
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#111
TMR2_S
TIMER2 Clock Source Selection\n
16
3
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#000
1
Clock source from external 32.768 kHz low speed crystal oscillator clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from internal 10 kHz low speed RC oscillator clock
#101
7
Clock source from internal 22.1184 MHz high speed RC oscillator clock
#111
TMR3_S
TIMER3 Clock Source Selection\n
20
3
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from 10 kHz internal low speed RC oscillator clock
#101
7
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#111
UART_S
UART Clock Source Selection\n
24
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
WDT_S
Watchdog Timer Clock Source Select (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
2
read-write
0
Reserved
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from 10 kHz internal low speed RC oscillator clock
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Selection\n
2
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator clock
#01
2
Clock source from HCLK
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
I2S_S
I2S Clock Source Selection\n
0
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
PWM01_S_E
PWM0 And PWM1 Clock Source Selection Extend\nPWM0 and PWM1 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).\n
8
1
read-write
PWM23_S_E
PWM2 And PWM3 Clock Source Selection Extend\nPWM2 and PWM3 used the same peripheral clock source; both of them used the same prescaler. The perpherial clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).\n
9
1
read-write
PWM45_S
PWM4 And PWM5 Clock Source Selection\nPWM4 and PWM5 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10]).\n
4
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock.\nReserved
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator clock.\nReserved
#01
2
Clock source from HCLK.\nReserved
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock.\nClock source from 10 kHz internal low speed RC oscillator clock
#11
PWM45_S_E
PWM4 And PWM5 Clock Source Selection Extend\nPWM4 and PWM5 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10]).\n
10
1
read-write
PWM67_S
PWM6 And PWM7 Clock Source Selection\nPWM6 and PWM7 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]).\n
6
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock.\nReserved
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator clock.\nReserved
#01
2
Clock source from HCLK.\nReserved
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock.\nClock source from 10 kHz internal low speed RC oscillator clock
#11
PWM67_S_E
PWM6 And PWM7 Clock Source Selection Extend\nPWM6 and PWM7 used the same peripheral clock source; both of them used the same prescaler. The peripheral clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]).\n
11
1
read-write
RTC_SEL_10K
RTC Clock Source Selection\n
18
1
read-write
0
Clock source from 32.768 kHz external low speed crystal oscillator clock
#0
1
Clock source from 10 kHz internal low speed RC oscillator clock
#1
WWDT_S
Window Watchdog Timer Clock Source Selection\n
16
2
read-write
2
Clock source from HCLK/2048 clock
#10
3
Clock source from 10 kHz internal low speed RC oscillator clock
#11
CLKSEL3
CLKSEL3
Clock Source Select Control Register 3
0x34
read-write
n
0x0
0x0
SC0_S
SC0 Clock Source Selection\n
0
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
SC1_S
SC1 Clock Source Selection\n
2
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
SC2_S
SC2 Clock Source Selection\n
4
2
read-write
0
Clock source from 4~24 MHz external high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from 22.1184 MHz internal high speed RC oscillator clock
#11
CLKSTATUS
CLKSTATUS
Clock Status Monitor Register
0xC
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switch system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
OSC10K_STB
Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)\n
3
1
read-only
0
10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
OSC22M_STB
22.1184 MHz Internal High Speed RC Oscillator (HIRC) Clock Source Stable Flag (Read Only)\n
4
1
read-only
0
22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
22.1184 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
#1
PLL_STB
Internal PLL Clock Source Stable Flag (Read Only)\n
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable in normal mode
#1
XTL12M_STB
4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)\n
0
1
read-only
0
4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
#1
XTL32K_STB
32.768 KHz External Low Speed Crystallator Oscillator (LXT) Clock Source Stable Flag (Read Only)\n
1
1
read-only
0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock is stable and enabled
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
CLKO_1HZ_EN
Clock Output 1Hz Enable Bit\n
6
1
read-write
0
1 Hz clock output for 32.768 kHz external low speed crystal oscillator clock frequency compensation Disabled
#0
1
1 Hz clock output for 32.768 kHz external low speed crystal oscillator clock frequency compensation Enabled
#1
DIVIDER1
Frequency Divider One Enable Bit\n
5
1
read-write
0
Frequency divider will output clock with source frequency divided by FSEL
#0
1
Frequency divider will output clock with source frequency
#1
DIVIDER_EN
Frequency Divider Enable Bit\n
4
1
read-write
0
Frequency Divider function Disabled
#0
1
Frequency Divider function Enabled
#1
FSEL
Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
PLLCON
PLLCON
PLL Control Register
0x20
read-write
n
0x0
0x0
BP
PLL Bypass Control\n
17
1
read-write
0
PLL is in Normal mode (default)
#0
1
PLL clock output is same as PLL source clock input
#1
FB_DV
PLL Feedback Divider Control Bits\nRefer to the formulas below the table.
0
9
read-write
IN_DV
PLL Input Divider Control Bits\nRefer to the formulas below the table.
9
5
read-write
OE
PLL OE (FOUT Enable) Pin Control\n
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUT_DV
PLL Output Divider Control Bits\nRefer to the formulas below the table.
14
2
read-write
PD
Power-Down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n
16
1
read-write
0
PLL is in Normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLL_SRC
PLL Source Clock Selection\n
19
1
read-write
0
PLL source clock from 4~24 MHz external high speed crystal oscillator
#0
1
PLL source clock from 22.1184 MHz internal high speed RC oscillator
#1
PWRCON
PWRCON
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
3
1
read-write
0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
10 kHz internal low speed RC oscillator (LIRC) Enabled
#1
OSC22M_EN
22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
2
1
read-write
0
22.1184 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
22.1184 MHz internal high speed RC oscillator (HIRC) Enabled
#1
PD_WAIT_CPU
Power-Down Entry Condition Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
8
1
read-write
0
Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1
#0
1
Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction
#1
PD_WU_DLY
Wake-Up Delay Counter Enable Bit (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PD_WU_INT_EN
Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
Note2: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PD_WU_STS
Power-Down Mode Wake-Up Interrupt Status
Set by Power-down wake-up event , it indicates that resume from Power-down mode
The flag is set if the GPIO, USB, UART, WDT, I2C, TIMER, ACMP, BOD or RTC wake-up occurred
Write 1 to clear the bit to 0.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
6
1
read-write
PWR_DOWN_EN
System Power-Down Enable Bit (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.
(b) if the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend)
When chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.
In Power-down mode, 4~24 MHz external high speed crystal oscillator and the 22.1184 MHz internal high speed RC oscillator will be disabled in this mode, but the 32.768 kHz external low speed crystal oscillator and 10 kHz internal low speed oscillator are not controlled by Power-down mode.
In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 32.768 kHz external low speed crystal oscillator or the internal 10 kHz low speed oscillator.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
7
1
read-write
0
Chip operating normally or chip in Idle mode because of WFI command
#0
1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
#1
XTL12M_EN
4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect)
The bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from 4~24 MHz external high speed crystal oscillator, this bit is set to 1 automatically.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
4 ~ 24 MHz external high speed crystal oscillators (HXT) Disabled
#0
1
4~24 MHz external high speed crystal oscillator (HXT) Enabled
#1
XTL32K_EN
32.768 KHz External Low Speed Crystal Oscillator (LXT) Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
1
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) Enabled (Normal operation)
#1
CRC
PDMA Register Map
PDMA
0x0
0x0
0x8
registers
n
0x14
0x4
registers
n
0x1C
0xC
registers
n
0x80
0xC
registers
n
0xC
0x4
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0x88
read-only
n
0x0
0x0
CRC_CHECKSUM
CRC Checksum Register\nThis fields indicates the CRC checksum result
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
read-write
n
0x0
0x0
CHECKSUM_COM
Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.\n
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHECKSUM_RVS
Checksum Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CPU_WDLEN
CPU Write Data Length\nThis field indicates the CPU write data length only when operating in CPU PIO mode.\nNote1: This field is only valid when operating in CPU PIO mode.\nNote2: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
28
2
read-write
0
The write data length is 8-bit mode
#00
1
The write data length is 16-bit mode
#01
2
The write data length is 32-bit mode
#10
3
Reserved
#11
CRCCEN
CRC Channel Enable Bit\n
0
1
read-write
0
No effect
#0
1
CRC operation Enabled
#1
CRC_MODE
CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.\n
30
2
read-write
0
CRC-CCITT Polynomial Mode
#00
1
CRC-8 Polynomial Mode
#01
2
CRC-16 Polynomial Mode
#10
3
CRC-32 Polynomial Mode
#11
CRC_RST
CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value (CRC_SEED register).
1
1
read-write
0
No effect
#0
1
Reset the internal CRC state machine and internal buffer. The others contents of CRC_CTL register will not be cleared. This bit will be cleared automatically
#1
TRIG_EN
Trigger Enable Bit\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped. Software must reset all DMA channel before trigger DMA again.
23
1
read-write
0
No effect
#0
1
CRC DMA data read or write transfer Enabled
#1
WDATA_COM
Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_WDATA register.\n
26
1
read-write
0
1's complement for CRC write data in Disabled
#0
1
1's complement for CRC write data in Enabled
#1
WDATA_RVS
Write Data Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_WDATA register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
24
1
read-write
0
Bit order reverse for CRC write data in Disabled
#0
1
Bit order reverse for CRC write data in Enabled (per byte)
#1
DMABCR
CRC_DMABCR
CRC DMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
CRC_DMABCR
CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit total transfer byte count number of CRC DMA\n
0
16
read-write
DMACBCR
CRC_DMACBCR
CRC DMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
CRC_DMACBCR
CRC DMA Current Remained Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting CRC_RST (CRC_CTL[1]) bit to 1 will clear this register value.
0
16
read-only
DMACSAR
CRC_DMACSAR
CRC DMA Current Source Address Register
0x14
read-only
n
0x0
0x0
CRC_DMACSAR
CRC DMA Current Source Address Register (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs.\n
0
32
read-only
DMAIER
CRC_DMAIER
CRC DMA Interrupt Enable Register
0x20
read-write
n
0x0
0x0
CRC_BLKD_IE
CRC DMA Block Transfer Done Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF (CRC_DMAISR[1]) bit is set to 1.\n
1
1
read-write
0
Interrupt generator Disabled when CRC DMA transfer done
#0
1
Interrupt generator Enabled when CRC DMA transfer done
#1
CRC_TABORT_IE
CRC DMA Read/Write Target Abort Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF (CRC_DMAISR[0]) bit is set to 1.\n
0
1
read-write
0
Target abort interrupt generation Disabled during CRC DMA transfer
#0
1
Target abort interrupt generation Enabled during CRC DMA transfer
#1
DMAISR
CRC_DMAISR
CRC DMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
CRC_BLKD_IF
CRC DMA Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA transfer has finished or not.\nIt is cleared by writing 1 to it through software..\n(When CRC DMA transfer done, TRIG_EN (CRC_CTL[23]) bit will be cleared automatically)
1
1
read-write
0
Not finished if TRIG_EN (CRC_CTL[23]) bit has enabled
#0
1
CRC transfer done if TRIG_EN (CRC_CTL[23]) bit has enabled
#1
CRC_TABORT_IF
CRC DMA Read/Write Target Abort Interrupt Flag\nThis bit indicates that CRC bus has error or not during CRC DMA transfer.\nIt is cleared by writing 1 to it through software.\nNote: The bit filed indicate bus master received error response or not. If bus master received error response, it means that CRC transfer target abort is happened. DMA will stop transfer and respond this event to software then CRC state machine goes to IDLE state. When target abort occurred, software must reset DMA before transfer those data again.
0
1
read-write
0
No bus error response received during CRC DMA transfer
#0
1
Bus error response received during CRC DMA transfer
#1
DMASAR
CRC_DMASAR
CRC DMA Source Address Register
0x4
read-write
n
0x0
0x0
CRC_DMASAR
CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x84
read-write
n
0x0
0x0
CRC_SEED
CRC Seed Register\nThis field indicates the CRC seed value.
0
32
read-write
WDATA
CRC_WDATA
CRC Write Data Register
0x80
read-write
n
0x0
0x0
CRC_WDATA
CRC Write Data Register\nWhen operating in CPU PIO mode, software can write data to this field to perform CRC operation.\nWhen operating in DMA mode, this field indicates the DMA read data from memory and cannot be written.\nNote: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
0
32
read-write
EBI
EBI Register Map
EBI
0x0
0x0
0xC
registers
n
EBICON
EBICON
External Bus Interface General Control Register
0x0
read-write
n
0x0
0x0
ExtBW16
EBI Data Width 16-bit/8-bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
1
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
ExtEN
EBI Enable\nThis bit is the functional enable bit for EBI.\n
0
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
ExttALE
Expand Time of ALE\nThis field is used for control the ALE pulse width (tALE) for latch the address \n
16
3
read-write
MCLKDIV
External Output Clock Divider\n
8
3
read-write
EBICON2
EBICON2
External Bus Interface General Control Register 2
0x8
read-write
n
0x0
0x0
RAHD_OFF
Access Hold Time Disable Control When Read\n
1
1
read-write
0
tAHD is controlled by ExttAHD when read through EBI
#0
1
No tAHD when read through EBI
#1
WAHD_OFF
Access Hold Time Disable Control When Write\n
2
1
read-write
0
tAHD is controlled by ExttAHD when write through EBI
#0
1
No tAHD when write through EBI
#1
WBUFF_EN
EBI Write Buffer Enable\n
0
1
read-write
0
EBI write buffer disable
#0
1
EBI write buffer enable
#1
EXTIME
EXTIME
External Bus Interface Timing Control Register
0x4
read-write
n
0x0
0x0
ExtIR2R
Idle State Cycle Between Read-Read\nWhen read action is finished and the next action is going to read, idle state is inserted and nCS signal return to high if ExtIR2R is not zero.\n
24
4
read-write
ExtIW2X
Idle State Cycle After Write\nWhen write action is finished, idle state is inserted and nCS signal return to high if ExtIW2X is not zero.\n
12
4
read-write
ExttACC
EBI Data Access Time\nExttACC defines data access time (tACC).\n
3
5
read-write
ExttAHD
EBI Data Access Hold Time\nExttAHD defines data access hold time (tAHD).\n
8
3
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
DFBADR
DFBADR
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBADR
Data Flash Base Address\nThis register indicates Data Flash start address. It is read only.\nFor 128 KB flash memory device, the Data Flash size is defined by user configuration, register content is loaded from CONFIG1 when chip is powered on but for 64/32 KB device, it is fixed at 0x0001_F000.
0
32
read-only
FATCON
FATCON
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
FOMSEL0
Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)\nWhen CPU frequency is lower than 72 MHz, user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance.\n
4
1
read-write
FOMSEL1
Chip Frequency Optimization Mode Select1 (Write-protection Bit)
6
1
read-write
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address\nThe NuMicro( NUC230/240 series has a maximum of 32Kx32 (128 KB) embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
ISPCMD
ISP Command\nISP command table is shown below:\n
0
6
read-write
0
Read
0x00
4
Read Unique ID
0x04
11
Read Company ID (0xDA)
0x0b
33
Program
0x21
34
Page Erase
0x22
46
Set Vector Page Re-Map
0x2e
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)\n
3
1
read-write
0
APROM cannot be updated when chip runs in APROM
#0
1
APROM can be updated when chip runs in APROM
#1
BS
Boot Select (Write Protect )\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
Enable Config Update By ISP (Write Protect)\n
4
1
read-write
0
ISP update config-bit Disabled
#0
1
ISP update config-bit Enabled
#1
ISPEN
ISP Enable Bit (Write Protect )\nISP function enable bit. Set this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear to this bit to 0.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when chip runs in APROM
#1
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
0
32
read-write
ISPSTA
ISPSTA
ISP Status Register
0x40
read-write
n
0x0
0x0
CBS
Chip Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0.
1
2
read-only
ISPFF
ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear this bit.\nNote: The function of this bit is the same as ISPCON bit6
6
1
read-write
ISPGO
ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0
0
1
read-only
0
ISP operation finished
#0
1
ISP operation progressed
#1
VECMAP
Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
9
12
read-only
ISPTRG
ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write-Protection Bit)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
0
1
read-write
0
ISP operation finished
#0
1
ISP progressed
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x18
0x8
registers
n
0x24
0x4
registers
n
0x30
0x18
registers
n
0x50
0x4
registers
n
0x58
0x8
registers
n
0x80
0xC
registers
n
ALT_MFP
ALT_MFP
Alternative Multiple Function Pin Control Register
0x50
read-write
n
0x0
0x0
EBI_EN
EBI_EN is use to switch GPIO function to EBI function (AD[15:0], ALE, RE, WE, CS, MCLK), it need additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8], MCLK)
11
1
read-write
EBI_HB_EN0
Bits EBI_HB_EN[0] (ALT_MFP[16]), EBI_EN (ALT_MFP[11]),PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN, EBI_EN, PA5_SC1RST, GPA_MFP5) value and function mapping is as following list,\n
16
1
read-write
EBI_HB_EN1
Bits EBI_HB_EN[1] (ALT_MFP[17]), EBI_EN (ALT_MFP[11]), PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] determine the PA.4 function.\n(EBI_HB_EN, EBI_EN, PA4_SC1PWR, GPA_MFP4) value and function mapping is as following list.\n
17
1
read-write
EBI_HB_EN2
Bits EBI_HB_EN[2] (ALT_MFP[18]), EBI_EN (ALT_MFP[11]), PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN, EBI_EN PA3_SC0DAT, GPA_MFP3) value and function mapping is as following list.\n
18
1
read-write
EBI_HB_EN3
Bits EBI_HB_EN[3] (ALT_MFP[19]), EBI_EN (ALT_MFP[11]), PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN, EBI_EN, PA2_SC0CLK, GPA_MFP2) value and function mapping is as following list.\n
19
1
read-write
EBI_HB_EN4
Bit EBI_HB_EN[4] (ALT_MFP[20]), EBI_EN (ALT_MFP[11]), PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN, EBI_EN, PA1_SC0RST, GPA_MFP1) value and function mapping is as following list.\n
20
1
read-write
EBI_HB_EN5
Bits EBI_HB_EN[5] (ALT_MFP[21]), EBI_EN (ALT_MFP[11]), PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] determine the PA.12 function.\n(EBI_HB_EN, EBI_EN, PA12_SC2DAT, GPA_MFP12) value and function mapping is as following list.\n
21
1
read-write
EBI_HB_EN6
Bits EBI_HB_EN[6] (ALT_MFP[22]), EBI_EN (ALT_MFP[11]), PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] determine the PA.13 function.\n(EBI_HB_EN, EBI_EN, PA13_SC2CLK, GPA_MFP13) value and function mapping is as following list.\n
22
1
read-write
EBI_HB_EN7
Bits EBI_HB_EN[7] (ALT_MFP[23]), EBI_EN (ALT_MFP[11]), PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] determine the PA.14 function.\n(EBI_HB_EN, EBI_EN, PA14_SC2RST, GPA_MFP14) value and function mapping is as following list.\n
23
1
read-write
EBI_MCLK_EN
Bits EBI_MCLK_EN (ALT_MFP[12]), EBI_EN (ALT_MFP[11]), GPC_MFP[8] determine the PC.8 function.
(EBI_MCLK_EN, EBI_EN, GPC_MFP8) value and function mapping is as following list.
12
1
read-write
EBI_nWRH_EN
Bits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.
(EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.
14
1
read-write
EBI_nWRL_EN
Bits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.\n
13
1
read-write
PA10_11_CAN1
PA.10 And PA.11 Pin Alternative Function Selection\nBits PA10_11_CAN1 (ALT_MFP[28]) and GPA_MFP[11] determine the PA.11 function.\n(PA10_11_CAN1, GPA_MFP11) value and function mapping is as following list.\n
28
1
read-write
PA15_I2SMCLK
PA.15 Pin Alternative Function Selection\nBits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] determine the PA.15 function.\n(PA15_SC2PWR, PA15_I2SMCLK, GPA_MFP15) value and function mapping is as following list.\n
9
1
read-write
PA7_S21
PA.7 Pin Alternative Function Selection\nBits EBI_EN (ALT_MFP[11]), PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] determine the PA.7 function.\n(EBI_EN, PA7_SC1DAT, PA7_S21, GPA_MFP7) value and function mapping is as following list.\n
2
1
read-write
PB10_S01
PB.10 Pin Alternative Function Selection\nBits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.\n(PB10_S01, GPB_MFP10) value and function mapping is as following list.\n
0
1
read-write
PB11_PWM4
PB.11 Pin Alternative Function Selection\nBits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function.\n(PB11_PWM4, GPB_MFP11) value and function mapping is as following list.\n
4
1
read-write
PB14_S31
PB.14 Pin Alternative Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]), PB14_S31 (ALT_MFP[3]) and GPB_MFP[14] determine the PB.14 function.\n(PB14_15_EBI , PB14_S31, GPB_MFP14) value and function mapping is as following list\n
3
1
read-write
PB15_T0EX
PB.15 Pin Alternative Function Selection
Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.
(PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
24
1
read-write
PB2_CPO0
PB.2 Pin Alternative Function Selection\nBits PB2_TM2 (ALT_MFP2[4]), PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(PB2_TM2, PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.\n
30
1
read-write
PB2_T2EX
PB.2 Pin Alternative Function Selection\nBits PB2_TM2 (ALT_MFP2[4]), PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(PB2_TM2, PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.\n
26
1
read-write
PB3_T3EX
PB.3 Pin Alternative Function Selection\nBits PB3_TM3 (ALT_MFP2[5]), PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(PB3_TM3, PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.\n
27
1
read-write
PB8_CLKO
PB.8 Pin Alternative Function Selection\nBits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function.\n(PB8_CLKO, GPB_MFP8) value and function mapping is as following list.\n
29
1
read-write
PB9_S11
PB.9 Pin Alternative Function Selection\nBits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function.\n(PB9_S11, GPB_MFP9) value and function mapping is as following list.\n
1
1
read-write
PC0_I2SLRCLK
Bits PC0_I2SLRCLK (ALT_MFP[5]) And GPC_MFP[0] Determine The PC.0 Function\nBits PC0_I2SLRCLK (ALT_MFP[5]) and GPC_MFP[0] determine the PC.0 function.\n(PC0_I2SLRCLK, GPC_MFP0) value and function mapping is as following list.\n
5
1
read-write
PC1_I2SBCLK
PC.1 Pin Alternative Function Selection\nBits PC1_I2SBCLK (ALT_MFP[6]) and GPC_MFP[1] determine the PC.1 function.\n(PC1_I2SBCLK, GPC_MFP1) value and function mapping is as following list.\n
6
1
read-write
PC2_I2SDI
PC.2 Pin Alternative Function Selection\nBits PC2_I2SDI (ALT_MFP[7]) and GPC_MFP[2] determine the PC.2 function.\n(PC2_I2SDI, GPC_MFP2) value and function mapping is as following list.\n
7
1
read-write
PC3_I2SDO
PC.3 Pin Alternative Function Selection\nBits PC3_I2SDO (ALT_MFP[8]) and GPC_MFP[3] determine the PC.3 function.\n(PC3_I2SDO, GPC_MFP3) value and function mapping is as following list.\n
8
1
read-write
PE5_T1EX
PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list.\n
25
1
read-write
ALT_MFP1
ALT_MFP1
Alternative Multiple Function Pin Control Register 1
0x58
read-write
n
0x0
0x0
PA0_SC0PWR
PA.0 Pin Alternative Function Selection\nBit PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] determine the PA.0 function.\n(PA0_SC0PWR, GPA_MFP0) value and function mapping is as following list.\n
2
1
read-write
PA12_SC2DAT
PA.12 Pin Alternative Function Selection\nBits EBI_HB_EN[5] (ALT_MFP[21]), EBI_EN (ALT_MFP[11]), PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] determine the PA.12 function.\n(EBI_HB_EN, EBI_EN, PA12_SC2DAT, GPA_MFP12) value and function mapping is as following list.\n
11
1
read-write
PA13_SC2CLK
PA.13 Pin Alternative Function Selection\nBits EBI_HB_EN[6] (ALT_MFP[22]), EBI_EN (ALT_MFP[11]), PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] determine the PA.13 function.\n(EBI_HB_EN, EBI_EN, PA13_SC2CLK, GPA_MFP13) value and function mapping is as following list.\n
10
1
read-write
PA14_SC2RST
PA.14 Pin Alternative Function Selection\nBits EBI_HB_EN[7] (ALT_MFP[23]), EBI_EN (ALT_MFP[11]), PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] determine the PA.14 function.\n(EBI_HB_EN, EBI_EN, PA14_SC2RST, GPA_MFP14) value and function mapping is as following list.\n
13
1
read-write
PA15_SC2PWR
PA.15 Pin Alternative Function Selection\nBits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] determine the PA.15 function.\n(PA15_SC2PWR, PA15_I2SMCLK, GPA_MFP15) value and function mapping is as following list.\n
12
1
read-write
PA1_SC0RST
PA.1 Pin Alternative Function Selection\nBit EBI_HB_EN[4] (ALT_MFP[20]), EBI_EN (ALT_MFP[11]), PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN, EBI_EN, PA1_SC0RST, GPA_MFP1) value and function mapping is as following list.\n
3
1
read-write
PA2_SC0CLK
PA.2 Pin Alternative Function Selection\nBits EBI_HB_EN[3] (ALT_MFP[19]), EBI_EN (ALT_MFP[11]), PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN, EBI_EN, PA2_SC0CLK, GPA_MFP2) value and function mapping is as following list.\n
0
1
read-write
PA3_SC0DAT
PA.3 Pin Alternative Function Selection\nBits EBI_HB_EN[2] (ALT_MFP[18]), EBI_EN (ALT_MFP[11]), PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN, EBI_EN PA3_SC0DAT, GPA_MFP3) value and function mapping is as following list.\n
1
1
read-write
PA4_SC1PWR
PA.4 Pin Alternative Function Selection\nBits EBI_HB_EN[1] (ALT_MFP[17]), EBI_EN (ALT_MFP[11]),PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN, EBI_EN, PA5_SC1RST, GPA_MFP5) value and function mapping is as following list.\n
7
1
read-write
PA5_SC1RST
PA.5 Pin Alternative Function Selection\nBits EBI_HB_EN[1] (ALT_MFP[17]), EBI_EN (ALT_MFP[11]),PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN , EBI_EN, PA5_SC1RST, GPA_MFP5) value and function mapping is as following list.\n
8
1
read-write
PA6_SC1CLK
PA.6 Pin Alternative Function Selection\nBits EBI_EN (ALT_MFP[11]), PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] determine the PA.6 function.\n(EBI_EN , PA6_SC1CLK, GPA_MFP6) value and function mapping is as following list.\n
5
1
read-write
PA7_SC1DAT
PA.7 Pin Alternative Function Selection\nBits EBI_EN (ALT_MFP[11]), PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] determine the PA.7 function.\n(EBI_EN, PA7_SC1DAT, PA7_S21, GPA_MFP7) value and function mapping is as following list.\n
6
1
read-write
PB3_SC2CD
PB.3 Pin Alternative Function Selection\nBits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(EBI_nWRH_EN, EBI_EN PB3_TM3, PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.\n
14
1
read-write
PC6_SC0CD
PC.6 Pin Alternative Function Selection\nBits EBI_EN (ALT_MFP[11]), PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] determine the PC.6 function.\n(EBI_EN, PC6_SC0CD, GPB_MFP6) value and function mapping is as following list.\n
4
1
read-write
PC7_SC1CD
PC.7 Pin Alternative Function Selection\nBits EBI_EN (ALT_MFP[11]), PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] determine the PC.7 function.\n(EBI_EN, PC7_SC1CD, GPC_MFP7) value and function mapping is as following list.\n
9
1
read-write
ALT_MFP2
ALT_MFP2
Alternative Multiple Function Pin Control Register 2
0x5C
read-write
n
0x0
0x0
PB14_15_EBI
Bits PB15_T0EX (ALT_MFP[24]), PB14_15_EBI (ALT_MFP2[1]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.\n
1
1
read-write
PB15_TM0
PB.15 Pin Alternative Function Selection
Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.
(PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
2
1
read-write
PB2_TM2
PB.2 Pin Alternative Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.\n
4
1
read-write
PB3_TM3
PB.3 Pin Alternative Function Selection\nBits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.\n(EBI_nWRH_EN, EBI_EN PB3_TM3, PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.\n
5
1
read-write
PD14_15_CAN1
PD.14 And PD.15 Pin Alternative Function Selection\nBits PD14_15_CAN1 (ALT_MFP2[0]) and GPD_MFP[15] determine the PD.15 function.\n(PD14_15_CAN1, GPD_MFP15) value and function mapping is as following list.\n
0
1
read-write
PE5_TM1
PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list.\n
3
1
read-write
BODCR
BODCR
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-Out Detector Enable Bit (Write Protect)
The default value is set by flash memory controller user configuration register CBODEN(CONFIG0[23]) bit.
Note: This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BOD_INTF
Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BOD_LPM
Brown-Out Detector Low Power Mode (Write Protect)
Note1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.
Note2: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
5
1
read-write
0
BOD operated in Normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BOD_OUT
Brown-Out Detector Output Status\n
6
1
read-write
0
Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#0
1
Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0
#1
BOD_RSTEN
Brown-Out Reset Enable Bit (Write Protect)
While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high).
Note1: While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).
Note2: The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.
Note3: This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
3
1
read-write
0
Brown-out INTERRUPT function Enabled
#0
1
Brown-out RESET function Enabled
#1
BOD_VL
Brown-Out Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash momory controller user configuration register CBOV(CONFIG0[22:21]) bit .
Note: This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
1
2
read-write
0
Brown-out voltage is 2.2V
#00
1
Brown-out voltage is 2.7V
#01
2
Brown-out voltage is 3.7V
#10
3
Brown-out voltage is 4.4V
#11
LVR_EN
Low Voltage Reset Enable Bit (Write Protect)
The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default)
#1
GPA_MFP
GPA_MFP
GPIOA Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
GPA_MFP0
PA.0 Pin Function Selection\nBit PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] determine the PA.0 function.\n(PA0_SC0PWR, GPA_MFP0) value and function mapping is as following list.\n
0
1
read-write
GPA_MFP1
PA.1 Pin Function Selection\nBit EBI_HB_EN[4] (ALT_MFP[20]), EBI_EN (ALT_MFP[11]), PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN, EBI_EN, PA1_SC0RST, GPA_MFP1) value and function mapping is as following list.\n
1
1
read-write
GPA_MFP10
PA.10 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]), PA10_11_CAN1 (ALT_MFP[28]) and GPA_MFP[10] determine the PA.10 function.\n(EBI_EN, PA10_11_CAN1, GPA_MFP10) value and function mapping is as following list.\n
10
1
read-write
GPA_MFP11
PA.11 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]), PA10_11_CAN1 (ALT_MFP[28]) and GPA_MFP[11] determine the PA.11 function.\n(EBI_EN, PA10_11_CAN1, GPA_MFP11) value and function mapping is as following list.\n
11
1
read-write
GPA_MFP12
PA.12 Pin Function Selection
Bits EBI_HB_EN[5] (ALT_MFP[21]), EBI_EN (ALT_MFP[11]), PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] determine the PA.12 function.
(EBI_HB_EN, EBI_EN, PA12_SC2DAT, GPA_MFP12) value and function mapping is as following list.
12
1
read-write
GPA_MFP13
PA.13 Pin Function Selection
Bits EBI_HB_EN[6] (ALT_MFP[22]), EBI_EN (ALT_MFP[11]), PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] determine the PA.13 function.
(EBI_HB_EN, EBI_EN, PA13_SC2CLK, GPA_MFP13) value and function mapping is as following list.
13
1
read-write
GPA_MFP14
PA.14 Pin Function Selection
Bits EBI_HB_EN[7] (ALT_MFP[23]), EBI_EN (ALT_MFP[11]), PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] determine the PA.14 function.
(EBI_HB_EN , EBI_EN, PA14_SC2RST, GPA_MFP14) value and function mapping is as following list.
14
1
read-write
GPA_MFP15
PA.15 Pin Function Selection\nBits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] determine the PA.15 function.\n(PA15_SC2PWR, PA15_I2SMCLK, GPA_MFP15) value and function mapping is as following list.\n
15
1
read-write
GPA_MFP2
PA.2 Pin Function Selection\nBits EBI_HB_EN[3] (ALT_MFP[19]), EBI_EN (ALT_MFP[11]), PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN, EBI_EN, PA2_SC0CLK, GPA_MFP2) value and function mapping is as following list.\n
2
1
read-write
GPA_MFP3
PA.3 Pin Function Selection\nBits EBI_HB_EN[2] (ALT_MFP[18]), EBI_EN (ALT_MFP[11]), PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN, EBI_EN, PA3_SC0DAT, GPA_MFP3) value and function mapping is as following list.\n
3
1
read-write
GPA_MFP4
PA.4 Pin Function Selection\nBits EBI_HB_EN[1] (ALT_MFP[17]), EBI_EN (ALT_MFP[11]), PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] determine the PA.4 function.\n(EBI_HB_EN, EBI_EN, PA4_SC1PWR, GPA_MFP4) value and function mapping is as following list.\n
4
1
read-write
GPA_MFP5
PA.5 Pin Function Selection\nBits EBI_HB_EN[0] (ALT_MFP[16]), EBI_EN (ALT_MFP[11]),PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN, EBI_EN, PA5_SC1RST, GPA_MFP5) value and function mapping is as following list,\n
5
1
read-write
GPA_MFP6
PA.6 Pin Function Selection
Bits EBI_EN (ALT_MFP[11]), PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] determine the PA.6 function.
(EBI_EN, PA6_SC1CLK, GPA_MFP6) value and function mapping is as following list.
6
1
read-write
GPA_MFP7
PA.7 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]), PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] determine the PA.7 function.\n(EBI_EN, PA7_SC1DAT, PA7_S21, GPA_MFP7) value and function mapping is as following list.\n
7
1
read-write
GPA_MFP8
PA.8 Pin Function Selection\nBit GPA_MFP[8] determines the PA.9 function.\n
8
1
read-write
0
GPIO function is selected to the pin PA.8
#0
1
I2C0_SDA function is selected to the pin PA.8
#1
GPA_MFP9
PA.9 Pin Function Selection\nBit GPA_MFP[9] determines the PA.9 function.\n
9
1
read-write
0
GPIO function is selected
#0
1
I2C0_SCL function is selected
#1
GPA_TYPEn
Trigger Function Selection\n
16
16
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOA[15:0] I/O input Schmitt Trigger function Enabled
1
GPB_MFP
GPB_MFP
GPIOB Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
GPB_MFP0
PB.0 Pin Function Selection\nBit GPB_MFP[0] determines the PB.0 function.\n
0
1
read-write
0
GPIO function is selected to the pin PB.0
#0
1
UART0_RXD function is selected to the pin PB.0
#1
GPB_MFP1
PB.1 Pin Function Selection\nBit GPB_MFP[1] determines the PB.1 function.\n
1
1
read-write
0
GPIO function is selected to the pin PB.1
#0
1
UART0_TXD function is selected to the pin PB.1
#1
GPB_MFP10
PB.10 Pin Function Selection\nBits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.\n(PB10_S01, GPB_MFP10) value and function mapping is as following list.\n
10
1
read-write
GPB_MFP11
PB.11 Pin Function Selection\nBits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function.\n(PB11_PWM4, GPB_MFP11) value and function mapping is as following list.\n
11
1
read-write
GPB_MFP12
Reserved
12
1
read-write
GPB_MFP13
PB.13 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]), GPB_MFP[13] determines the PB.13 function.\n(EBI_EN, GPB_MFP13) value and function mapping is as following list\n
13
1
read-write
GPB_MFP14
PB.14 Pin Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]), PB14_S31 (ALT_MFP[3]) and GPB_MFP[14] determine the PB.14 function.\n(PB14_15_EBI , PB14_S31, GPB_MFP14) value and function mapping is as following list\n
14
1
read-write
GPB_MFP15
PB.15 Pin Function Selection
Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function.
(PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
15
1
read-write
GPB_MFP2
PB.2 Pin Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_CPO0, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.\n
2
1
read-write
GPB_MFP3
PB.3 Pin Function Selection
Bits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function.
(EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_SC2CD, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.
3
1
read-write
GPB_MFP4
PB.4 Pin Function Selection\nBit GPB_MFP[4] determines the PB.4 function.\n
4
1
read-write
0
GPIO function is selected to the pin PB.4
#0
1
UART1_RXD function is selected to the pin PB.4
#1
GPB_MFP5
PB 5 Pin Function Selection\nBit GPB_MFP[5] determines the PB.5 function.\n
5
1
read-write
0
GPIO function is selected to the pin PB.5
#0
1
UART1_TXD function is selected to the pin PB.5
#1
GPB_MFP6
PB.6 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]), GPB_MFP[6] determines the PB.6 function.\n(EBI_EN, GPB_MFP6) value and function mapping is as following list.\n
6
1
read-write
GPB_MFP7
PB.7 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]), GPB_MFP[7] determines the PB.7 function.\n(EBI_EN, GPB_MFP7) value and function mapping is as following list.\n
7
1
read-write
GPB_MFP8
PB.8 Pin Function Selection\nBits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function.\n(PB8_CLKO, GPB_MFP8) value and function mapping is as following list.\n
8
1
read-write
GPB_MFP9
PB.9 Pin Function Selection\nBits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function.\n(PB9_S11, GPB_MFP9) value and function mapping is as following list.\n
9
1
read-write
GPB_TYPEn
Trigger Function Selection\n
16
16
read-write
0
GPIOB[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOB[15:0] I/O input Schmitt Trigger function Enabled
1
GPC_MFP
GPC_MFP
GPIOC Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
GPC_MFP0
PC.0 Pin Function Selection\nBits PC0_I2SLRCLK (ALT_MFP[5]) and GPC_MFP[0] determine the PC.0 function.\n(PC0_I2SLRCLK, GPC_MFP0) value and function mapping is as following list.\n
0
1
read-write
GPC_MFP1
PC.1 Pin Function Selection\nBits PC1_I2SBCLK (ALT_MFP[6]) and GPC_MFP[1] determine the PC.1 function.\n(PC1_I2SBCLK, GPC_MFP1) value and function mapping is as following list.\n
1
1
read-write
GPC_MFP10
PC.10 Pin Function Selection\nBit GPC_MFP[10] determines the PC.10 function.\n
10
1
read-write
0
GPIO function is selected to the pin PC.10
#0
1
SPI1_MISO0 function is selected to the pin PC.10
#1
GPC_MFP11
PC.11 Pin Function Selection\nBit GPC_MFP[11] determines the PC.11 function.\n
11
1
read-write
0
GPIO function is selected to the pin PC.11
#0
1
SPI1_MOSI0 function is selected to the pin PC.11
#1
GPC_MFP12
PC.12 Pin Function Selection\nBit GPC_MFP[12] determines the PC.12 function.\n
12
1
read-write
0
GPIO function is selected to the pin PC.12
#0
1
SPI1_MISO1 function is selected to the pin PC.12
#1
GPC_MFP13
PC.13 Pin Function Selection\nBit GPC_MFP[13] determines the PC.13 function.\n
13
1
read-write
0
GPIO function is selected to the pin PC.13
#0
1
SPI1_MOSI1 function is selected to the pin PC.13
#1
GPC_MFP14
PC.14 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[14] determine the PC.14 function.\n(EBI_EN, GPC_MFP14) value and function mapping is as following list\n
14
1
read-write
GPC_MFP15
PC.15 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[15] determine the PC.15 function.\n(EBI_EN, GPC_MFP15) value and function mapping is as following list\n
15
1
read-write
GPC_MFP2
PC.2 Pin Function Selection\nBits PC2_I2SDI (ALT_MFP[7]) and GPC_MFP[2] determine the PC.2 function.\n(PC2_I2SDI, GPC_MFP2) value and function mapping is as following list.\n
2
1
read-write
GPC_MFP3
PC.3 Pin Function Selection\nBits PC3_I2SDO (ALT_MFP[8]) and GPC_MFP[3] determine the PC.3 function.\n(PC3_I2SDO, GPC_MFP3) value and function mapping is as following list.\n
3
1
read-write
GPC_MFP4
PC.4 Pin Function Selection\nBit GPC_MFP[4] determines the PC.4 function.\n
4
1
read-write
0
GPIO function is selected to the pin PC.4
#0
1
SPI0_MISO1 function is selected to the pin PC.4
#1
GPC_MFP5
PC.5 Pin Function Selection\nBit GPC_MFP[5] determines the PC.5 function.\n
5
1
read-write
0
GPIO function is selected to the pin PC.5
#0
1
SPI0_MOSI1 function is selected to the pin PC.5
#1
GPC_MFP6
PC.6 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]). PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] determine the PC.6 function.\n(EBI_EN, PC6_SC0CD, GPB_MFP6) value and function mapping is as following list.\n
6
1
read-write
GPC_MFP7
PC.7 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]), PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] determine the PC.7 function.\n(EBI_EN, PC7_SC1CD, GPC_MFP7) value and function mapping is as following list.\n
7
1
read-write
GPC_MFP8
PC.8 Pin Function Selection
Bits EBI_MCLK_EN (ALT_MFP[12]), EBI_EN (ALT_MFP[11]), GPC_MFP[8] determine the PC.8 function.
(EBI_MCLK_EN, EBI_EN, GPC_MFP8) value and function mapping is as following list.
8
1
read-write
GPC_MFP9
PC.9 Pin Function Selection\nBit GPC_MFP[9] determines the PC.9 function.\n
9
1
read-write
0
GPIO function is selected to the pin PC.9
#0
1
SPI1_CLK function is selected to the pin PC.9
#1
GPC_TYPEn
Trigger Function Selection\n
16
16
read-write
0
GPIOC[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOC[15:0] I/O input Schmitt Trigger function Enabled
1
GPD_MFP
GPD_MFP
GPIOD Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
GPD_MFP0
PD.0 Pin Function Selection\nBit GPD_MFP[0] determines the PD.0 function.\n
0
1
read-write
0
GPIOfunction is selected to the pin PD.0
#0
1
SPI2_SS0 function is selected to the pin PD.0
#1
GPD_MFP1
PD.1 Pin Function Selection\nBit GPD_MFP[1] determines the PD.1 function.\n
1
1
read-write
0
GPIO function is selected to the pin PD.1
#0
1
SPI2_CLK function is selected to the pin PD.1
#1
GPD_MFP10
PD.10 Pin Function Selection \nBit GPD_MFP[10] determines the PD.10 function.\n
10
1
read-write
0
GPIO function is selected to the pin PD.10
#0
1
SPI3_MISO0 function is selected to the pin PD.10
#1
GPD_MFP11
PD.11 Pin Function Selection\nBit GPD_MFP[11] determines the PD.11 function.\n
11
1
read-write
0
GPIO function is selected to the pin PD.11
#0
1
SPI3_MOSI0 function is selected to the pin PD.11
#1
GPD_MFP12
PD.12 Pin Function Selection \nBit GPD_MFP[12] determines the PD.12 function.\n
12
1
read-write
0
GPIO function is selected to the pin PD.12
#0
1
SPI3_MISO1 function is selected to the pin PD.12
#1
GPD_MFP13
PD.13 Pin Function Selection \nBit GPD_MFP[13] determines the PD.13 function.\n
13
1
read-write
0
GPIO function is selected to the pin PD.13
#0
1
SPI3_MOSI1 function is selected to the pin PD.13
#1
GPD_MFP14
PD.14 Pin Function Selection \nBits PD14_15_CAN1 (ALT_MFP2[0]) and GPD_MFP[14] determine the PD.14 function.\n(PD14_15_CAN1, GPD_MFP14) value and function mapping is as following list.\n
14
1
read-write
GPD_MFP15
PD.15 Pin Function Selection \nBits PD14_15_CAN1 (ALT_MFP2[0]) and GPD_MFP[15] determine the PD.15 function.\n(PD14_15_CAN1, GPD_MFP15) value and function mapping is as following list.\n
15
1
read-write
GPD_MFP2
PD.2 Pin Function Selection\nBit GPD_MFP[2] determines the PD.5 function.\n
2
1
read-write
0
GPIO function is selected to the pin PD.2
#0
1
SPI2_MISO0 function is selected to the pin PD.2
#1
GPD_MFP3
PD.3 Pin Function Selection\nBit GPD_MFP[3] determines the PD.3 function.\n
3
1
read-write
0
GPIO function is selected to the pin PD.3
#0
1
SPI2_MOSI0 function is selected to the pin PD.3
#1
GPD_MFP4
PD.4 Pin Function Selection \nBit GPD_MFP[4] determines the PD.4 function.\n
4
1
read-write
0
GPIO function is selected to the pin PD.4
#0
1
SPI2_MISO1 function is selected to the pin PD.4
#1
GPD_MFP5
PD.5 Pin Function Selection \nBit GPD_MFP[5] determines the PD.5 function.\n
5
1
read-write
0
GPIO function is selected to the pin PD.5
#0
1
SPI2_MOSI1 function is selected to the pin PD.5
#1
GPD_MFP6
PD.6 Pin Function Selection\nBit GPD_MFP[6] determines the PD.6 function.\n
6
1
read-write
0
The GPIO function is selected to the pin PD.6
#0
1
The CAN0_RXD function is selected to the pin PD.6
#1
GPD_MFP7
PD.7 Pin Function Selection \nBit GPD_MFP[7] determines the PD.5 function.\n
7
1
read-write
0
The GPIO function is selected to the pin PD.7
#0
1
The CAN0_TXD function is selected to the pin PD.7
#1
GPD_MFP8
PD.8 Pin Function Selection\nBit GPD_MFP[8] determines the PD.8 function.\n
8
1
read-write
0
GPIO function is selected to the pin PD.8
#0
1
SPI3_SS0 function is selected to the pin PD.8
#1
GPD_MFP9
PD.9 Pin Function Selection\nBit GPD_MFP[9] determines the PD.9 function.\n
9
1
read-write
0
GPIO is function is selected to the pin PD.9
#0
1
SPI3_CLK function is selected to the pin PD.9
#1
GPD_TYPEn
Trigger Function Selection\n
16
16
read-write
0
GPIOD[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOD[15:0] I/O input Schmitt Trigger function Enabled
1
GPE_MFP
GPE_MFP
GPIOE Multiple Function and Input Type Control Register
0x40
read-write
n
0x0
0x0
GPE_MFP0
PE.0 Pin Function Selection\nBit GPE_MFP[0] determines the PE.0 function.\n
0
1
read-write
0
GPIO function is selected to the pin PE.0
#0
1
PWM6 function is selected to the pin PE.0
#1
GPE_MFP1
PE.1 Pin Function Selection \nBit GPE_MFP[1] determines the PE.1 function.\n
1
1
read-write
0
GPIO function is selected to the pin PE.1
#0
1
PWM7 function is selected to the pin PE.1
#1
GPE_MFP5
PE.5 Pin Function Selection\nBits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list.\n
5
1
read-write
GPE_TYPEn
Trigger Function Selection\n
16
16
read-write
0
GPIOE[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOE[15:0] I/O input Schmitt Trigger function Enabled
1
GPF_MFP
GPF_MFP
GPIOF Multiple Function and Input Type Control Register
0x44
read-write
n
0x0
0x0
GPF_MFP0
PF.0 Pin Function Selection\nBit GPF_MFP[0] determines the PF.0 function\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27]).
0
1
read-write
0
GPIO function is selected to the pin PF.0
#0
1
XT1_OUT function is selected to the pin PF.0
#1
GPF_MFP1
PF.1 Pin Function Selection \nBit GPF_MFP[1] determines the PF.1 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27]).
1
1
read-write
0
GPIO function is selected to the pin PF.1
#0
1
XT1_IN function is selected to the pin PF.1
#1
GPF_MFP2
PF.2 Pin Function Selection\nBit GPF_MFP[2] determines the PF.2 function.\n
2
1
read-write
0
GPIO function is selected to the pin PF.2
#0
1
PS/2_DAT function is selected to the pin PF.2
#1
GPF_MFP3
PF.3 Pin Function Selection \nBit GPF_MFP[3] determines the PF.3 function.\n
3
1
read-write
0
GPIO function is selected to the pin PF.3
#0
1
PS/2_CLK function is selected to the pin PF.3
#1
GPF_TYPEn
Trigger Function Selection\n
16
4
read-write
0
GPIOF[3:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOF[3:0] I/O input Schmitt Trigger function Enabled
1
IPRSTC1
IPRSTC1
Peripheral Reset Control Register 1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP One-Shot Reset (Write Protect)
Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload.
For the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
CHIP normal operation
#0
1
CHIP one-shot reset
#1
CPU_RST
CPU Kernel One-Shot Reset (Write Protect)
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
1
1
read-write
0
CPU normal operation
#0
1
CPU one-shot reset
#1
EBI_RST
EBI Controller Reset (Write-protection Bit)
Set this bit to 1 will generate a reset signal to the EBI. User need to set this bit to 0 to release from the reset state.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
3
1
read-write
0
EBI controller normal operation
#0
1
EBI controller reset
#1
PDMA_RST
PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
Note1: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
Note2: Setting PDMA_RST bit to 1 will generate asynchronous reset signal to PDMA module. Users need to set PDMA_RST to 0 to release PDMA module from reset state.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRSTC2
IPRSTC2
Peripheral Reset Control Register 2
0xC
read-write
n
0x0
0x0
ACMP_RST
Analog Comparator Controller Reset\n
22
1
read-write
0
Analog Comparator controller normal operation
#0
1
Analog Comparator controller reset
#1
ADC_RST
ADC Controller Reset\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
CAN0_RST
CAN0 Controller Reset\n
24
1
read-write
0
CAN0 controller normal operation
#0
1
CAN0 controller reset
#1
CAN1_RST
CAN1 Controller Reset\n
25
1
read-write
0
CAN1 controller normal operation
#0
1
CAN1 controller reset
#1
GPIO_RST
GPIO Controller Reset\n
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0_RST
I2C0 Controller Reset\n
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1_RST
I2C1 Controller Reset\n
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2S_RST
I2S Controller Reset\n
29
1
read-write
0
I2S controller normal operation
#0
1
I2S controller reset
#1
PS2_RST
PS/2 Controller Reset\n
23
1
read-write
0
PS/2 controller normal operation
#0
1
PS/2 controller reset
#1
PWM03_RST
PWM03 Controller Reset\n
20
1
read-write
0
PWM03 controller normal operation
#0
1
PWM03 controller reset
#1
PWM47_RST
PWM47 Controller Reset\n
21
1
read-write
0
PWM47 controller normal operation
#0
1
PWM47 controller reset
#1
SPI0_RST
SPI0 Controller Reset\n
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1_RST
SPI1 Controller Reset\n
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
SPI2_RST
SPI2 Controller Reset \n
14
1
read-write
0
SPI2 controller normal operation
#0
1
SPI2 controller reset
#1
SPI3_RST
SPI3 Controller Reset \n
15
1
read-write
0
SPI3 controller normal operation
#0
1
SPI3 controller reset
#1
TMR0_RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1_RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2_RST
Timer2 Controller Reset\n
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3_RST
Timer3 Controller Reset\n
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0_RST
UART0 Controller Reset\n
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1_RST
UART1 Controller Reset\n
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2_RST
UART2 Controller Reset \n
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
USBD_RST
USB Device Controller Reset\n
27
1
read-write
0
USB device controller normal operation
#0
1
USB device controller reset
#1
IPRSTC3
IPRSTC3
Peripheral Reset Control Register 3
0x10
read-write
n
0x0
0x0
SC0_RST
SC0 Controller Reset\n
0
1
read-write
0
SC0 controller normal operation
#0
1
SC0 controller reset
#1
SC1_RST
SC1 Controller Reset\n
1
1
read-write
0
SC1 controller normal operation
#0
1
SC1 controller reset
#1
SC2_RST
SC2 Controller Reset\n
2
1
read-write
0
SC2 controller normal operation
#0
1
SC2 controller reset
#1
IRCTRIMCTL
IRCTRIMCTL
IRC Trim Control Register
0x80
read-write
n
0x0
0x0
CLKERR_STOP_EN
Clock Error Stop Enable Bit\n
8
1
read-write
0
The trim operation is kept going if clock is inaccuracy
#0
1
The trim operation is stopped if clock is inaccuracy
#1
TRIM_LOOP
Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clocks in.\nFor example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.\n
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks
#00
1
Trim value calculation is based on average difference in 8 clocks
#01
2
Trim value calculation is based on average difference in 16 clocks
#10
3
Trim value calculation is based on average difference in 32 clocks
#11
TRIM_RETRY_CNT
Trim Value Update Limitation Count\nThe field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.\n
6
2
read-write
0
Trim retry count limitation is 64
#00
1
Trim retry count limitation is 128
#01
2
Trim retry count limitation is 256
#10
3
Trim retry count limitation is 512
#11
TRIM_SEL
Trim Frequency Selection\nThis field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically.\nIf no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.\nDuring auto trim operation, if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached, this field will be cleared to 00 automatically.\n
0
2
read-write
0
HIRC auto trim function Disabled
#00
1
HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz
#01
2
HIRC auto trim function Enabled and HIRC trimmed to 24 MHz
#10
3
Reserved
#11
IRCTRIMIEN
IRCTRIMIEN
IRC Trim Interrupt Enable Register
0x84
read-write
n
0x0
0x0
CLKERR_IEN
Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERR_INT (IRCTRIMINT[2]) is set during auto trim operation. An interrupt will be triggered to notify the clock frequency is inaccuracy.\n
2
1
read-write
0
CLKERR_INT (IRCTRIMINT[2]) status to trigger an interrupt to CPU Disabled
#0
1
CLKERR_INT (IRCTRIMINT[2]) status to trigger an interrupt to CPU Enabled
#1
TRIM_FAIL_IEN
Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTRIMCTL[1:0]).\nIf this bit is high and TRIM_FAIL_INT (IRCTRIMINT[1]) is set during auto trim operation. An interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
1
1
read-write
0
TRIM_FAIL_INT (IRCTRIMINT[1]) status to trigger an interrupt to CPU Disabled
#0
1
TRIM_FAIL_INT (IRCTRIMINT[1]) status to trigger an interrupt to CPU Enabled
#1
IRCTRIMINT
IRCTRIMINT
IRC Trim Interrupt Status Register
0x88
read-write
n
0x0
0x0
CLKERR_INT
Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CLKERR_STOP_EN (IRCTRIMCTL[8]) is set to 1.\nIf this bit is set and CLKERR_IEN (IRCTRIMIEN [2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
2
1
read-write
0
Clock frequency is accurate
#0
1
Clock frequency is inaccurate
#1
FREQ_LOCK
HIRC Frequency Lock Status\nThis bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
0
1
read-write
TRIM_FAIL_INT
Trim Failure Interrupt Status\nThis bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN (IRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
1
1
read-write
0
Trim value update limitation count did not reach
#0
1
Trim value update limitation count reached and internal 22.1184 MHz high speed oscillator frequency was still not locked
#1
PDID
PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number\nThis register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
PORCR
PORCR
Power-on-reset Controller Register
0x24
read-write
n
0x0
0x0
POR_DIS_CODE
Power-On-Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog Timer reset, Window Watchdog Timer reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function
Note: This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
16
read-write
REGWRPROT
REGWRPROT
Register Write Protection Register
0x100
read-write
n
0x0
0x0
REGWRPROT
Register Write-Protection Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
Register Write-Protection Disable Index (Read Only)
The Protected registers are:
IPRSTC1: address 0x5000_0008
BODCR: address 0x5000_0018
PORCR: address 0x5000_0024
PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear)
APBCLK bit[0]: address 0x5000_0208 (bit[0] is Watchdog Timer clock enable)
CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source selection)
CLKSEL1 bit[1:0]: address 0x5000_0214 (for Watchdog Timer clock source selection)
NMI_SEL bit[8]: address 0x5000_0380 (for NMI_EN interrupt enable)
ISPCON: address 0x5000_C000 (Flash ISP Control register)
ISPTRG: address 0x5000_C010 (ISP Trigger Control register)
WTCR: address 0x4000_4000
FATCON: address 0x5000_C018
Note: The bits which are write-protected will be noted as (Write Protect) beside the description.
0
8
read-write
0
Write-protection is enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection is disabled for writing protected registers
1
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
Brown-Out Detector Reset Flag
The RSTS_BOD flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
RSTS_CPU
CPU Reset Flag\nThe RSTS_CPU flag Is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 To reset Cortex-M0 kernel and flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST(IPRSTC1[1]) to 1
#1
RSTS_LVR
Low Voltage Reset Flag
The RSTS_LVR flag is set by the Reset Signal from the Low-Voltage-Reset controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
The LVR controller had issued the reset signal to reset the system
#1
RSTS_POR
Power-On Reset Flag
The RSTS_POR Flag is set by the Reset Signal from the Power-On Reset (POR) vontroller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIP_RST (IPRSTC1[0])
#0
1
Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]) had issued the reset signal to reset the system
#1
RSTS_RESET
Reset Pin Reset Flag
The RSTS_RESET flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
The Pin nRESET had issued the reset signal to reset the system
#1
RSTS_SYS
SYS Reset Flag
The RSTS_SYS flag Is set by the Reset Signal from the Cortex-M0 kernel to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel
#1
RSTS_WDT
Watchdog Timer Reset Flag
The RSTS_WDT flag is set by the Reset Signal from the watchdog timer or window watchdog timer to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register WTRF(WTCR[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDTSR) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
TEMPCR
TEMPCR
Temperature Sensor Control Register
0x1C
read-write
n
0x0
0x0
VTEMP_EN
Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detail ADC conversion functional description.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x24
registers
n
0x180
0x4
registers
n
0x200
0x150
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
DBNCECON
DBNCECON
External Interrupt De-bounce Control
0x180
read-write
n
0x0
0x0
DBCLKSEL
De-Bounce Sampling Cycle Selection\n
0
4
read-write
DBCLKSRC
De-Bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz low speed oscillator
#1
ICLK_ON
Interrupt Clock On Mode\nIt is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
GPIOA_DBEN
GPIOA_DBEN
GPIO Port A De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
0
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN1
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
1
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN10
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
10
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN11
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
11
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN12
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
12
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN13
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
13
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN14
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
14
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN15
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
15
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN2
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
2
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN3
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
3
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN4
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
4
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN5
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
5
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN6
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
6
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN7
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
7
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN8
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
8
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN9
Port [A/B/C/D/E/F] Input Signal De-Bounce Enable Bit\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
9
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
GPIOA_DMASK
GPIOA_DMASK
GPIO Port A Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
0
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK1
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
1
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK10
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
10
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK11
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
11
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK12
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
12
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK13
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
13
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK14
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
14
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK15
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
15
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK2
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
2
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK3
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
3
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK4
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
4
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK5
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
5
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK6
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
6
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK7
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
7
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK8
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
8
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK9
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
9
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
GPIOA_DOUT
GPIOA_DOUT
GPIO Port A Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
0
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
1
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
10
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
11
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
12
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
13
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
14
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
15
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
2
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
3
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
4
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
5
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
6
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
7
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
8
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or quasi-bidirectional mode.\n
9
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
GPIOA_IEN
GPIOA_IEN
GPIO Port A Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
0
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN1
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
1
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN10
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
10
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN11
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
11
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN12
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
12
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN13
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
13
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN14
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
14
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN15
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
15
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN2
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
2
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN3
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
3
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN4
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
4
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN5
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
5
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN6
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
6
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN7
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
7
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN8
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
8
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN9
Port [A/B/C/D/E/F] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen setting the IF_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt.\n
9
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IR_EN0
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
16
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN1
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
17
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN10
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
26
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN11
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
27
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN12
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
28
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN13
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
29
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN14
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
30
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN15
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
31
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN2
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
18
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN3
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
19
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN4
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
20
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN5
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
21
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN6
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
22
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN7
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
23
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN8
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
24
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN9
Port [A/B/C/D/E/F] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge trigger, the input PIN[n] state change from "low-to-high" will generate the interrupt.\n
25
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
GPIOA_IMD
GPIOA_IMD
GPIO Port A Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD1
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD10
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD11
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD12
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD13
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD14
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD15
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD2
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD3
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD4
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD5
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD6
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD7
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD8
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD9
Port [A/B/C/D/E/F] Edge Or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
GPIOA_ISRC
GPIOA_ISRC
GPIO Port A Interrupt Source Flag
0x20
read-write
n
0x0
0x0
ISRC0
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
0
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC1
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
1
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC10
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
10
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC11
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
11
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC12
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
12
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC13
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
13
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC14
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
14
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC15
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
15
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC2
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
2
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC3
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
3
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC4
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
4
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC5
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
5
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC6
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
6
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC7
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
7
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC8
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
8
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC9
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
9
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
GPIOA_OFFD
GPIOA_OFFD
GPIO Port A Pin Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
OFFD
GPIOx Pin[N] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid current leakage.\n
16
16
read-write
0
I/O digital input path Enabled
0
1
I/O digital input path Disabled (digital input tied to low)
1
GPIOA_PIN
GPIOA_PIN
GPIO Port A Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
0
1
read-only
PIN1
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
1
1
read-only
PIN10
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
10
1
read-only
PIN11
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
11
1
read-only
PIN12
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
12
1
read-only
PIN13
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
13
1
read-only
PIN14
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
14
1
read-only
PIN15
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
15
1
read-only
PIN2
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
2
1
read-only
PIN3
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
3
1
read-only
PIN4
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
4
1
read-only
PIN5
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
5
1
read-only
PIN6
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
6
1
read-only
PIN7
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
7
1
read-only
PIN8
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
8
1
read-only
PIN9
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
9
1
read-only
GPIOA_PMD
GPIOA_PMD
GPIO Port A Pin I/O Mode Control
0x0
read-write
n
0x0
0x0
PMD0
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Quasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GPIOB_DBEN
GPIOB_DBEN
GPIO Port B De-bounce Enable
0x54
read-write
n
0x0
0x0
GPIOB_DMASK
GPIOB_DMASK
GPIO Port B Data Output Write Mask
0x4C
read-write
n
0x0
0x0
GPIOB_DOUT
GPIOB_DOUT
GPIO Port B Data Output Value
0x48
read-write
n
0x0
0x0
GPIOB_IEN
GPIOB_IEN
GPIO Port B Interrupt Enable
0x5C
read-write
n
0x0
0x0
GPIOB_IMD
GPIOB_IMD
GPIO Port B Interrupt Mode Control
0x58
read-write
n
0x0
0x0
GPIOB_ISRC
GPIOB_ISRC
GPIO Port B Interrupt Source Flag
0x60
read-write
n
0x0
0x0
GPIOB_OFFD
GPIOB_OFFD
GPIO Port B Pin Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
GPIOB_PIN
GPIOB_PIN
GPIO Port B Pin Value
0x50
read-write
n
0x0
0x0
GPIOB_PMD
GPIOB_PMD
GPIO Port B Pin I/O Mode Control
0x40
read-write
n
0x0
0x0
GPIOC_DBEN
GPIOC_DBEN
GPIO Port C De-bounce Enable
0x94
read-write
n
0x0
0x0
GPIOC_DMASK
GPIOC_DMASK
GPIO Port C Data Output Write Mask
0x8C
read-write
n
0x0
0x0
GPIOC_DOUT
GPIOC_DOUT
GPIO Port C Data Output Value
0x88
read-write
n
0x0
0x0
GPIOC_IEN
GPIOC_IEN
GPIO Port C Interrupt Enable
0x9C
read-write
n
0x0
0x0
GPIOC_IMD
GPIOC_IMD
GPIO Port C Interrupt Mode Control
0x98
read-write
n
0x0
0x0
GPIOC_ISRC
GPIOC_ISRC
GPIO Port C Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
GPIOC_OFFD
GPIOC_OFFD
GPIO Port C Pin Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
GPIOC_PIN
GPIOC_PIN
GPIO Port C Pin Value
0x90
read-write
n
0x0
0x0
GPIOC_PMD
GPIOC_PMD
GPIO Port C Pin I/O Mode Control
0x80
read-write
n
0x0
0x0
GPIOD_DBEN
GPIOD_DBEN
GPIO Port D De-bounce Enable
0xD4
read-write
n
0x0
0x0
GPIOD_DMASK
GPIOD_DMASK
GPIO Port D Data Output Write Mask
0xCC
read-write
n
0x0
0x0
GPIOD_DOUT
GPIOD_DOUT
GPIO Port D Data Output Value
0xC8
read-write
n
0x0
0x0
GPIOD_IEN
GPIOD_IEN
GPIO Port D Interrupt Enable
0xDC
read-write
n
0x0
0x0
GPIOD_IMD
GPIOD_IMD
GPIO Port D Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
GPIOD_ISRC
GPIOD_ISRC
GPIO Port D Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
GPIOD_OFFD
GPIOD_OFFD
GPIO Port D Pin Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
GPIOD_PIN
GPIOD_PIN
GPIO Port D Pin Value
0xD0
read-write
n
0x0
0x0
GPIOD_PMD
GPIOD_PMD
GPIO Port D Pin I/O Mode Control
0xC0
read-write
n
0x0
0x0
GPIOE_DBEN
GPIOE_DBEN
GPIO Port E De-bounce Enable
0x114
read-write
n
0x0
0x0
GPIOE_DMASK
GPIOE_DMASK
GPIO Port E Data Output Write Mask
0x10C
read-write
n
0x0
0x0
GPIOE_DOUT
GPIOE_DOUT
GPIO Port E Data Output Value
0x108
read-write
n
0x0
0x0
GPIOE_IEN
GPIOE_IEN
GPIO Port E Interrupt Enable
0x11C
read-write
n
0x0
0x0
GPIOE_IMD
GPIOE_IMD
GPIO Port E Interrupt Mode Control
0x118
read-write
n
0x0
0x0
GPIOE_ISRC
GPIOE_ISRC
GPIO Port E Interrupt Source Flag
0x120
read-write
n
0x0
0x0
GPIOE_OFFD
GPIOE_OFFD
GPIO Port E Pin Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
GPIOE_PIN
GPIOE_PIN
GPIO Port E Pin Value
0x110
read-write
n
0x0
0x0
GPIOE_PMD
GPIOE_PMD
GPIO Port E Pin I/O Mode Control
0x100
read-write
n
0x0
0x0
GPIOF_DBEN
GPIOF_DBEN
GPIO Port F De-bounce Enable
0x154
read-write
n
0x0
0x0
GPIOF_DMASK
GPIOF_DMASK
GPIO Port F Data Output Write Mask
0x14C
read-write
n
0x0
0x0
GPIOF_DOUT
GPIOF_DOUT
GPIO Port F Data Output Value
0x148
read-write
n
0x0
0x0
GPIOF_IEN
GPIOF_IEN
GPIO Port F Interrupt Enable
0x15C
read-write
n
0x0
0x0
GPIOF_IMD
GPIOF_IMD
GPIO Port F Interrupt Mode Control
0x158
read-write
n
0x0
0x0
GPIOF_ISRC
GPIOF_ISRC
GPIO Port F Interrupt Source Flag
0x160
read-write
n
0x0
0x0
GPIOF_OFFD
GPIOF_OFFD
GPIO Port F Pin Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
GPIOF_PIN
GPIOF_PIN
GPIO Port F Pin Value
0x150
read-write
n
0x0
0x0
GPIOF_PMD
GPIOF_PMD
GPIO Port F Pin I/O Mode Control
0x140
read-write
n
0x0
0x0
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output
0x200
read-write
n
0x0
0x0
Pxn_PDIO
GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0], read PA0_PDIO will return the value of GPIOA_PIN[0]\nNote: The write operation will not be affected by register GPIOx_DMASK
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output
0x228
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output
0x22C
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output
0x230
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output
0x234
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output
0x238
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output
0x23C
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output
0x204
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output
0x208
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output
0x20C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output
0x210
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output
0x214
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output
0x218
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output
0x21C
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output
0x220
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output
0x224
read-write
n
0x0
0x0
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output
0x240
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output
0x268
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output
0x26C
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output
0x270
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output
0x274
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output
0x278
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output
0x27C
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output
0x244
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output
0x248
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output
0x24C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output
0x250
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output
0x254
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output
0x258
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output
0x25C
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output
0x260
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output
0x264
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output
0x280
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output
0x2A8
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output
0x2AC
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output
0x2B0
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output
0x2B4
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output
0x2B8
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output
0x2BC
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output
0x284
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output
0x288
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output
0x28C
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output
0x290
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output
0x294
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output
0x298
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output
0x29C
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output
0x2A0
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output
0x2A4
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output
0x2C0
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output
0x2E8
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output
0x2EC
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output
0x2F0
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output
0x2F4
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output
0x2F8
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output
0x2FC
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output
0x2C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output
0x2C8
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output
0x2CC
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output
0x2D0
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output
0x2D4
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output
0x2D8
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output
0x2DC
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output
0x2E0
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output
0x2E4
read-write
n
0x0
0x0
PE0_PDIO
PE0_PDIO
GPIO PE.n Pin Data Input/Output
0x300
read-write
n
0x0
0x0
PE10_PDIO
PE10_PDIO
GPIO PE.n Pin Data Input/Output
0x328
read-write
n
0x0
0x0
PE11_PDIO
PE11_PDIO
GPIO PE.n Pin Data Input/Output
0x32C
read-write
n
0x0
0x0
PE12_PDIO
PE12_PDIO
GPIO PE.n Pin Data Input/Output
0x330
read-write
n
0x0
0x0
PE13_PDIO
PE13_PDIO
GPIO PE.n Pin Data Input/Output
0x334
read-write
n
0x0
0x0
PE14_PDIO
PE14_PDIO
GPIO PE.n Pin Data Input/Output
0x338
read-write
n
0x0
0x0
PE15_PDIO
PE15_PDIO
GPIO PE.n Pin Data Input/Output
0x33C
read-write
n
0x0
0x0
PE1_PDIO
PE1_PDIO
GPIO PE.n Pin Data Input/Output
0x304
read-write
n
0x0
0x0
PE2_PDIO
PE2_PDIO
GPIO PE.n Pin Data Input/Output
0x308
read-write
n
0x0
0x0
PE3_PDIO
PE3_PDIO
GPIO PE.n Pin Data Input/Output
0x30C
read-write
n
0x0
0x0
PE4_PDIO
PE4_PDIO
GPIO PE.n Pin Data Input/Output
0x310
read-write
n
0x0
0x0
PE5_PDIO
PE5_PDIO
GPIO PE.n Pin Data Input/Output
0x314
read-write
n
0x0
0x0
PE6_PDIO
PE6_PDIO
GPIO PE.n Pin Data Input/Output
0x318
read-write
n
0x0
0x0
PE7_PDIO
PE7_PDIO
GPIO PE.n Pin Data Input/Output
0x31C
read-write
n
0x0
0x0
PE8_PDIO
PE8_PDIO
GPIO PE.n Pin Data Input/Output
0x320
read-write
n
0x0
0x0
PE9_PDIO
PE9_PDIO
GPIO PE.n Pin Data Input/Output
0x324
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output
0x340
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output
0x344
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output
0x348
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output
0x34C
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
EI
Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThere are 26 possible status codes. \nWhen I2CSTATUS contains 0xF8, no serial interrupt is requested. \n In addition, states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
0
8
read-only
I2CTOC
I2CTOC
I2C Time-out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
ENTI
Time-Out Counter Enable Bit \nWhen Enabled, the 14-bit time-out counter will start counting when SI(I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TIF
Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI(I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
Chip is not woken-up from Power-down mode by I2C
#0
1
Chip is woken-up from Power-down mode by I2C
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nThis field is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
EI
Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThere are 26 possible status codes. \nWhen I2CSTATUS contains 0xF8, no serial interrupt is requested. \n In addition, states 0x00 stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
0
8
read-only
I2CTOC
I2CTOC
I2C Time-out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
ENTI
Time-Out Counter Enable Bit \nWhen Enabled, the 14-bit time-out counter will start counting when SI(I2CON[3]) is clear. Setting flag SI SI(I2CON[3]) to high will reset counter and re-start up counting after SI SI(I2CON[3]) is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TIF
Time-Out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit EI(I2CON[7]) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
Chip is not woken-up from Power-down mode by I2C
#0
1
Chip is woken-up from Power-down mode by I2C
#1
I2S
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
I2SCLKDIV
I2SCLKDIV
I2S Clock Divider Control Register
0x4
read-write
n
0x0
0x0
BCLK_DIV
Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The bit clock rate, F_BCLK, is determined by the following expression.\n
8
8
read-write
MCLK_DIV
Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The master clock rate, F_MCLK, is determined by the following expressions.\nF_I2SCLK is the frequency of I2S peripheral clock.\nIn general, the master clock rate is 256 times sampling clock rate.
0
3
read-write
I2SCON
I2SCON
I2S Control Register
0x0
read-write
n
0x0
0x0
CLR_RXFIFO
Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically. Returns 0 on read.
19
1
read-write
CLR_TXFIFO
Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TX_LEVEL[3:0] returns to 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically. Returns 0 on read.
18
1
read-write
FORMAT
Data Format\n
7
1
read-write
0
I2S data format
#0
1
MSB justified data format
#1
I2SEN
I2S Controller Enable Bit\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
LCHZCEN
Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
17
1
read-write
0
Left channel zero cross detection Disabled
#0
1
Left channel zero cross detection Enabled
#1
MCLKEN
Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.\n
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data\n
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit\n
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Send zero on transmit channel
#1
RCHZCEN
Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
16
1
read-write
0
Right channel zero cross detection Disabled
#0
1
Right channel zero cross detection Enabled
#1
RXDMA
Receive DMA Enable Bit\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
21
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXEN
Receive Enable Bit\n
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXLCH
Receive Left Channel Enable Bit\n
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RXTH
Receive FIFO Threshold Level\nWhen the count of received data word(s) in buffer is equal to or higher than threshold level, RXTHF (I2SSTATUS[10]) will be set.\n
12
3
read-write
0
1 word data in receive FIFO
#000
1
2 word data in receive FIFO
#001
2
3 word data in receive FIFO
#010
3
4 word data in receive FIFO
#011
4
5 word data in receive FIFO
#100
5
6 word data in receive FIFO
#101
6
7 word data in receive FIFO
#110
7
8 word data in receive FIFO
#111
SLAVE
Slave Mode\nI2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC230/240 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXDMA
Transmit DMA Enable Bit\nWhen TX DMA is enabled, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
20
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
TXEN
Transmit Enable Bit\n
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
TXTH
Transmit FIFO Threshold Level\nIf the count of remaining data word (32 bits) in transmit FIFO is equal to or less than threshold level then TXTHF (I2SSTATUS[18]) is set.\n
9
3
read-write
0
0 word data in transmit FIFO
#000
1
1 word data in transmit FIFO
#001
2
2 words data in transmit FIFO
#010
3
3 words data in transmit FIFO
#011
4
4 words data in transmit FIFO
#100
5
5 words data in transmit FIFO
#101
6
6 words data in transmit FIFO
#110
7
7 words data in transmit FIFO
#111
WORDWIDTH
Word Width\n
4
2
read-write
0
data is 8-bit word
#00
1
data is 16-bit word
#01
2
data is 24-bit word
#10
3
data is 32-bit word
#11
I2SIE
I2SIE
I2S Interrupt Enable Register
0x8
read-write
n
0x0
0x0
LZCIE
Left Channel Zero-Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero-cross event is detected.\n
12
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVFIE
Receive FIFO Overflow Interrupt Enable Bit\n
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIE
Receive FIFO Threshold Level Interrupt Enable Bit\nWhen the count of data words in receive FIFO is equal to or higher than RXTH (I2SCON[14:12]) and this bit is set to 1, receive FIFO threshold level interrupt will be asserted.\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDFIE
Receive FIFO Underflow Interrupt Enable Bit\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RZCIE
Right Channel Zero-Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero-cross event is detected.\n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVFIE
Transmit FIFO Overflow Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIE
Transmit FIFO Threshold Level Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and the count of data words in transmit FIFO is less than TXTH (I2SCON[11:9]).\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDFIE
Transmit FIFO Underflow Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1.\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
I2SRXFIFO
I2SRXFIFO
I2S Receive FIFO Register
0x14
read-only
n
0x0
0x0
RXFIFO
Receive FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data receive. Read this register to get data of receive FIFO. The remaining data word number is indicated by RX_LEVEL (I2SSTATUS[27:24]).
0
32
read-only
I2SSTATUS
I2SSTATUS
I2S Status Register
0xC
read-write
n
0x0
0x0
I2SINT
I2S Interrupt Flag\nThis bit is wire-OR of I2STXINT and I2SRXINT bits.\nNote: This bit is read only.
0
1
read-write
0
No I2S interrupt
#0
1
I2S interrupt
#1
I2SRXINT
I2S Receive Interrupt\nNote: This bit is read only.
1
1
read-write
0
No receive interrupt
#0
1
Receive interrupt
#1
I2STXINT
I2S Transmit Interrupt\nNote: This bit is read only.
2
1
read-write
0
No transmit interrupt
#0
1
Transmit interrupt
#1
LZCF
Left Channel Zero-Cross Flag\nIt indicates the sign bit of left channel sample data is changed or all data bits are 0.\nNote: Write 1 to clear this bit to 0.
23
1
read-write
0
No zero-cross
#0
1
Left channel zero-cross event is detected
#1
RIGHT
Right Channel\nThis bit indicates current transmit data is belong to which channel\nNote: This bit is read only.
3
1
read-write
0
Left channel
#0
1
Right channel
#1
RXEMPTY
Receive FIFO Empty\nThis bit reflects the count of data in receive FIFO is 0\nNote: This bit is read only.
12
1
read-write
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full\nThis bit reflects the count of data in receive FIFO is 8\nNote: This bit is read only.
11
1
read-write
0
Not full
#0
1
Full
#1
RXOVF
Receive FIFO Overflow Flag\nWhen receive FIFO is full and hardware attempt to write data to receive FIFO, this bit will be set to 1, data in 1st buffer will be overwrote.\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No overflow
#0
1
Overflow
#1
RXTHF
Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or larger than threshold value set in RXTH (I2SCON[14:12]). The RXTHF bit becomes to 1. It keeps at 1 till RX_LEVEL (I2SSTATUS[27:24]) is less than RXTH.\nNote: This bit is read only.
10
1
read-write
0
Data word(s) in FIFO is less than threshold level
#0
1
Data word(s) in FIFO is equal to or larger than threshold level
#1
RXUDF
Receive FIFO Underflow Flag\nUnderflow event will occur if read the empty receive FIFO.\nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
No underflow event occurred
#0
1
Underflow
#1
RX_LEVEL
Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
24
4
read-write
0
No data
#0000
1
1 word in receive FIFO
#0001
8
8 words in receive FIFO
#1000
RZCF
Right Channel Zero-Cross Flag\nIt indicates the sign bit of right channel sample data is changed or all data bits are 0.\nNote: Write 1 to clear this bit to 0.
22
1
read-write
0
No zero-cross
#0
1
Right channel zero-cross event is detected
#1
TXBUSY
Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.\nNote: This bit is read only.
21
1
read-write
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is not empty
#1
TXEMPTY
Transmit FIFO Empty\nThis bit reflects data word number in transmit FIFO is 0\nNote: This bit is read only.
20
1
read-write
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full\nThis bit reflects data word number in transmit FIFO is 8\nNote: This bit is read only.
19
1
read-write
0
Not full
#0
1
Full
#1
TXOVF
Transmit FIFO Overflow Flag\nThis bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full.\nNote: Write 1 to clear this bit to 0.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHF
Transmit FIFO Threshold Flag\nWhen the count of data stored in transmit-FIFO is equal to or less than threshold value set in TXTH (I2SCON[11:9]). The TXTHF bit becomes to 1. It keeps at 1 till TX_LEVEL (I2SSTATUS[31:28]) is larger than TXTH.\nNote: This bit is read only.
18
1
read-write
0
Data word(s) in FIFO is larger than threshold level
#0
1
Data word(s) in FIFO is equal to or less than threshold level
#1
TXUDF
Transmit FIFO Underflow Flag\nIf transmit FIFO is empty and hardware reads data from transmit FIFO. This bit will be set to 1.\nNote: Software can write 1 to clear this bit to 0.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX_LEVEL
Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
28
4
read-write
0
No data
#0000
1
1 word in transmit FIFO
#0001
8
8 words in transmit FIFO
#1000
I2STXFIFO
I2STXFIFO
I2S Transmit FIFO Register
0x10
write-only
n
0x0
0x0
TXFIFO
Transmit FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmission. The remaining word number is indicated by TX_LEVEL (I2SSTATUS[31:28])
0
32
write-only
INT
INT Register Map
INT
0x0
0x0
0x8C
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity
0x0
read-only
n
0x0
0x0
INT_SRC
Interrupt Source\nDefine the interrupt sources for interrupt event.
0
4
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (TMR2) Interrupt Source Identity
0x28
read-write
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
IRQ11 (TMR3) Interrupt Source Identity
0x2C
read-write
n
0x0
0x0
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0/2) Interrupt Source Identity
0x30
read-write
n
0x0
0x0
IRQ13_SRC
IRQ13_SRC
IRQ13 (UART1) Interrupt Source Identity
0x34
read-write
n
0x0
0x0
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) Interrupt Source Identity
0x38
read-write
n
0x0
0x0
IRQ15_SRC
IRQ15_SRC
IRQ15 (SPI1) Interrupt Source Identity
0x3C
read-write
n
0x0
0x0
IRQ16_SRC
IRQ16_SRC
IRQ16 (SPI2) Interrupt Source Identity
0x40
read-write
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (SPI3) Interrupt Source Identity
0x44
read-write
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) Interrupt Source Identity
0x48
read-write
n
0x0
0x0
IRQ19_SRC
IRQ19_SRC
IRQ19 (I2C1) Interrupt Source Identity
0x4C
read-write
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity
0x4
read-write
n
0x0
0x0
IRQ20_SRC
IRQ20_SRC
Reserved
0x50
read-write
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
Reserved
0x54
read-write
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
IRQ22 (SC0/1/2) Interrupt Source Identity
0x58
read-write
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
IRQ23 (USBD) Interrupt Source Identity
0x5C
read-write
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
IRQ24 (PS/2) Interrupt Source Identity
0x60
read-write
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity
0x64
read-write
n
0x0
0x0
IRQ26_SRC
IRQ26_SRC
IRQ26 (PDMA) Interrupt Source Identity
0x68
read-write
n
0x0
0x0
IRQ27_SRC
IRQ27_SRC
IRQ27 (I2S) Interrupt Source Identity
0x6C
read-write
n
0x0
0x0
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) Interrupt Source Identity
0x70
read-write
n
0x0
0x0
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity
0x74
read-write
n
0x0
0x0
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity
0x8
read-write
n
0x0
0x0
IRQ30_SRC
IRQ30_SRC
IRQ30 (IRC) Interrupt Source Identity
0x78
read-write
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
IRQ31 (RTC) Interrupt Source Identity
0x7C
read-write
n
0x0
0x0
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity
0xC
read-write
n
0x0
0x0
IRQ4_SRC
IRQ4_SRC
IRQ4 (GPA/B) Interrupt Source Identity
0x10
read-write
n
0x0
0x0
IRQ5_SRC
IRQ5_SRC
IRQ5 (GPC/D/E/F) Interrupt Source Identity
0x14
read-write
n
0x0
0x0
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWMA) Interrupt Source Identity
0x18
read-write
n
0x0
0x0
IRQ7_SRC
IRQ7_SRC
IRQ7 (PWMB) Interrupt Source Identity
0x1C
read-write
n
0x0
0x0
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity
0x20
read-write
n
0x0
0x0
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity
0x24
read-write
n
0x0
0x0
MCU_IRQ
MCU_IRQ
MCU Interrupt Request Source Register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0: has no effect
0
32
read-write
MCU_IRQCR
MCU_IRQCR
MCU Interrupt Request Control Register
0x88
read-write
n
0x0
0x0
FAST_IRQ
Fast IRQ Latency Enable Bit\n
0
1
read-write
0
MCU IRQ latency is fixed at 13 clock cycles of HCLK, MCU will enter IRQ handler after this fixed latency when interrupt happened
#0
1
MCU IRQ latency will not fixed, MCU will enter IRQ handler as soon as possible when interrupt happened
#1
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMI_EN
NMI Interrupt Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
8
1
read-write
0
NMI interrupt Disabled
#0
1
NMI interrupt Enabled
#1
NMI_SEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
0
5
read-write
PDMA_CH0
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH1
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH2
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH3
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH4
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH5
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH6
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH7
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_CH8
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCR0
PDMA_BCR0
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
0
16
read-write
PDMA_BCR1
PDMA_BCR1
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR2
PDMA_BCR2
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR3
PDMA_BCR3
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR4
PDMA_BCR4
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR5
PDMA_BCR5
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR6
PDMA_BCR6
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR7
PDMA_BCR7
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_BCR8
PDMA_BCR8
PDMA Channel x Transfer Byte Count Register
PDMA_BCR0
0xC
read-write
n
0x0
0x0
PDMA_CBCR0
PDMA_CBCR0
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to "1".
0
16
read-only
PDMA_CBCR1
PDMA_CBCR1
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR2
PDMA_CBCR2
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR3
PDMA_CBCR3
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR4
PDMA_CBCR4
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR5
PDMA_CBCR5
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR6
PDMA_CBCR6
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR7
PDMA_CBCR7
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CBCR8
PDMA_CBCR8
PDMA Channel x Current Transfer Byte Count Register
PDMA_CBCR0
0x1C
read-write
n
0x0
0x0
PDMA_CDAR0
PDMA_CDAR0
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CDAR1
PDMA_CDAR1
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR2
PDMA_CDAR2
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR3
PDMA_CDAR3
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR4
PDMA_CDAR4
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR5
PDMA_CDAR5
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR6
PDMA_CDAR6
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR7
PDMA_CDAR7
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CDAR8
PDMA_CDAR8
PDMA Channel x Current Destination Address Register
PDMA_CDAR0
0x18
read-write
n
0x0
0x0
PDMA_CSAR0
PDMA_CSAR0
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSAR1
PDMA_CSAR1
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR2
PDMA_CSAR2
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR3
PDMA_CSAR3
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR4
PDMA_CSAR4
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR5
PDMA_CSAR5
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR6
PDMA_CSAR6
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR7
PDMA_CSAR7
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSAR8
PDMA_CSAR8
PDMA Channel x Current Source Address Register
PDMA_CSAR0
0x14
read-write
n
0x0
0x0
PDMA_CSR0
PDMA_CSR0
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_CSR1
PDMA_CSR1
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR2
PDMA_CSR2
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR3
PDMA_CSR3
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR4
PDMA_CSR4
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR5
PDMA_CSR5
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR6
PDMA_CSR6
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR7
PDMA_CSR7
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_CSR8
PDMA_CSR8
PDMA Channel x Control Register
PDMA_CSR0
0x0
read-write
n
0x0
0x0
PDMA_DAR0
PDMA_DAR0
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
0
32
read-write
PDMA_DAR1
PDMA_DAR1
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR2
PDMA_DAR2
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR3
PDMA_DAR3
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR4
PDMA_DAR4
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR5
PDMA_DAR5
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR6
PDMA_DAR6
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR7
PDMA_DAR7
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_DAR8
PDMA_DAR8
PDMA Channel x Destination Address Register
PDMA_DAR0
0x8
read-write
n
0x0
0x0
PDMA_IER0
PDMA_IER0
PDMA Channel x Interrupt Enable Register
0x20
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_IER1
PDMA_IER1
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER2
PDMA_IER2
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER3
PDMA_IER3
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER4
PDMA_IER4
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER5
PDMA_IER5
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER6
PDMA_IER6
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER7
PDMA_IER7
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_IER8
PDMA_IER8
PDMA Channel x Interrupt Enable Register
PDMA_IER0
0x20
read-write
n
0x0
0x0
PDMA_ISR0
PDMA_ISR0
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_ISR1
PDMA_ISR1
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR2
PDMA_ISR2
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR3
PDMA_ISR3
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR4
PDMA_ISR4
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR5
PDMA_ISR5
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR6
PDMA_ISR6
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR7
PDMA_ISR7
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_ISR8
PDMA_ISR8
PDMA Channel x Interrupt Status Register
PDMA_ISR0
0x24
read-write
n
0x0
0x0
PDMA_POINT0
PDMA_POINT0
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_POINT1
PDMA_POINT1
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT2
PDMA_POINT2
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT3
PDMA_POINT3
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT4
PDMA_POINT4
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT5
PDMA_POINT5
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT6
PDMA_POINT6
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT7
PDMA_POINT7
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_POINT8
PDMA_POINT8
PDMA Channel x Internal Buffer Pointer Register
PDMA_POINT0
0x10
read-write
n
0x0
0x0
PDMA_SAR0
PDMA_SAR0
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SAR1
PDMA_SAR1
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR2
PDMA_SAR2
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR3
PDMA_SAR3
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR4
PDMA_SAR4
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR5
PDMA_SAR5
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR6
PDMA_SAR6
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR7
PDMA_SAR7
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SAR8
PDMA_SAR8
PDMA Channel x Source Address Register
PDMA_SAR0
0x4
read-write
n
0x0
0x0
PDMA_SBUF0_C0
PDMA_SBUF0_C0
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_SBUF0_C1
PDMA_SBUF0_C1
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C2
PDMA_SBUF0_C2
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C3
PDMA_SBUF0_C3
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C4
PDMA_SBUF0_C4
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C5
PDMA_SBUF0_C5
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C6
PDMA_SBUF0_C6
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C7
PDMA_SBUF0_C7
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_SBUF0_C8
PDMA_SBUF0_C8
PDMA Channel x Shared Buffer FIFO 0 Register
PDMA_SBUF0_C0
0x80
read-write
n
0x0
0x0
PDMA_GCR
PDMA Register Map
PDMA
0x0
0x0
0x14
registers
n
PDMA_GCRCSR
PDMA_GCRCSR
PDMA Global Control Register
0x0
read-write
n
0x0
0x0
CLK0_EN
PDMA Controller Channel 0 Clock Enable Bit\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK1_EN
PDMA Controller Channel 1 Clock Enable Bit\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK2_EN
PDMA Controller Channel 2 Clock Enable Bit \n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK3_EN
PDMA Controller Channel 3 Clock Enable Bit\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK4_EN
PDMA Controller Channel 4 Clock Enable Bit\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK5_EN
PDMA Controller Channel 5 Clock Enable Bit\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK6_EN
PDMA Controller Channel 6 Clock Enable Bit\n
14
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK7_EN
PDMA Controller Channel 7 Clock Enable Bit\n
15
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK8_EN
PDMA Controller Channel 8 Clock Enable Bit \n
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CRC_CLK_EN
CRC Controller Clock Enable Bit\n
24
1
read-write
0
Disabled
#0
1
Enabled
#1
PDMA_GCRISR
PDMA_GCRISR
PDMA Global Interrupt Status Register
0xC
read-only
n
0x0
0x0
INTR
Interrupt Status\nThis bit is the interrupt status of PDMA controller.\nNote: This bit is read only.
31
1
read-only
INTR0
Interrupt Status Of Channel 0\nThis bit is the interrupt status of PDMA channel0.\nNote: This bit is read only.
0
1
read-only
INTR1
Interrupt Status Of Channel 1\nThis bit is the interrupt status of PDMA channel1.\nNote: This bit is read only.
1
1
read-only
INTR2
Interrupt Status Of Channel 2\nThis bit is the interrupt status of PDMA channel2.\nNote: This bit is read only.
2
1
read-only
INTR3
Interrupt Status Of Channel 3\nThis bit is the interrupt status of PDMA channel3.\nNote: This bit is read only.
3
1
read-only
INTR4
Interrupt Status Of Channel 4\nThis bit is the interrupt status of PDMA channel4.\nNote: This bit is read only.
4
1
read-only
INTR5
Interrupt Status Of Channel 5 \nThis bit is the interrupt status of PDMA channel5.\nNote: This bit is read only.
5
1
read-only
INTR6
Interrupt Status Of Channel 6 \nThis bit is the interrupt status of PDMA channel6.\nNote: This bit is read only.
6
1
read-only
INTR7
Interrupt Status Of Channel 7 \nThis bit is the interrupt status of PDMA channel7.\nNote: This bit is read only.
7
1
read-only
INTR8
Interrupt Status Of Channel 8 \nThis bit is the interrupt status of PDMA channel8.\nNote: This bit is read only.
8
1
read-only
INTRCRC
Interrupt Status Of CRC Controller\nThis bit is the interrupt status of CRC controller\nNote: This bit is read only
16
1
read-only
PDMA_PDSSR0
PDMA_PDSSR0
PDMA Service Selection Control Register 0
0x4
read-write
n
0x0
0x0
SPI0_RXSEL
PDMA SPI0 RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3 \n0100: CH4 \n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved
0
4
read-write
SPI0_TXSEL
PDMA SPI0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
4
4
read-write
SPI1_RXSEL
PDMA SPI1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
8
4
read-write
SPI1_TXSEL
PDMA SPI1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
12
4
read-write
SPI2_RXSEL
PDMA SPI2 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
16
4
read-write
SPI2_TXSEL
PDMA SPI2 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
20
4
read-write
SPI3_RXSEL
PDMA SPI3 RX Selection \nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
24
4
read-write
SPI3_TXSEL
PDMA SPI3 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
28
4
read-write
PDMA_PDSSR1
PDMA_PDSSR1
PDMA Service Selection Control Register 1
0x8
read-write
n
0x0
0x0
ADC_RXSEL
PDMA ADC RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
24
4
read-write
UART0_RXSEL
PDMA UART0 RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3 \n0100: CH4 \n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved
0
4
read-write
UART0_TXSEL
PDMA UART0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
4
4
read-write
UART1_RXSEL
PDMA UART1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
8
4
read-write
UART1_TXSEL
PDMA UART1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
12
4
read-write
PDMA_PDSSR2
PDMA_PDSSR2
PDMA Service Selection Control Register 2
0x10
read-write
n
0x0
0x0
I2S_RXSEL
PDMA I2S RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3\n0100: CH4\n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved
0
4
read-write
I2S_TXSEL
PDMA I2S TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by this field. The channel configuration is the same as I2S_RXSEL (PDMA_PDSSR2[3:0]) field. Please refer to the explanation of I2S_RXSEL (PDMA_PDSSR2[3:0]).
4
4
read-write
PS2
PS2 Register Map
PS2
0x0
0x0
0x20
registers
n
PS2CON
PS2CON
PS/2 Control Register
0x0
read-write
n
0x0
0x0
ACK
Acknowledge Enable Bit\n
7
1
read-write
0
Always send acknowledge to host at 12th clock for host to device communication
#0
1
If parity bit error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock
#1
CLRFIFO
Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY(PS2STATUS[7]) bit will be set to 1 and pointer BYTEIDX (PS2STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
8
1
read-write
0
Not active
#0
1
Clear FIFO
#1
FPS2CLK
Force PS2CLK Line\nIt forces PS2_CLK line high or low regardless of the internal state of the device controller if OVERRIDE(PS2CON[9]) is set to 1.\n
10
1
read-write
0
Force PS2_CLK line low
#0
1
Force PS2_CLK line high
#1
FPS2DAT
Force PS2DATA Line\nIt forces PS2_DATA high or low regardless of the internal state of the device controller if OVERRIDE (PS2CON[9]) is set to 1.\n
11
1
read-write
0
Force PS2_DATA low
#0
1
Force PS2_DATA high
#1
OVERRIDE
Software Override PS/2 CLK/DATA Pin State\n
9
1
read-write
0
PS2_CLK and PS2_DATA pins are controlled by internal state machine
#0
1
PS2_CLK and PS2_DATA pins are controlled by software
#1
PS2EN
PS/2 Device Enable Bit\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
RXINTEN
Receive Interrupt Enable Bit\n
2
1
read-write
0
Data receive complete interrupt Disabled
#0
1
Data receive complete interrupt Enabled
#1
TXFIFO_DEPTH
Transmit Data FIFO Depth\nThere is a 16 bytes buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depends on application.\n
3
4
read-write
0
1 byte
0
1
2 bytes
1
14
15 bytes
14
15
16 bytes
15
TXINTEN
Transmit Interrupt Enable Bit\n
1
1
read-write
0
Data transmit complete interrupt Disabled
#0
1
Data transmit complete interrupt Enabled
#1
PS2INTID
PS2INTID
PS/2 Interrupt Identification Register
0x1C
read-write
n
0x0
0x0
RXINT
Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN(PS2CON[2]) bit is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No interrupt
#0
1
Receive interrupt occurs
#1
TXINT
Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN(PS2CON[1]) bit is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
No interrupt
#0
1
Transmit interrupt occurs
#1
PS2RXDATA
PS2RXDATA
PS/2 Receive Data Register
0x14
read-only
n
0x0
0x0
RXDATA
Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete, otherwise the data will be overwritten and RXOVF(PS2STATUS[6]) bit will be set to 1.
0
8
read-only
PS2STATUS
PS2STATUS
PS/2 Status Register
0x18
read-write
n
0x0
0x0
BYTEIDX
Byte Index\nIt indicates which data byte in transmit data shift register. When all data in FIFO is transmitted and it will be cleared to 0.\nThis bit is read only.\n
8
4
read-write
0
PS2TXDATA0[7:0]
#0000
1
PS2TXDATA0[15:8]
#0001
2
PS2TXDATA0[23:16]
#0010
3
PS2TXDATA0[31:24]
#0011
4
PS2TXDATA1[7:0]
#0100
5
PS2TXDATA1[15:8]
#0101
6
PS2TXDATA1[23:16]
#0110
7
PS2TXDATA1[31:24]
#0111
8
PS2TXDATA2[7:0]
#1000
9
PS2TXDATA2[15:8]
#1001
10
PS2TXDATA2[23:16]
#1010
11
PS2TXDATA2[31:24]
#1011
12
PS2TXDATA3[7:0]
#1100
13
PS2TXDATA3[15:8]
#1101
14
PS2TXDATA3[23:16]
#1110
15
PS2TXDATA3[31:24]
#1111
FRAMERR
Frame Error\nFor host to device communication, this bit sets to 1 if STOP bit (logic 1) is not received. If frame error occurs, the PS/2_DATA line may keep at low state after 12th clock. At this moment, software overrides PS2_CLK to send clock till PS2_DATA release to high state. After that, device sends a "Resend" command to host.\nWrite 1 to clear this bit.
2
1
read-write
0
No frame error
#0
1
Frame error occur
#1
PS2CLK
CLK Pin State\nThis bit reflects the status of the PS2_CLK line after synchronizing.
0
1
read-write
PS2DATA
DATA Pin State\nThis bit reflects the status of the PS2_DATA line after synchronizing and sampling.
1
1
read-write
RXBUSY
Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nThis bit is read only.
4
1
read-write
0
Idle
#0
1
Currently receiving data
#1
RXOVF
RX Buffer Overwrite\nWrite 1 to clear this bit.
6
1
read-write
0
No overwrite
#0
1
Data in PS2RXDATA register is overwritten by new received data
#1
RXPARITY
Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nThis bit is read only.
3
1
read-write
TXBUSY
Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nThis bit is read only.
5
1
read-write
0
Idle
#0
1
Currently sending data
#1
TXEMPTY
TX FIFO Empty\nWhen software writes data to PS2TXDATA0-3, the TXEMPTY bit is cleared to 0 immediately if PS2EN(PS2CON[0]) is enabled. When transmitted data byte number is equal to TXFIFO_DEPTH (PS2CON[6:3]) then TXEMPTY bit is set to 1.\nThis bit is read only.
7
1
read-write
0
There is data to be transmitted
#0
1
FIFO is empty
#1
PS2TXDATA0
PS2TXDATA0
PS/2 Transmit Data Register 0
0x4
read-write
n
0x0
0x0
PS2TXDATAx
Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer.
0
32
read-write
PS2TXDATA1
PS2TXDATA1
PS/2 Transmit Data Register 1
0x8
read-write
n
0x0
0x0
PS2TXDATA2
PS2TXDATA2
PS/2 Transmit Data Register 2
0xC
read-write
n
0x0
0x0
PS2TXDATA3
PS2TXDATA3
PS/2 Transmit Data Register 3
0x10
read-write
n
0x0
0x0
PWMA
PWM Register Map
PWM
0x0
0x0
0x48
registers
n
0x50
0x48
registers
n
CAPENR
CAPENR
PWM Capture Input 0~3 Enable Register
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable Bit\n
0
1
read-write
0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#0
1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
#1
CINEN1
Channel 1 Capture Input Enable Bit\n
1
1
read-write
0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#0
1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
#1
CINEN2
Channel 2 Capture Input Enable Bit\n
2
1
read-write
0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#0
1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
#1
CINEN3
Channel 3 Capture Input Enable Bit\n
3
1
read-write
0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#0
1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
#1
CCR0
CCR0
PWM Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable Bit\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable Bit\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Capture Control Register 2
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 2 Disabled
#0
1
Capture function on PWM group channel 2 Enabled
#1
CAPCH3EN
Channel 3 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
4
1
read-write
CAPIF3
Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
20
1
read-write
CFLRI2
CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
7
1
read-write
CFLRI3
CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
23
1
read-write
CFL_IE2
Channel 2 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
Channel 3 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI3
CRLR3 Latched Indicator\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
22
1
read-write
CRL_IE2
Channel 2 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
Channel 3 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
Channel 2 Inverter Enable Bit\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
Channel 3 Inverter Enable Bit\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Source Divider Select Register
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
4
3
read-write
CSR2
PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
8
3
read-write
CSR3
PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\nSelect clock source divider for PWM timer 3.\n
12
3
read-write
0
2
#000
1
4
#001
2
8
#010
3
16
#011
4
1
#100
PBCR
PBCR
PWM Backward Compatible Register
0x3C
read-write
n
0x0
0x0
BCn
PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6, 7, 22, 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2.
0
1
read-write
0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#0
1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
#1
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\n
0
1
read-write
0
The corresponding PWM-Timer stops running
#0
1
The corresponding PWM-Timer starts running
#1
CH0INV
PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH0PINV
PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\n
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\n
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\n
10
1
read-write
0
Inverter Disable
#0
1
Inverter Enable
#1
CH1MOD
PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1PINV
PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\n
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
CH2EN
PWM-Timer 2 Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\n
16
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH2INV
PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH2PINV
PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\n
17
1
read-write
0
PWM2 output polar inverse Disabled
#0
1
PWM2 output polar inverse Enabled
#1
CH3EN
PWM-Timer 3 Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\n
24
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH3INV
PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\n
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3PINV
PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\n
25
1
read-write
0
PWM3 output polar inverse Disable
#0
1
PWM3 output polar inverse Enable
#1
DZEN01
Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\n
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PWM23TYPE
PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
0
16
read-only
PDR1
PDR1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
INT01TYPE
PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
16
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
INT23TYPE
PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
17
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
PWMDIE0
PWM Channel 0 Duty Interrupt Enable Bit\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE1
PWM Channel 1 Duty Interrupt Enable Bit\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE2
PWM Channel 2 Duty Interrupt Enable Bit\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE3
PWM Channel 3 Duty Interrupt Enable Bit\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE0
PWM Channel 0 Period Interrupt Enable Bit\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE1
PWM Channel 1 Period Interrupt Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE2
PWM Channel 2 Period Interrupt Enable Bit\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE3
PWM Channel 3 Period Interrupt Enable Bit\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMDIF0
PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
8
1
read-write
PWMDIF1
PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
9
1
read-write
PWMDIF2
PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
10
1
read-write
PWMDIF3
PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
11
1
read-write
PWMIF0
PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
0
1
read-write
PWMIF1
PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
1
1
read-write
PWMIF2
PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
2
1
read-write
PWMIF3
PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
3
1
read-write
POE
POE
PWM Output Enable for Channel 0~3
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
POE2
Channel 2 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
POE3
Channel 3 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PPR
PPR
PWM Prescaler Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n
0
8
read-write
CP23
Clock Prescaler 2 (PWM-Timer2 / 3 For Group A And PWM-Timer 6 / 7 For Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
8
8
read-write
DZI01
Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
16
8
read-write
DZI23
Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
24
8
read-write
SYNCBUSY0
SYNCBUSY0
PWM0 Synchronous Busy Status Register
0x88
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR0/CMR0/PPR or switching PWM0 operation mode (PCR[3]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY1
SYNCBUSY1
PWM1 Synchronous Busy Status Register
0x8C
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY2
SYNCBUSY2
PWM2 Synchronous Busy Status Register
0x90
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY3
SYNCBUSY3
PWM3 Synchronous Busy Status Register
0x94
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure previous setting has been updated completely.\nThis bit will be set when Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
TCON
TCON
PWM Trigger Control for Channel 0~3
0x80
read-write
n
0x0
0x0
PWM0TEN
Channel 0 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
0
1
read-write
0
PWM channel 0 trigger ADC function Disabled
#0
1
PWM channel 0 trigger ADC function Enabled
#1
PWM1TEN
Channel 1 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
1
1
read-write
0
PWM channel 1 trigger ADC function Disabled
#0
1
PWM channel 1 trigger ADC function Enabled
#1
PWM2TEN
Channel 2 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
2
1
read-write
0
PWM channel 2 trigger ADC function Disabled
#0
1
PWM channel 2 trigger ADC function Enabled
#1
PWM3TEN
Channel 3 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
3
1
read-write
0
PWM channel 3 trigger ADC function Disabled
#0
1
PWM channel 3 trigger ADC function Enabled
#1
TSTATUS
TSTATUS
PWM Trigger Status Register
0x84
read-write
n
0x0
0x0
PWM0TF
Channel 0 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
0
1
read-write
PWM1TF
Channel 1 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
1
1
read-write
PWM2TF
Channel 2 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
2
1
read-write
PWM3TF
Channel 3 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
3
1
read-write
PWMB
PWM Register Map
PWM
0x0
0x0
0x48
registers
n
0x50
0x48
registers
n
CAPENR
CAPENR
PWM Capture Input 0~3 Enable Register
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable Bit\n
0
1
read-write
0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#0
1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
#1
CINEN1
Channel 1 Capture Input Enable Bit\n
1
1
read-write
0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#0
1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
#1
CINEN2
Channel 2 Capture Input Enable Bit\n
2
1
read-write
0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#0
1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
#1
CINEN3
Channel 3 Capture Input Enable Bit\n
3
1
read-write
0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#0
1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
#1
CCR0
CCR0
PWM Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable Bit\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable Bit\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Capture Control Register 2
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 2 Disabled
#0
1
Capture function on PWM group channel 2 Enabled
#1
CAPCH3EN
Channel 3 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
4
1
read-write
CAPIF3
Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
20
1
read-write
CFLRI2
CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
7
1
read-write
CFLRI3
CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
23
1
read-write
CFL_IE2
Channel 2 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
Channel 3 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI3
CRLR3 Latched Indicator\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
22
1
read-write
CRL_IE2
Channel 2 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
Channel 3 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
Channel 2 Inverter Enable Bit\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
Channel 3 Inverter Enable Bit\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Source Divider Select Register
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
4
3
read-write
CSR2
PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
8
3
read-write
CSR3
PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\nSelect clock source divider for PWM timer 3.\n
12
3
read-write
0
2
#000
1
4
#001
2
8
#010
3
16
#011
4
1
#100
PBCR
PBCR
PWM Backward Compatible Register
0x3C
read-write
n
0x0
0x0
BCn
PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6, 7, 22, 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2.
0
1
read-write
0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#0
1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
#1
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\n
0
1
read-write
0
The corresponding PWM-Timer stops running
#0
1
The corresponding PWM-Timer starts running
#1
CH0INV
PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH0PINV
PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\n
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\n
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\n
10
1
read-write
0
Inverter Disable
#0
1
Inverter Enable
#1
CH1MOD
PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1PINV
PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\n
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
CH2EN
PWM-Timer 2 Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\n
16
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH2INV
PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH2PINV
PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A And PWM Timer 6 For Group B)\n
17
1
read-write
0
PWM2 output polar inverse Disabled
#0
1
PWM2 output polar inverse Enabled
#1
CH3EN
PWM-Timer 3 Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\n
24
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH3INV
PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\n
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3PINV
PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A And PWM Timer 7 For Group B)\n
25
1
read-write
0
PWM3 output polar inverse Disable
#0
1
PWM3 output polar inverse Enable
#1
DZEN01
Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\n
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PWM23TYPE
PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
0
16
read-only
PDR1
PDR1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
INT01TYPE
PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
16
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
INT23TYPE
PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
17
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
PWMDIE0
PWM Channel 0 Duty Interrupt Enable Bit\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE1
PWM Channel 1 Duty Interrupt Enable Bit\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE2
PWM Channel 2 Duty Interrupt Enable Bit\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE3
PWM Channel 3 Duty Interrupt Enable Bit\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE0
PWM Channel 0 Period Interrupt Enable Bit\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE1
PWM Channel 1 Period Interrupt Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE2
PWM Channel 2 Period Interrupt Enable Bit\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMIE3
PWM Channel 3 Period Interrupt Enable Bit\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMDIF0
PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
8
1
read-write
PWMDIF1
PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
9
1
read-write
PWMDIF2
PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
10
1
read-write
PWMDIF3
PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
11
1
read-write
PWMIF0
PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
0
1
read-write
PWMIF1
PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
1
1
read-write
PWMIF2
PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
2
1
read-write
PWMIF3
PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
3
1
read-write
POE
POE
PWM Output Enable for Channel 0~3
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
POE2
Channel 2 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
POE3
Channel 3 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PPR
PPR
PWM Prescaler Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n
0
8
read-write
CP23
Clock Prescaler 2 (PWM-Timer2 / 3 For Group A And PWM-Timer 6 / 7 For Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
8
8
read-write
DZI01
Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
16
8
read-write
DZI23
Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A, PWM6 And PWM7 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
24
8
read-write
SYNCBUSY0
SYNCBUSY0
PWM0 Synchronous Busy Status Register
0x88
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR0/CMR0/PPR or switching PWM0 operation mode (PCR[3]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY1
SYNCBUSY1
PWM1 Synchronous Busy Status Register
0x8C
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY2
SYNCBUSY2
PWM2 Synchronous Busy Status Register
0x90
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY3
SYNCBUSY3
PWM3 Synchronous Busy Status Register
0x94
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure previous setting has been updated completely.\nThis bit will be set when Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
TCON
TCON
PWM Trigger Control for Channel 0~3
0x80
read-write
n
0x0
0x0
PWM0TEN
Channel 0 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
0
1
read-write
0
PWM channel 0 trigger ADC function Disabled
#0
1
PWM channel 0 trigger ADC function Enabled
#1
PWM1TEN
Channel 1 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
1
1
read-write
0
PWM channel 1 trigger ADC function Disabled
#0
1
PWM channel 1 trigger ADC function Enabled
#1
PWM2TEN
Channel 2 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
2
1
read-write
0
PWM channel 2 trigger ADC function Disabled
#0
1
PWM channel 2 trigger ADC function Enabled
#1
PWM3TEN
Channel 3 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
3
1
read-write
0
PWM channel 3 trigger ADC function Disabled
#0
1
PWM channel 3 trigger ADC function Enabled
#1
TSTATUS
TSTATUS
PWM Trigger Status Register
0x84
read-write
n
0x0
0x0
PWM0TF
Channel 0 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
0
1
read-write
PWM1TF
Channel 1 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
1
1
read-write
PWM2TF
Channel 2 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
2
1
read-write
PWM3TF
Channel 3 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
3
1
read-write
RTC
RTC Register Map
RTC
0x0
0x0
0x30
registers
n
0x3C
0x54
registers
n
AER
AER
RTC Access Enable Register
0x4
read-write
n
0x0
0x0
AER
RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clocks.
0
16
write-only
ENF
RTC Register Access Enable Flag (Read Only)\nNote: This bit will be set after AER[15:0] is load a 0xA965, and will be cleared automatically after 1024 RTC clocks.
16
1
read-only
0
RTC register read/write access Disabled
#0
1
RTC register read/write access Enabled
#1
CAR
CAR
Calendar Alarm Register
0x20
read-write
n
0x0
0x0
_10DAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
_10MON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
_10YEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
_1DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
_1MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
_1YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CLR
CLR
Calendar Loading Register
0x10
read-write
n
0x0
0x0
_10DAY
10-Day Calendar Digit (0~3)
4
2
read-write
_10MON
10-Month Calendar Digit (0~1)
12
1
read-write
_10YEAR
10-Year Calendar Digit (0~9)
20
4
read-write
_1DAY
1-Day Calendar Digit (0~9)
0
4
read-write
_1MON
1-Month Calendar Digit (0~9)
8
4
read-write
_1YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
DWR
DWR
Day of the Week Register
0x18
read-write
n
0x0
0x0
DWR
Day Of The Week Register \n
0
3
read-write
0
Sunday
#000
1
Monday
#001
2
Tuesday
#010
3
Wednesday
#011
4
Thursday
#100
5
Friday
#101
6
Saturday
#110
7
Reserved
#111
FCR
FCR
RTC Frequency Compensation Register
0x8
read-write
n
0x0
0x0
FRACTION
Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number..
0
6
read-write
INTEGER
Integer Part\nPlease refer to 5.14.5.4 .
8
4
read-write
INIR
INIR
RTC Initiation Register
0x0
read-write
n
0x0
0x0
INIR
RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0xa5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIR is a write-only field and read value will be always 0.
1
31
read-write
INIR_Active
RTC Active Status (Read Only)\n
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
LIR
LIR
Leap Year Indicator Register
0x24
read-only
n
0x0
0x0
LIR
Leap Year Indication Register (Read Only)\n
0
1
read-only
0
This year is not a leap year
#0
1
This year is a leap year
#1
RIER
RIER
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
AIER
Alarm Interrupt Enable Bit\nThis bit is used to enable/disable RTC Alarm Interrupt, and generate an interrupt signal if AIF (RIIR[0] RTC Alarm Interrupt Flag) is set to 1.\nNote: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode and RTC Alarm Interrupt signal generated.
0
1
read-write
0
RTC Alarm Interrupt Disabled
#0
1
RTC Alarm Interrupt Enabled
#1
TIER
Time Tick Interrupt Enable Bit\nThis bit is used to enable/disable RTC Time Tick Interrupt, and generate an interrupt signal if TIF (RIIR[1] RTC Time Tick Interrupt Flag) is set to 1.\nNote: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode and RTC Time Tick Interrupt signal generated.
1
1
read-write
0
RTC Time Tick Interrupt Disabled
#0
1
RTC Time Tick Interrupt Enabled
#1
RIIR
RIIR
RTC Interrupt Indicator Register
0x2C
read-write
n
0x0
0x0
AIF
RTC Alarm Interrupt Flag\nWhen RTC time counters TLR and CLR match the alarm setting time registers TAR and CAR, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled AIER (RIER[0]) is set to 1. Chip will be wake-up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit.
0
1
read-write
0
Alarm condition is not matched
#0
1
Alarm condition is matched
#1
TIF
RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TIER (RIER[1]) is set to 1. Chip will also be wake-up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: Write 1 to clear this bit.
1
1
read-write
0
Tick condition does not occur
#0
1
Tick condition occur
#1
SPR0
SPR0
RTC Spare Register 0
0x40
read-write
n
0x0
0x0
SPR1
SPR1
RTC Spare Register 1
0x44
read-write
n
0x0
0x0
SPR10
SPR10
RTC Spare Register 10
0x68
read-write
n
0x0
0x0
SPR11
SPR11
RTC Spare Register 11
0x6C
read-write
n
0x0
0x0
SPR12
SPR12
RTC Spare Register 12
0x70
read-write
n
0x0
0x0
SPR13
SPR13
RTC Spare Register 13
0x74
read-write
n
0x0
0x0
SPR14
SPR14
RTC Spare Register 14
0x78
read-write
n
0x0
0x0
SPR15
SPR15
RTC Spare Register 15
0x7C
read-write
n
0x0
0x0
SPR16
SPR16
RTC Spare Register 16
0x80
read-write
n
0x0
0x0
SPR17
SPR17
RTC Spare Register 17
0x84
read-write
n
0x0
0x0
SPR18
SPR18
RTC Spare Register 18
0x88
read-write
n
0x0
0x0
SPR19
SPR19
RTC Spare Register 19
0x8C
read-write
n
0x0
0x0
SPR2
SPR2
RTC Spare Register 2
0x48
read-write
n
0x0
0x0
SPR3
SPR3
RTC Spare Register 3
0x4C
read-write
n
0x0
0x0
SPR4
SPR4
RTC Spare Register 4
0x50
read-write
n
0x0
0x0
SPR5
SPR5
RTC Spare Register 5
0x54
read-write
n
0x0
0x0
SPR6
SPR6
RTC Spare Register 6
0x58
read-write
n
0x0
0x0
SPR7
SPR7
RTC Spare Register 7
0x5C
read-write
n
0x0
0x0
SPR8
SPR8
RTC Spare Register 8
0x60
read-write
n
0x0
0x0
SPR9
SPR9
RTC Spare Register 9
0x64
read-write
n
0x0
0x0
SPRCTL
SPRCTL
RTC Spare Functional Control Register
0x3C
read-write
n
0x0
0x0
SPREN
SPR Register Enable Bit\nNote: When spare register is disabled, RTC SPR0 ~ SPR19 cannot be accessed.
2
1
read-write
0
Spare register is Disabled
#0
1
Spare register is Enabled
#1
SPRRDY
SPR Register Ready\nThis bit indicates if the registers SPRCTL, SPR0 ~ SPR19 are ready to be accessed.\nAfter user writing registers SPRCTL, SPR0 ~ SPR19, read this bit to check if these registers are updated done is necessary.\nNote: This bit is read only and any write to it won't take any effect.
7
1
read-write
0
SPRCTL, SPR0 ~ SPR19 updating is in progress
#0
1
SPRCTL, SPR0 ~ SPR19 are updated done and ready to be accessed
#1
TAR
TAR
Time Alarm Register
0x1C
read-write
n
0x0
0x0
_10HR
10-Hour Time Digit of Alarm Setting (0~2)
20
2
read-write
_10MIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
_10SEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
_1HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
_1MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
_1SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TLR
TLR
Time Loading Register
0xC
read-write
n
0x0
0x0
_10HR
10-Hour Time Digit (0~2)
20
2
read-write
_10MIN
10-Min Time Digit (0~5)
12
3
read-write
_10SEC
10-Sec Time Digit (0~5)
4
3
read-write
_1HR
1-Hour Time Digit (0~9)
16
4
read-write
_1MIN
1-Min Time Digit (0~9)
8
4
read-write
_1SEC
1-Sec Time Digit (0~9)
0
4
read-write
TSSR
TSSR
Time Scale Selection Register
0x14
read-write
n
0x0
0x0
_24H_12H
24-Hour / 12-Hour Time Scale Selection\nIt indicates that RTC TLR and TAR counter are in 24-hour time scale or 12-hour time scale. Please refer to 5.14.5.6 .\n
0
1
read-write
0
24-hour time scale selected
#0
1
24-hour time scale selected
#1
TTR
TTR
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TTR
Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote: This register can be read back after the RTC register access enable bit ENF (AER[16]) is active.
0
3
read-write
0
Time tick is 1 second
#000
1
Time tick is 1/2 second
#001
2
Time tick is 1/4 second
#010
3
Time tick is 1/8 second
#011
4
Time tick is 1/16 second
#100
5
Time tick is 1/32 second
#101
6
Time tick is 1/64 second
#110
7
Time tick is 1/28 second
#111
SC0
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACT_EN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
DACT_EN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST, and RX_RST at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INIT_SEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 679.\nWarm-reset: refer to Warm-Reset Sequence in Figure 680.\nDeactivation: refer to Deactivation Sequence in Figure 681.
8
2
read-write
OUTSEL
Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin (SC_DATA) output mode\n
16
1
read-write
0
Quasi mode
#0
1
Open-drain mode
#1
RX_BGT_EN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RX_RST
Rx Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TMR0_ATV
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
TMR0_SEN
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST and RX_RST at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
TMR1_ATV
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
TMR1_SEN
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
TMR2_ATV
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
TMR2_SEN
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
TX_RST
TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARST_EN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST, and RX_RST at the same time.\nNote3: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTO_CON_EN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CON_SEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CD_DEB_SEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) SC peripheral clocks and de-bounce sample card removal once per 128 SC peripheral clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) SC peripheral clocks and de-bounce sample card removal once per 64 SC peripheral clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) SC peripheral clocks and de-bounce sample card removal once per 32 SC peripheral clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) SC peripheral clocks and de-bounce sample card removal once per 16 SC peripheral clocks
#11
CON_SEL
Convention Selection\nNote: If AUTO_CON_EN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
DIS_RX
RX Transition Disable Bit\nNote: If AUTO_CON_EN (SC_CTL[3])is enabled, these fields must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
DIS_TX
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
RX_ERETRY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RX_ERETRY_EN
RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RX_ERETRY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RX_FTRI_LEV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SC_CEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SLEN
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RX_ERETRY and TX_ERETRY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to RX_ERETRY and TX_ERETRY
#0
1
Last value is synchronizing
#1
TMR_SEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMR0 [23:0]. SC_TMR1 and SC_TMR2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1[7:0]. SC_TMR2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0]
#11
TX_ERETRY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TX_ERETRY_EN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_EGTR
SC_EGTR
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCR
SC_ETUCR
SC ETU Control Register
0x14
read-write
n
0x0
0x0
COMPEN_EN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETU_RDIV .\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETU_RDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_IER
SC_IER
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACON_ERR_IE
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGT_IE
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CD_IE
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F(SC_SR[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INIT_IE
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDA_IE
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RTMR_IE
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TERR_IE
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_SR[5]), parity error RX_EPA_F(SC_SR[4]), receiver buffer overflow error RX_OVER_F(SC_SR[0]), transmit buffer overflow error TX_OVER_F(SC_SR[8]), receiver retry over limit error RX_OVER_REERR(SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR(SC_SR[30]).\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0_IE
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1_IE
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2_IE
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
TXBE_IE
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
SC_ISR
SC_ISR
SC Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ACON_ERR_IS
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGT_IS
\n
6
1
read-only
CD_IS
Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F(SC_SR[11]).\nNote: This field is the status flag of CD_INS_F(SC_SR[12]) or CD_REM_F(SC_TRSR[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INIT_IS
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN(SC_ALTCTL[3])), deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RDA_IS
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV (SC_CTL[7:6]). If software reads data from SC_RBR and receiver buffer data byte number is less than RX_FTRI_LEV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
RTMR_IS
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_RBR buffer,
9
1
read-only
TBE_IS
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to THR(SC_THR[7:0]) buffer and then this bit will be cleared automatically.
1
1
read-only
TERR_IS
Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_TRSR[5], parity error RX_EPA_F(SC_TRSR[4] and receiver buffer overflow error RX_OVER_F(SC_TRSR[0]), transmit buffer overflow error TX_OVER_F(SC_TRSR[8]), receiver retry over limit error RX_OVER_REERR(SC_TRSR[22] and transmitter retry over limit error TX_OVER_REERR(SC_TRSR[30]).\nNote: This field is the status flag of RX_EBR_F(SC_TRSR[6]), RX_EFR_F(SC_TRSR[5]), RX_EPA_F(SC_TRSR[4]), RX_OVER_F(SC_TRSR[0]), TX_OVER_F(SC_TRSR[8]), RX_OVER_REERR(SC_TRSR[22]) or TX_OVER_REERR(SC_TRSR[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0_IS
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1_IS
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2_IS
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCSR
SC_PINCSR
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
ADAC_CD_EN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU.
7
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CD_INS_F
Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only, but it can be cleared by writing "1" to it.\nNote2: The card detect engine will start after SC_CEN (SC_CTL[0] )set.
3
1
read-only
0
No effect
#0
1
Card insert
#1
CD_LEV
Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled
10
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CD_PIN_ST
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
4
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CD_REM_F
Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever a card has been removed.\nNote1: This bit is read only, but it can be cleared by writing "1" to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0] )set.
2
1
read-only
0
No effect
#0
1
Card removed
#1
CLK_KEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
POW_EN
SC_POW_EN Pin Signal\nSoftware can set POW_EN (SC_PINCSR[0]) and POW_INV (SC_PINCSR[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV (SC_PINCSR[11]) description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
POW_INV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by POW_INV(SC_PINCSR[11]) and POW_EN(SC_PINCSR[0]). POW_INV (SC_PINCSR[11]) is bit 1 and POW_EN(SC_PINCSR[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote: Software must select POW_INV (SC_PINCSR[11]) before Smart Card is enabled by SC_CEN (SC_CTL[0]).
11
1
read-write
SC_DATA_I_ST
SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DATA\n
16
1
read-only
0
The SC_DATA pin is low
#0
1
The SC_DATA pin is high
#1
SC_DATA_O
SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SC_DATA_O pin to low
#0
1
Drive SC_DATA_O pin to high
#1
SC_OEN_ST
SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n
8
1
read-only
0
The SC_DATA_OEN pin state at low
#0
1
The SC_DATA_OEN pin state at high
#1
SC_RST
SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SC_RST pin to low.\nSC_RST pin status is low
#0
1
Drive SC_RST pin to high.\nSC_RST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCSR register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCSR register
#0
1
Last value is synchronizing
#1
SC_RBR
SC_RBR
SC Receiving Buffer Register.
0x0
read-only
n
0x0
0x0
RBR
Receiving Buffer \nBy reading RBR, the SC will return an 8-bit received data.
0
8
read-only
SC_RFTMR
SC_RFTMR
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_TDRA
SC_TDRA
SC Timer Current Data Register A
0x38
read-only
n
0x0
0x0
TDR0
Timer0 Current Data Value(Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TDRB
SC_TDRB
SC Timer Current Data Register B
0x3C
read-only
n
0x0
0x0
TDR1
Timer1 Current Data Value(Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
TDR2
Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_THR
SC_THR
SC Transmit Holding Register
SC_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Buffer\nBy writing data to THR, the SC will send out an 8-bit data.\nNote: If SC_CEN(SC_CTL[0]) is not enabled, THR cannot be programmed.
0
8
write-only
SC_TMR0
SC_TMR0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT0
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
MODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer0
24
4
read-write
SC_TMR1
SC_TMR1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT1
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer1
24
4
read-write
SC_TMR2
SC_TMR2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT2
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.14.5.4 for programming Timer2
24
4
read-write
SC_TRSR
SC_TRSR
SC Status Register
0x20
read-write
n
0x0
0x0
RX_ATV
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RX_EBR_F
Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). .\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
RX_EFR_F
Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
RX_EMPTY_F
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RX_EPA_F
Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit".\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RX_FULL_F
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RX_OVER_F
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RX_OVER_REERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]), the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set RX_EPA_F(SC_TRSR[4])).
22
1
read-only
RX_POINT_F
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F(SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU, RX_POINT_F(SC_SR[17:16]) decreases one.
16
2
read-only
RX_REERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RX_ERETRY_EN (SC_CTL[19]) , the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set RX_EPA_F(SC_TRSR[4])).
21
1
read-only
TX_ATV
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TX_EMPTY_F
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR(SC_THR[7:0]) (TX buffer not empty).
9
1
read-only
TX_FULL_F
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TX_OVER_F
TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full, an additional write to THR(SC_THR[7:0]) will cause this bit be set to "1" by hardware. \nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TX_OVER_REERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TX_POINT_F
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
24
2
read-only
TX_REERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_UACTL
SC_UACTL
SC UART Mode Control Register.
0x34
read-write
n
0x0
0x0
DATA_LEN
Data Length\nNote: In smart card mode, this DATA_LEN must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBDIS bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBDIS
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UA_MODE_EN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
SC1
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACT_EN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
DACT_EN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST, and RX_RST at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INIT_SEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 679.\nWarm-reset: refer to Warm-Reset Sequence in Figure 680.\nDeactivation: refer to Deactivation Sequence in Figure 681.
8
2
read-write
OUTSEL
Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin (SC_DATA) output mode\n
16
1
read-write
0
Quasi mode
#0
1
Open-drain mode
#1
RX_BGT_EN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RX_RST
Rx Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TMR0_ATV
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
TMR0_SEN
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST and RX_RST at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
TMR1_ATV
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
TMR1_SEN
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
TMR2_ATV
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
TMR2_SEN
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
TX_RST
TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARST_EN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST, and RX_RST at the same time.\nNote3: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTO_CON_EN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CON_SEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CD_DEB_SEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) SC peripheral clocks and de-bounce sample card removal once per 128 SC peripheral clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) SC peripheral clocks and de-bounce sample card removal once per 64 SC peripheral clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) SC peripheral clocks and de-bounce sample card removal once per 32 SC peripheral clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) SC peripheral clocks and de-bounce sample card removal once per 16 SC peripheral clocks
#11
CON_SEL
Convention Selection\nNote: If AUTO_CON_EN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
DIS_RX
RX Transition Disable Bit\nNote: If AUTO_CON_EN (SC_CTL[3])is enabled, these fields must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
DIS_TX
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
RX_ERETRY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RX_ERETRY_EN
RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RX_ERETRY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RX_FTRI_LEV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SC_CEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SLEN
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RX_ERETRY and TX_ERETRY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to RX_ERETRY and TX_ERETRY
#0
1
Last value is synchronizing
#1
TMR_SEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMR0 [23:0]. SC_TMR1 and SC_TMR2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1[7:0]. SC_TMR2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0]
#11
TX_ERETRY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TX_ERETRY_EN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_EGTR
SC_EGTR
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCR
SC_ETUCR
SC ETU Control Register
0x14
read-write
n
0x0
0x0
COMPEN_EN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETU_RDIV .\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETU_RDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_IER
SC_IER
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACON_ERR_IE
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGT_IE
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CD_IE
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F(SC_SR[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INIT_IE
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDA_IE
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RTMR_IE
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TERR_IE
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_SR[5]), parity error RX_EPA_F(SC_SR[4]), receiver buffer overflow error RX_OVER_F(SC_SR[0]), transmit buffer overflow error TX_OVER_F(SC_SR[8]), receiver retry over limit error RX_OVER_REERR(SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR(SC_SR[30]).\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0_IE
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1_IE
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2_IE
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
TXBE_IE
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
SC_ISR
SC_ISR
SC Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ACON_ERR_IS
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGT_IS
\n
6
1
read-only
CD_IS
Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F(SC_SR[11]).\nNote: This field is the status flag of CD_INS_F(SC_SR[12]) or CD_REM_F(SC_TRSR[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INIT_IS
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN(SC_ALTCTL[3])), deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RDA_IS
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV (SC_CTL[7:6]). If software reads data from SC_RBR and receiver buffer data byte number is less than RX_FTRI_LEV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
RTMR_IS
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_RBR buffer,
9
1
read-only
TBE_IS
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to THR(SC_THR[7:0]) buffer and then this bit will be cleared automatically.
1
1
read-only
TERR_IS
Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_TRSR[5], parity error RX_EPA_F(SC_TRSR[4] and receiver buffer overflow error RX_OVER_F(SC_TRSR[0]), transmit buffer overflow error TX_OVER_F(SC_TRSR[8]), receiver retry over limit error RX_OVER_REERR(SC_TRSR[22] and transmitter retry over limit error TX_OVER_REERR(SC_TRSR[30]).\nNote: This field is the status flag of RX_EBR_F(SC_TRSR[6]), RX_EFR_F(SC_TRSR[5]), RX_EPA_F(SC_TRSR[4]), RX_OVER_F(SC_TRSR[0]), TX_OVER_F(SC_TRSR[8]), RX_OVER_REERR(SC_TRSR[22]) or TX_OVER_REERR(SC_TRSR[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0_IS
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1_IS
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2_IS
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCSR
SC_PINCSR
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
ADAC_CD_EN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU.
7
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CD_INS_F
Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only, but it can be cleared by writing "1" to it.\nNote2: The card detect engine will start after SC_CEN (SC_CTL[0] )set.
3
1
read-only
0
No effect
#0
1
Card insert
#1
CD_LEV
Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled
10
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CD_PIN_ST
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
4
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CD_REM_F
Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever a card has been removed.\nNote1: This bit is read only, but it can be cleared by writing "1" to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0] )set.
2
1
read-only
0
No effect
#0
1
Card removed
#1
CLK_KEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
POW_EN
SC_POW_EN Pin Signal\nSoftware can set POW_EN (SC_PINCSR[0]) and POW_INV (SC_PINCSR[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV (SC_PINCSR[11]) description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
POW_INV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by POW_INV(SC_PINCSR[11]) and POW_EN(SC_PINCSR[0]). POW_INV (SC_PINCSR[11]) is bit 1 and POW_EN(SC_PINCSR[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote: Software must select POW_INV (SC_PINCSR[11]) before Smart Card is enabled by SC_CEN (SC_CTL[0]).
11
1
read-write
SC_DATA_I_ST
SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DATA\n
16
1
read-only
0
The SC_DATA pin is low
#0
1
The SC_DATA pin is high
#1
SC_DATA_O
SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SC_DATA_O pin to low
#0
1
Drive SC_DATA_O pin to high
#1
SC_OEN_ST
SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n
8
1
read-only
0
The SC_DATA_OEN pin state at low
#0
1
The SC_DATA_OEN pin state at high
#1
SC_RST
SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SC_RST pin to low.\nSC_RST pin status is low
#0
1
Drive SC_RST pin to high.\nSC_RST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCSR register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCSR register
#0
1
Last value is synchronizing
#1
SC_RBR
SC_RBR
SC Receiving Buffer Register.
0x0
read-only
n
0x0
0x0
RBR
Receiving Buffer \nBy reading RBR, the SC will return an 8-bit received data.
0
8
read-only
SC_RFTMR
SC_RFTMR
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_TDRA
SC_TDRA
SC Timer Current Data Register A
0x38
read-only
n
0x0
0x0
TDR0
Timer0 Current Data Value(Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TDRB
SC_TDRB
SC Timer Current Data Register B
0x3C
read-only
n
0x0
0x0
TDR1
Timer1 Current Data Value(Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
TDR2
Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_THR
SC_THR
SC Transmit Holding Register
SC_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Buffer\nBy writing data to THR, the SC will send out an 8-bit data.\nNote: If SC_CEN(SC_CTL[0]) is not enabled, THR cannot be programmed.
0
8
write-only
SC_TMR0
SC_TMR0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT0
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
MODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer0
24
4
read-write
SC_TMR1
SC_TMR1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT1
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer1
24
4
read-write
SC_TMR2
SC_TMR2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT2
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.14.5.4 for programming Timer2
24
4
read-write
SC_TRSR
SC_TRSR
SC Status Register
0x20
read-write
n
0x0
0x0
RX_ATV
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RX_EBR_F
Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). .\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
RX_EFR_F
Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
RX_EMPTY_F
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RX_EPA_F
Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit".\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RX_FULL_F
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RX_OVER_F
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RX_OVER_REERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]), the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set RX_EPA_F(SC_TRSR[4])).
22
1
read-only
RX_POINT_F
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F(SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU, RX_POINT_F(SC_SR[17:16]) decreases one.
16
2
read-only
RX_REERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RX_ERETRY_EN (SC_CTL[19]) , the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set RX_EPA_F(SC_TRSR[4])).
21
1
read-only
TX_ATV
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TX_EMPTY_F
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR(SC_THR[7:0]) (TX buffer not empty).
9
1
read-only
TX_FULL_F
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TX_OVER_F
TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full, an additional write to THR(SC_THR[7:0]) will cause this bit be set to "1" by hardware. \nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TX_OVER_REERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TX_POINT_F
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
24
2
read-only
TX_REERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_UACTL
SC_UACTL
SC UART Mode Control Register.
0x34
read-write
n
0x0
0x0
DATA_LEN
Data Length\nNote: In smart card mode, this DATA_LEN must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBDIS bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBDIS
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UA_MODE_EN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
SC2
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACT_EN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
DACT_EN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST, and RX_RST at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INIT_SEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 679.\nWarm-reset: refer to Warm-Reset Sequence in Figure 680.\nDeactivation: refer to Deactivation Sequence in Figure 681.
8
2
read-write
OUTSEL
Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin (SC_DATA) output mode\n
16
1
read-write
0
Quasi mode
#0
1
Open-drain mode
#1
RX_BGT_EN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RX_RST
Rx Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TMR0_ATV
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
TMR0_SEN
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST and RX_RST at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
TMR1_ATV
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
TMR1_SEN
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
TMR2_ATV
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
TMR2_SEN
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]). So don't fill this bit, TX_RST(SC_ALTCTL[0]), and RX_RST(SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
TX_RST
TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARST_EN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST(SC_ALTCTL[0]) and RX_RST(SC_ALTCTL[1]), so don't fill this bit, TX_RST, and RX_RST at the same time.\nNote3: If SC_CEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTO_CON_EN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CON_SEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CD_DEB_SEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) SC peripheral clocks and de-bounce sample card removal once per 128 SC peripheral clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) SC peripheral clocks and de-bounce sample card removal once per 64 SC peripheral clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) SC peripheral clocks and de-bounce sample card removal once per 32 SC peripheral clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) SC peripheral clocks and de-bounce sample card removal once per 16 SC peripheral clocks
#11
CON_SEL
Convention Selection\nNote: If AUTO_CON_EN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
DIS_RX
RX Transition Disable Bit\nNote: If AUTO_CON_EN (SC_CTL[3])is enabled, these fields must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
DIS_TX
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
RX_ERETRY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RX_ERETRY_EN
RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RX_ERETRY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RX_FTRI_LEV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SC_CEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SLEN
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RX_ERETRY and TX_ERETRY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to RX_ERETRY and TX_ERETRY
#0
1
Last value is synchronizing
#1
TMR_SEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMR0 [23:0]. SC_TMR1 and SC_TMR2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1[7:0]. SC_TMR2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0]
#11
TX_ERETRY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TX_ERETRY_EN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_EGTR
SC_EGTR
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCR
SC_ETUCR
SC ETU Control Register
0x14
read-write
n
0x0
0x0
COMPEN_EN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETU_RDIV .\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETU_RDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_IER
SC_IER
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACON_ERR_IE
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGT_IE
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CD_IE
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F(SC_SR[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INIT_IE
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDA_IE
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RTMR_IE
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TERR_IE
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_SR[5]), parity error RX_EPA_F(SC_SR[4]), receiver buffer overflow error RX_OVER_F(SC_SR[0]), transmit buffer overflow error TX_OVER_F(SC_SR[8]), receiver retry over limit error RX_OVER_REERR(SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR(SC_SR[30]).\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0_IE
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1_IE
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2_IE
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
TXBE_IE
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
SC_ISR
SC_ISR
SC Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ACON_ERR_IS
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGT_IS
\n
6
1
read-only
CD_IS
Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F(SC_SR[11]).\nNote: This field is the status flag of CD_INS_F(SC_SR[12]) or CD_REM_F(SC_TRSR[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INIT_IS
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN(SC_ALTCTL[3])), deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RDA_IS
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV (SC_CTL[7:6]). If software reads data from SC_RBR and receiver buffer data byte number is less than RX_FTRI_LEV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
RTMR_IS
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_RBR buffer,
9
1
read-only
TBE_IS
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to THR(SC_THR[7:0]) buffer and then this bit will be cleared automatically.
1
1
read-only
TERR_IS
Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F(SC_SR[6]), frame error RX_EFR_F(SC_TRSR[5], parity error RX_EPA_F(SC_TRSR[4] and receiver buffer overflow error RX_OVER_F(SC_TRSR[0]), transmit buffer overflow error TX_OVER_F(SC_TRSR[8]), receiver retry over limit error RX_OVER_REERR(SC_TRSR[22] and transmitter retry over limit error TX_OVER_REERR(SC_TRSR[30]).\nNote: This field is the status flag of RX_EBR_F(SC_TRSR[6]), RX_EFR_F(SC_TRSR[5]), RX_EPA_F(SC_TRSR[4]), RX_OVER_F(SC_TRSR[0]), TX_OVER_F(SC_TRSR[8]), RX_OVER_REERR(SC_TRSR[22]) or TX_OVER_REERR(SC_TRSR[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0_IS
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1_IS
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2_IS
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCSR
SC_PINCSR
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
ADAC_CD_EN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU.
7
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CD_INS_F
Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only, but it can be cleared by writing "1" to it.\nNote2: The card detect engine will start after SC_CEN (SC_CTL[0] )set.
3
1
read-only
0
No effect
#0
1
Card insert
#1
CD_LEV
Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled
10
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CD_PIN_ST
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
4
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CD_REM_F
Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever a card has been removed.\nNote1: This bit is read only, but it can be cleared by writing "1" to it.\nNote2: Card detect engine will start after SC_CEN (SC_CTL[0] )set.
2
1
read-only
0
No effect
#0
1
Card removed
#1
CLK_KEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
POW_EN
SC_POW_EN Pin Signal\nSoftware can set POW_EN (SC_PINCSR[0]) and POW_INV (SC_PINCSR[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV (SC_PINCSR[11]) description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
POW_INV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by POW_INV(SC_PINCSR[11]) and POW_EN(SC_PINCSR[0]). POW_INV (SC_PINCSR[11]) is bit 1 and POW_EN(SC_PINCSR[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote: Software must select POW_INV (SC_PINCSR[11]) before Smart Card is enabled by SC_CEN (SC_CTL[0]).
11
1
read-write
SC_DATA_I_ST
SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DATA\n
16
1
read-only
0
The SC_DATA pin is low
#0
1
The SC_DATA pin is high
#1
SC_DATA_O
SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SC_DATA_O pin to low
#0
1
Drive SC_DATA_O pin to high
#1
SC_OEN_ST
SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n
8
1
read-only
0
The SC_DATA_OEN pin state at low
#0
1
The SC_DATA_OEN pin state at high
#1
SC_RST
SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SC_RST pin to low.\nSC_RST pin status is low
#0
1
Drive SC_RST pin to high.\nSC_RST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCSR register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCSR register
#0
1
Last value is synchronizing
#1
SC_RBR
SC_RBR
SC Receiving Buffer Register.
0x0
read-only
n
0x0
0x0
RBR
Receiving Buffer \nBy reading RBR, the SC will return an 8-bit received data.
0
8
read-only
SC_RFTMR
SC_RFTMR
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_TDRA
SC_TDRA
SC Timer Current Data Register A
0x38
read-only
n
0x0
0x0
TDR0
Timer0 Current Data Value(Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TDRB
SC_TDRB
SC Timer Current Data Register B
0x3C
read-only
n
0x0
0x0
TDR1
Timer1 Current Data Value(Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
TDR2
Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_THR
SC_THR
SC Transmit Holding Register
SC_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Buffer\nBy writing data to THR, the SC will send out an 8-bit data.\nNote: If SC_CEN(SC_CTL[0]) is not enabled, THR cannot be programmed.
0
8
write-only
SC_TMR0
SC_TMR0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT0
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
MODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer0
24
4
read-write
SC_TMR1
SC_TMR1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT1
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer1
24
4
read-write
SC_TMR2
SC_TMR2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT2
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.14.5.4 for programming Timer2
24
4
read-write
SC_TRSR
SC_TRSR
SC Status Register
0x20
read-write
n
0x0
0x0
RX_ATV
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RX_EBR_F
Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). .\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
RX_EFR_F
Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
RX_EMPTY_F
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RX_EPA_F
Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit".\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RX_ERETRY_EN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RX_FULL_F
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RX_OVER_F
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RX_OVER_REERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]), the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set RX_EPA_F(SC_TRSR[4])).
22
1
read-only
RX_POINT_F
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F(SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU, RX_POINT_F(SC_SR[17:16]) decreases one.
16
2
read-only
RX_REERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RX_ERETRY_EN (SC_CTL[19]) , the RX_EPA_F(SC_TRSR[4]) flag will be ignored (hardware will not set RX_EPA_F(SC_TRSR[4])).
21
1
read-only
TX_ATV
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TX_EMPTY_F
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR(SC_THR[7:0]) (TX buffer not empty).
9
1
read-only
TX_FULL_F
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TX_OVER_F
TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full, an additional write to THR(SC_THR[7:0]) will cause this bit be set to "1" by hardware. \nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TX_OVER_REERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TX_POINT_F
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
24
2
read-only
TX_REERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_UACTL
SC_UACTL
SC UART Mode Control Register.
0x34
read-write
n
0x0
0x0
DATA_LEN
Data Length\nNote: In smart card mode, this DATA_LEN must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBDIS bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBDIS
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UA_MODE_EN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
SCS
SYST_NVIC_SCS Register Map
SYST_NVIC_SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
1
1
read-write
VECTORKEY
Register Access Key\nWrite Operation:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead Operation:\nRead as 0xFA05.
16
16
read-write
CPUID
CPUID
CPUID Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
Implementer Code Assigned By ARM\n
24
8
read-only
PART
Architecture Of The Processor\nRead as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Part Number Of The Processor\nRead as 0xC20.
4
12
read-only
REVISION
Revision Number\nRead as 0x0
0
4
read-only
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI And Faults:\nThis bit is read only.
22
1
read-write
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
If Set, A Pending Exception Will Be Serviced On Exit From The Debug Halt State\nThis bit is read only.
23
1
read-write
NMIPENDSET
NMI Set-Pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception not pending
#0
1
Changes NMI exception state to pending.\nNMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-Pending Bit
Write Operation:
This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-Pending Bit\nWrite Operation:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-Pending Bit
Write Operation:
This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-Pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains The Active Exception Number\n
0
6
read-write
0
Thread mode
0
VECTPENDING
Indicates The Exception Number Of The Highest Priority Pending Enabled Exception:\n
12
6
read-write
0
No pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status is Disabled
0
1
Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Clear Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority Of IRQ0
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_1
Priority Of IRQ1
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_2
Priority Of IRQ2
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_3
Priority Of IRQ3
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority Of IRQ4
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_5
Priority Of IRQ5
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_6
Priority Of IRQ6
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_7
Priority Of IRQ7
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority Of IRQ10
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_11
Priority Of IRQ11
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
PRI_8
Priority Of IRQ8
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_9
Priority Of IRQ9
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority Of IRQ12
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_13
Priority Of IRQ13
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_14
Priority Of IRQ14
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority Of IRQ15
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority Of IRQ16
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_17
Priority Of IRQ17
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_18
Priority Of IRQ18
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_19
Priority Of IRQ19
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority Of IRQ20
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_21
Priority Of IRQ21
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_22
Priority Of IRQ22
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_23
Priority Of IRQ23
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority Of IRQ24
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_25
Priority Of IRQ25
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_26
Priority Of IRQ26
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_27
Priority Of IRQ27
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority Of IRQ28
0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_29
Priority Of IRQ29
0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_30
Priority Of IRQ30
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_31
Priority Of IRQ31
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current enable status.
0
32
read-write
0
No effect.\nAssociated interrupt status is Disabled
0
1
Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Set Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status.
0
32
read-write
0
No effect.\nAssociated interrupt in not in pending status
0
1
Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
1
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event On Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLEEPDEEP
Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n
2
1
read-write
0
Sleep mode
#0
1
Deep Sleep mode
#1
SLEEPONEXIT
Sleep-On-Exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application..
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter Sleep or Deep Sleep when returning from ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority Of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority Of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_15
Priority Of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection\n
2
1
read-write
0
Clock source is (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled\n
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled\n
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
FIFO
FIFO Mode EnableBit\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.\nAfter clearing this bit to 0, user must wait for at least 2 peripheral clock periods before setting this bit to 1 again.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt EnableBit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function EnableBit\nNote:\nByte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe Byte Reorder function is not supported when the variable bus clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode EnableBit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPI bus clock cycle.
12
4
read-write
TWOB
2-Bit Transfer Mode EnableBit\nNote: When 2-bit Transfer mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit Transfer mode Disabled
#0
1
2-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
VARCLK_EN
Variable Clock Enable Bit (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode EnableBit\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO, and SPIn_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt EnableBit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable Bit\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-Out Interrupt Enable Bit\n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable Bit (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPIn_SPISS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPIn_SPISS0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPIn_SPISS0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPIn_SPISS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPIn_SPISS0/1 is specified in SS_LVL. \nNote: SPIn_SPISS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPIn_SPISS0/1).\n
2
1
read-write
0
The slave select signal SPIn_SPISS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPIn_SPISS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote 1: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1.\nNote 2: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles since user wrote to this register.
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.
0
32
read-write
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
FIFO
FIFO Mode EnableBit\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.\nAfter clearing this bit to 0, user must wait for at least 2 peripheral clock periods before setting this bit to 1 again.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt EnableBit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function EnableBit\nNote:\nByte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe Byte Reorder function is not supported when the variable bus clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode EnableBit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPI bus clock cycle.
12
4
read-write
TWOB
2-Bit Transfer Mode EnableBit\nNote: When 2-bit Transfer mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit Transfer mode Disabled
#0
1
2-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
VARCLK_EN
Variable Clock Enable Bit (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode EnableBit\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO, and SPIn_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt EnableBit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable Bit\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-Out Interrupt Enable Bit\n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable Bit (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPIn_SPISS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPIn_SPISS0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPIn_SPISS0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPIn_SPISS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPIn_SPISS0/1 is specified in SS_LVL. \nNote: SPIn_SPISS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPIn_SPISS0/1).\n
2
1
read-write
0
The slave select signal SPIn_SPISS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPIn_SPISS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote 1: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1.\nNote 2: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles since user wrote to this register.
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.
0
32
read-write
SPI2
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
FIFO
FIFO Mode EnableBit\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.\nAfter clearing this bit to 0, user must wait for at least 2 peripheral clock periods before setting this bit to 1 again.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt EnableBit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function EnableBit\nNote:\nByte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe Byte Reorder function is not supported when the variable bus clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode EnableBit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPI bus clock cycle.
12
4
read-write
TWOB
2-Bit Transfer Mode EnableBit\nNote: When 2-bit Transfer mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit Transfer mode Disabled
#0
1
2-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
VARCLK_EN
Variable Clock Enable Bit (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode EnableBit\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO, and SPIn_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt EnableBit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable Bit\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-Out Interrupt Enable Bit\n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable Bit (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPIn_SPISS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPIn_SPISS0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPIn_SPISS0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPIn_SPISS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPIn_SPISS0/1 is specified in SS_LVL. \nNote: SPIn_SPISS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPIn_SPISS0/1).\n
2
1
read-write
0
The slave select signal SPIn_SPISS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPIn_SPISS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote 1: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1.\nNote 2: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles since user wrote to this register.
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.
0
32
read-write
SPI3
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
FIFO
FIFO Mode EnableBit\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.\nAfter clearing this bit to 0, user must wait for at least 2 peripheral clock periods before setting this bit to 1 again.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit And Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt EnableBit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function EnableBit\nNote:\nByte Reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe Byte Reorder function is not supported when the variable bus clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode EnableBit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI bus clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPI bus clock cycle.
12
4
read-write
TWOB
2-Bit Transfer Mode EnableBit\nNote: When 2-bit Transfer mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit Transfer mode Disabled
#0
1
2-bit Transfer mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
VARCLK_EN
Variable Clock Enable Bit (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Peripheral Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode EnableBit\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO, and SPIn_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt EnableBit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable Bit\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-Out Interrupt Enable Bit\n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable Bit (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPIn_SPISS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPIn_SPISS0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPIn_SPISS0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPIn_SPISS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPIn_SPISS0/1 is specified in SS_LVL. \nNote: SPIn_SPISS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPIn_SPISS0/1).\n
2
1
read-write
0
The slave select signal SPIn_SPISS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPIn_SPISS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote 1: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1.\nNote 2: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles since user wrote to this register.
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.
0
32
read-write
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP0
TCAP0
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.
0
24
read-only
TCAP1
TCAP1
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if user writes a new value into TCMP field.
0
24
read-write
TCMPR1
TCMPR1
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
read-write
n
0x0
0x0
CACT
Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1
#1
CTB
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IE
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag TIF (TISR[0]) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt function Disabled
#0
1
Timer Interrupt function Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
0
The Timer controller is operated in One-shot mode
#00
1
The Timer controller is operated in Periodic mode
#01
2
The Timer controller is operated in Toggle-output mode
#10
3
The Timer controller is operated in Continuous Counting mode
#11
PRESCALE
Prescale Counter\n
0
8
read-write
TDR_EN
Data Load Enable Bit\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while Timer counter is active
#1
WAKE_EN
Wake Up Function Enable Bit\n
23
1
read-write
0
Wake-up trigger event Disabled
#0
1
Wake-up trigger event Enabled
#1
TCSR1
TCSR1
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR register will be updated continuously to monitor 24-bit up counter value.
0
24
read-only
TDR1
TDR1
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON0
TEXCON0
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Timer External Capture Mode Selection\n
4
1
read-write
0
Transition on TMx_EXT pin is using to save the TDR value into TCAP.(event capture function)
#0
1
Transition on TMx_EXT pin is using to reset the 24-bit up counter.(event reset counter function)
#1
TCDB
Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXDB
Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT pin de-bounce Disabled
#0
1
TMx_EXT pin de-bounce Enabled
#1
TEXEN
Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n
3
1
read-write
0
RSTCAPSEL function of TMx_EXT pin will be ignored
#0
1
RSTCAPSEL function of TMx_EXT pin is active
#1
TEXIEN
Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
5
1
read-write
0
TMx_EXT pin detection Interrupt Disabled
#0
1
TMx_EXT pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Capture Pin Edge Detect Selection\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n
0
1
read-write
0
A falling edge of TMx_EXT pin will be counted
#0
1
A rising edge of TMx_EXT pin will be counted
#1
TEXCON1
TEXCON1
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR0
TEXISR0
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled, TMx_EXT pin selected as external capture function, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1]) setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
TMx_EXT pin interrupt did not occur
#0
1
TMx_EXT pin interrupt occurred
#1
TEXISR1
TEXISR1
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TDR value matches the TCMP value
#1
TWF
Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated
#1
TISR1
TISR1
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP2
TCAP2
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.
0
24
read-only
TCAP3
TCAP3
Timer3 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR2
TCMPR2
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if user writes a new value into TCMP field.
0
24
read-write
TCMPR3
TCMPR3
Timer3 Compare Register
0x24
read-write
n
0x0
0x0
TCSR2
TCSR2
Timer2 Control and Status Register
0x0
read-write
n
0x0
0x0
CACT
Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1
#1
CTB
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IE
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag TIF (TISR[0]) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt function Disabled
#0
1
Timer Interrupt function Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
0
The Timer controller is operated in One-shot mode
#00
1
The Timer controller is operated in Periodic mode
#01
2
The Timer controller is operated in Toggle-output mode
#10
3
The Timer controller is operated in Continuous Counting mode
#11
PRESCALE
Prescale Counter\n
0
8
read-write
TDR_EN
Data Load Enable Bit\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while Timer counter is active
#1
WAKE_EN
Wake Up Function Enable Bit\n
23
1
read-write
0
Wake-up trigger event Disabled
#0
1
Wake-up trigger event Enabled
#1
TCSR3
TCSR3
Timer3 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR2
TDR2
Timer2 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR register will be updated continuously to monitor 24-bit up counter value.
0
24
read-only
TDR3
TDR3
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON2
TEXCON2
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Timer External Capture Mode Selection\n
4
1
read-write
0
Transition on TMx_EXT pin is using to save the TDR value into TCAP.(event capture function)
#0
1
Transition on TMx_EXT pin is using to reset the 24-bit up counter.(event reset counter function)
#1
TCDB
Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXDB
Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT pin de-bounce Disabled
#0
1
TMx_EXT pin de-bounce Enabled
#1
TEXEN
Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.\n
3
1
read-write
0
RSTCAPSEL function of TMx_EXT pin will be ignored
#0
1
RSTCAPSEL function of TMx_EXT pin is active
#1
TEXIEN
Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
5
1
read-write
0
TMx_EXT pin detection Interrupt Disabled
#0
1
TMx_EXT pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Capture Pin Edge Detect Selection\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.\n
0
1
read-write
0
A falling edge of TMx_EXT pin will be counted
#0
1
A rising edge of TMx_EXT pin will be counted
#1
TEXCON3
TEXCON3
Timer3 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR2
TEXISR2
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled, TMx_EXT pin selected as external capture function, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1]) setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
TMx_EXT pin interrupt did not occur
#0
1
TMx_EXT pin interrupt occurred
#1
TEXISR3
TEXISR3
Timer3 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR2
TISR2
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TDR value matches the TCMP value
#1
TWF
Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated
#1
TISR3
TISR3
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n
0
4
read-write
LIN_RX_EN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable Bit\nRefer to Table 612 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal To 1\nRefer to Table 612 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
4
RX FIFO Interrupt Trigger Level is 30/14 bytes (High Speed/Normal Speed)
#0100
5
RX FIFO Interrupt Trigger Level is 46/14 bytes (High Speed/Normal Speed)
#0101
6
RX FIFO Interrupt Trigger Level is 62/14 bytes (High Speed/Normal Speed)
#0110
RFR
RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel)\nNote: This field is used for RTS auto-flow control.
16
4
read-write
0
RTS Trigger Level is 1 byte
#0000
1
RTS Trigger Level is 4 bytes
#0001
2
RTS Trigger Level is 8 bytes
#0010
3
RTS Trigger Level is 14 bytes
#0011
4
RTS Trigger Level is 30/14 bytes (High Speed/Normal Speed)
#0100
5
RTS Trigger Level is 46/14 bytes (High Speed/Normal Speed)
#0101
6
RTS Trigger Level is 62/14 bytes (High Speed/Normal Speed)
#0110
RX_DIS
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
0
Receiver detects a data that is not an address bit (bit 9 ='1')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it.
0
1
read-only
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2).
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing "1" to it.
24
1
read-only
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2).
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable Bit\n
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
BUF_ERR_INT Masked off
#0
1
BUF_ERR_INT Enabled
#1
DMA_RX_EN
RX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)\n
3
1
read-write
0
MODEM_INT Masked off
#0
1
MODEM_INT Enabled.
#1
RDA_IEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
RDA_INT Masked off
#0
1
RDA_INT Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable Bit\n
2
1
read-write
0
RLS_INT Masked off
#0
1
RLS_INT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
THRE_INT Masked off
#0
1
THRE_INT Enabled
#1
TIME_OUT_EN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOUT_IEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
TOUT_INT Masked off
#0
1
TOUT_INT Enabled
#1
WAKE_EN
UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
read-write
n
0x0
0x0
INV_RX
IrDA Inverse Receive Input Signal Control\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal
#1
INV_TX
IrDA Inverse Transmitting Output Signal Control\n
5
1
read-write
0
None inverse transmitting signal.
#0
1
Inverse transmitting output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5])is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared.
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated.0 = No buffer error interrupt flag is generated.\nBuffer error interrupt flag is generated
#1
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer maybe is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF (UA_FSR[24]]) and RX_OVER_IF (UA_FSR[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0]).
19
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1.\n
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
HW_TOUT_INT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]), LIN_BKDET_F(UA_LIN_SR[9]), BIT_ERR_F(UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared.
7
1
read-only
0
None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated
#0
1
At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated
#1
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLS_INT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
TOUT_INT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of "STOP Bit"\n
2
1
read-write
0
One " STOP bit" is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
0
Word length is 5-bit
#00
1
Word length is 6-bit
#01
2
Word length is 7-bit
#10
3
Word length is 8-bit
#11
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable Bit\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.13.5.8.4. (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.13.5.8.4. (Slave mode with automatic resynchronization).
3
1
read-write
0
UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable Bit\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This break field length is LIN_BKFL + 1.\n
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select\n
22
2
read-write
0
The LIN header includes "break field"
#00
1
The LIN header includes "break field" and "sync field"
#01
2
The LIN header includes "break field", "sync field" and "frame ID field"
#10
3
Reserved
#11
LIN_IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nIf the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
LIN Receiver Disable Bit\n
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
LIN_SHD
LIN TX Send Header Enable Bit\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".\n
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
No active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_MCR
UA_MCR
UART Modem Control Register
0x10
read-write
n
0x0
0x0
LEV_RTS
RTS Pin Active Level (Not Available In UART2 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 662 and Figure 663 for UART function mode.\nNote2: Refer to Figure 673 And Figure 674for RS-485 function mode.
9
1
read-write
0
RTS pin output is high level active
#0
1
RTS pin output is low level active
#1
RTS
RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel)\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
RTS signal is active
#0
1
RTS signal is inactive
#1
RTS_ST
RTS Pin State (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from RTS pin output of voltage logic status.\n
13
1
read-only
0
RTS pin output is low level voltage logic state
#0
1
RTS pin output is high level voltage logic state
#1
UA_MSR
UA_MSR
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected
4
1
read-only
0
CTS pin input is low level voltage logic state
#0
1
CTS pin input is high level voltage logic state
#1
DCTSF
Detect CTS State Change Flag (Read Only) (Not Available In UART2 Channel)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing "1" to it.
0
1
read-only
0
CTS input has not change state
#0
1
CTS input has change state
#1
LEV_CTS
CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 661 for more information
8
1
read-write
0
CTS pin input is high level active
#0
1
CTS pin input is low level active
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin.
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n
0
4
read-write
LIN_RX_EN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable Bit\nRefer to Table 612 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal To 1\nRefer to Table 612 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
4
RX FIFO Interrupt Trigger Level is 30/14 bytes (High Speed/Normal Speed)
#0100
5
RX FIFO Interrupt Trigger Level is 46/14 bytes (High Speed/Normal Speed)
#0101
6
RX FIFO Interrupt Trigger Level is 62/14 bytes (High Speed/Normal Speed)
#0110
RFR
RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel)\nNote: This field is used for RTS auto-flow control.
16
4
read-write
0
RTS Trigger Level is 1 byte
#0000
1
RTS Trigger Level is 4 bytes
#0001
2
RTS Trigger Level is 8 bytes
#0010
3
RTS Trigger Level is 14 bytes
#0011
4
RTS Trigger Level is 30/14 bytes (High Speed/Normal Speed)
#0100
5
RTS Trigger Level is 46/14 bytes (High Speed/Normal Speed)
#0101
6
RTS Trigger Level is 62/14 bytes (High Speed/Normal Speed)
#0110
RX_DIS
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
0
Receiver detects a data that is not an address bit (bit 9 ='1')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it.
0
1
read-only
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2).
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing "1" to it.
24
1
read-only
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2).
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable Bit\n
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
BUF_ERR_INT Masked off
#0
1
BUF_ERR_INT Enabled
#1
DMA_RX_EN
RX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)\n
3
1
read-write
0
MODEM_INT Masked off
#0
1
MODEM_INT Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
RDA_INT Masked off
#0
1
RDA_INT Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable Bit\n
2
1
read-write
0
RLS_INT Masked off
#0
1
RLS_INT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
THRE_INT Masked off
#0
1
THRE_INT Enabled
#1
TIME_OUT_EN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOUT_IEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
TOUT_INT Masked off
#0
1
TOUT_INT Enabled
#1
WAKE_EN
UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
read-write
n
0x0
0x0
INV_RX
IrDA Inverse Receive Input Signal Control\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal
#1
INV_TX
IrDA Inverse Transmitting Output Signal Control\n
5
1
read-write
0
None inverse transmitting signal
#0
1
Inverse transmitting output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5])is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared.
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated.0 = No buffer error interrupt flag is generated.\nBuffer error interrupt flag is generated
#1
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer maybe is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF (UA_FSR[24]]) and RX_OVER_IF (UA_FSR[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0]).
19
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1.\n
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
HW_TOUT_INT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]), LIN_BKDET_F(UA_LIN_SR[9]), BIT_ERR_F(UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared.
7
1
read-only
0
None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated
#0
1
At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated
#1
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLS_INT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
TOUT_INT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of "STOP Bit"\n
2
1
read-write
0
One " STOP bit" is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
0
Word length is 5-bit
#00
1
Word length is 6-bit
#01
2
Word length is 7-bit
#10
3
Word length is 8-bit
#11
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable Bit\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.13.5.8.4. (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.13.5.8.4. (Slave mode with automatic resynchronization).
3
1
read-write
0
UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable Bit\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This break field length is LIN_BKFL + 1.\n
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select\n
22
2
read-write
0
The LIN header includes "break field"
#00
1
The LIN header includes "break field" and "sync field"
#01
2
The LIN header includes "break field", "sync field" and "frame ID field"
#10
3
Reserved
#11
LIN_IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nIf the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
LIN Receiver Disable Bit\n
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
LIN_SHD
LIN TX Send Header Enable Bit\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".\n
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
No active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_MCR
UA_MCR
UART Modem Control Register
0x10
read-write
n
0x0
0x0
LEV_RTS
RTS Pin Active Level (Not Available In UART2 Channel)\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 662 and Figure 663 for UART function mode.\nNote2: Refer to Figure 673 And Figure 674for RS-485 function mode.
9
1
read-write
0
RTS pin output is high level active
#0
1
RTS pin output is low level active
#1
RTS
RTS (Request-To-Send) Signal Control (Not Available In UART2 Channel)\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
RTS signal is active
#0
1
RTS signal is inactive
#1
RTS_ST
RTS Pin State (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from RTS pin output of voltage logic status.\n
13
1
read-only
0
RTS pin output is low level voltage logic state
#0
1
RTS pin output is high level voltage logic state
#1
UA_MSR
UA_MSR
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTS_ST
CTS Pin Status (Read Only) (Not Available In UART2 Channel)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected
4
1
read-only
0
CTS pin input is low level voltage logic state
#0
1
CTS pin input is high level voltage logic state
#1
DCTSF
Detect CTS State Change Flag (Read Only) (Not Available In UART2 Channel)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing "1" to it.
0
1
read-only
0
CTS input has not change state
#0
1
CTS input has change state
#1
LEV_CTS
CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 661 for more information
8
1
read-write
0
CTS pin input is high level active
#0
1
CTS pin input is low level active
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin.
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART2
UART Register Map
UART
0x0
0x0
0x10
registers
n
0x18
0x24
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n
0
4
read-write
LIN_RX_EN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable Bit\nRefer to Table 612 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal To 1\nRefer to Table 612 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
4
RX FIFO Interrupt Trigger Level is 30/14 bytes (High Speed/Normal Speed)
#0100
5
RX FIFO Interrupt Trigger Level is 46/14 bytes (High Speed/Normal Speed)
#0101
6
RX FIFO Interrupt Trigger Level is 62/14 bytes (High Speed/Normal Speed)
#0110
RFR
RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel)\nNote: This field is used for RTS auto-flow control.
16
4
read-write
0
RTS Trigger Level is 1 byte
#0000
1
RTS Trigger Level is 4 bytes
#0001
2
RTS Trigger Level is 8 bytes
#0010
3
RTS Trigger Level is 14 bytes
#0011
4
RTS Trigger Level is 30/14 bytes (High Speed/Normal Speed)
#0100
5
RTS Trigger Level is 46/14 bytes (High Speed/Normal Speed)
#0101
6
RTS Trigger Level is 62/14 bytes (High Speed/Normal Speed)
#0110
RX_DIS
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
0
Receiver detects a data that is not an address bit (bit 9 ='1')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it.
0
1
read-only
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2).
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing "1" to it.
24
1
read-only
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2).
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable Bit\n
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable Bit (Not Available In UART2 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
BUF_ERR_INT Masked off
#0
1
BUF_ERR_INT Enabled
#1
DMA_RX_EN
RX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable Bit (Not Available In UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable Bit (Not Available In UART2 Channel)\n
3
1
read-write
0
MODEM_INT Masked off
#0
1
MODEM_INT Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
RDA_INT Masked off
#0
1
RDA_INT Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable Bit\n
2
1
read-write
0
RLS_INT Masked off
#0
1
RLS_INT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
THRE_INT Masked off
#0
1
THRE_INT Enabled
#1
TIME_OUT_EN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOUT_IEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
TOUT_INT Masked off
#0
1
TOUT_INT Enabled
#1
WAKE_EN
UART Wake-Up Function Enable Bit (Not Available In UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
read-write
n
0x0
0x0
INV_RX
IrDA Inverse Receive Input Signal Control\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal
#1
INV_TX
IrDA Inverse Transmitting Output Signal Control\n
5
1
read-write
0
None inverse transmitting signal
#0
1
Inverse transmitting output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5])is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared.
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated.0 = No buffer error interrupt flag is generated.\nBuffer error interrupt flag is generated
#1
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA__FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer maybe is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF (UA_FSR[24]]) and RX_OVER_IF (UA_FSR[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and HW_BUF_ERR_IF (UA_ISR[5])are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF(US_MSR[0]) is cleared by writing 1 on DCTSF (US_MSR[0]).
19
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3]) and HW_MODEM_IF(UA_ ISR[3]) are both set to 1.\n
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN (UA_IER[2])and HW_RLS_IF(UA_ISR[18]) are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
HW_TOUT_INT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4])and HW_TOUT_IF(UA_ISR[20]) are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F(UA_LIN_SR[0]), LIN_BKDET_F(UA_LIN_SR[9]), BIT_ERR_F(UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F(UA_LIN_SR[1]) all are cleared.
7
1
read-only
0
None of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated
#0
1
At least one of LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPERR_F and LINS_HERR_F is generated
#1
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLS_INT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
TOUT_INT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of "STOP Bit"\n
2
1
read-write
0
One " STOP bit" is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
0
Word length is 5-bit
#00
1
Word length is 6-bit
#01
2
Word length is 7-bit
#10
3
Word length is 8-bit
#11
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable Bit\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUD_M1 (UA_BAUD [29]) and BAUD_M0 (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.13.5.8.4. (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.13.5.8.4. (Slave mode with automatic resynchronization).
3
1
read-write
0
UA_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable Bit\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL, User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16].\nNote2: This break field length is LIN_BKFL + 1.\n
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select\n
22
2
read-write
0
The LIN header includes "break field"
#00
1
The LIN header includes "break field" and "sync field"
#01
2
The LIN header includes "break field", "sync field" and "frame ID field"
#10
3
Reserved
#11
LIN_IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nIf the parity generated by hardware, user fill ID0~ID5, (LIN_PID [29:24] )hardware will calculate P0 (LIN_PID[30]) and P1 (LIN_PID[31]), otherwise user must filled frame ID and parity in this field.\n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
LIN Receiver Disable Bit\n
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
LIN_SHD
LIN TX Send Header Enable Bit\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_SHD (UA_ALT_CSR [7]); user can read/write it by setting LIN_SHD (UA_ALT_CSR [7]) or LIN_SHD (UA_LIN_CTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check LIN_IDPEN (UA_LIN_CTL [9]), if hardware detect complete header ("break + sync + frame ID"), the LINS_HEDT_F will be set whether the frame ID correct or not.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".\n
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
No active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin.
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
USBD
USB Register Map
USB
0x0
0x0
0x1C
registers
n
0x500
0x80
registers
n
0x90
0x4
registers
n
USB_ATTR
USB_ATTR
USB Bus Status and Attribution Register
0x10
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection\n
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPU_EN
Pull-Up Resistor On USB_D+ Enable Bit\n
8
1
read-write
0
Pull-up resistor in USB_D+ pin Disabled
#0
1
Pull-up resistor in USB_D+ pin Enabled
#1
PHY_EN
PHY Transceiver Function Enable Bit\n
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-Down PHY Transceiver, Low Active\n
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn-on related circuit of PHY transceiver
#1
RESUME
Resume Status\nNote: This bit is read only.
2
1
read-write
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-Up\n
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up
#1
SUSPEND
Suspend Status\nNote: This bit is read only.
1
1
read-write
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
#1
TIMEOUT
Time-Out Status\nNote: This bit is read only.
3
1
read-write
0
No time-out
#0
1
No Bus response more than 18 bits time
#1
USBRST
USB Reset Status\nNote: This bit is read only.
0
1
read-write
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) is presented more than 2.5us
#1
USB_EN
USB Controller Enable Bit\n
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USB_BUFSEG0
USB_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x500
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
3
6
read-write
USB_BUFSEG1
USB_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x510
read-write
n
0x0
0x0
USB_BUFSEG2
USB_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x520
read-write
n
0x0
0x0
USB_BUFSEG3
USB_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x530
read-write
n
0x0
0x0
USB_BUFSEG4
USB_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x540
read-write
n
0x0
0x0
USB_BUFSEG5
USB_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x550
read-write
n
0x0
0x0
USB_BUFSEG6
USB_BUFSEG6
Endpoint 6 Buffer Segmentation Register
0x560
read-write
n
0x0
0x0
USB_BUFSEG7
USB_BUFSEG7
Endpoint 7 Buffer Segmentation Register
0x570
read-write
n
0x0
0x0
USB_CFG0
USB_CFG0
Endpoint 0 Configuration Register
0x508
read-write
n
0x0
0x0
CSTALL
Clear STALL Response\n
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQ_SYNC
Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EP_NUM
Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint.
0
4
read-write
ISOCH
Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint STATE\n
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
USB_CFG1
USB_CFG1
Endpoint 1 Configuration Register
0x518
read-write
n
0x0
0x0
USB_CFG2
USB_CFG2
Endpoint 2 Configuration Register
0x528
read-write
n
0x0
0x0
USB_CFG3
USB_CFG3
Endpoint 3 Configuration Register
0x538
read-write
n
0x0
0x0
USB_CFG4
USB_CFG4
Endpoint 4 Configuration Register
0x548
read-write
n
0x0
0x0
USB_CFG5
USB_CFG5
Endpoint 5 Configuration Register
0x558
read-write
n
0x0
0x0
USB_CFG6
USB_CFG6
Endpoint 6 Configuration Register
0x568
read-write
n
0x0
0x0
USB_CFG7
USB_CFG7
Endpoint 7 Configuration Register
0x578
read-write
n
0x0
0x0
USB_CFGP0
USB_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x50C
read-write
n
0x0
0x0
CLRRDY
Clear Ready\nWhen the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.\nFor IN token, write '1' to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\nThis bit is write 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL\n
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
USB_CFGP1
USB_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x51C
read-write
n
0x0
0x0
USB_CFGP2
USB_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x52C
read-write
n
0x0
0x0
USB_CFGP3
USB_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x53C
read-write
n
0x0
0x0
USB_CFGP4
USB_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x54C
read-write
n
0x0
0x0
USB_CFGP5
USB_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x55C
read-write
n
0x0
0x0
USB_CFGP6
USB_CFGP6
Endpoint 6 Set Stall and Clear In/Out Ready Control Register
0x56C
read-write
n
0x0
0x0
USB_CFGP7
USB_CFGP7
Endpoint 7 Set Stall and Clear In/Out Ready Control Register
0x57C
read-write
n
0x0
0x0
USB_DRVSE0
USB_DRVSE0
USB Drive SE0 Control Register
0x90
read-write
n
0x0
0x0
DRVSE0
Drive Single Ended Zero In USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.\n
0
1
read-write
0
None
#0
1
Force USB PHY transceiver to drive SE0
#1
USB_EPSTS
USB_EPSTS
USB Endpoint Status Register
0xC
read-only
n
0x0
0x0
EPSTS0
Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
8
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS1
Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
11
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS2
Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
14
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS3
Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
17
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS4
Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
20
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS5
Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
23
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS6
Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
26
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS7
Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
29
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
OVERRUN
Overrun\nIt indicates that the received data is over the maximum payload number or not.\n
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
USB_FADDR
USB_FADDR
USB Device Function Address Register
0x8
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
USB_FLDET
USB_FLDET
USB Floating Detection Register
0x14
read-only
n
0x0
0x0
FLDET
Device Floating Detected\n
0
1
read-only
0
Controller is not attached into the USB host
#0
1
Controller is attached into the BUS
#1
USB_INTEN
USB_INTEN
USB Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BUS_IE
Bus Event Interrupt Enable Bit\n
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
FLDET_IE
Floating Detection Interrupt Enable Bit\n
2
1
read-write
0
Floating detection Interrupt Disabled
#0
1
Floating detection Interrupt Enabled
#1
INNAK_EN
Active NAK Function And Its Status In IN Token\n
15
1
read-write
0
When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token
#1
USB_IE
USB Event Interrupt Enable Bit\n
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
WAKEUP_EN
Wake-Up Function Enable Bit\n
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
WAKEUP_IE
USB Wake-Up Interrupt Enable Bit\n
3
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
USB_INTSTS
USB_INTSTS
USB Interrupt Event Status Register
0x4
read-write
n
0x0
0x0
BUS_STS
BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status\n
16
1
read-write
0
No event occurred on endpoint 0
#0
1
USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status\n
17
1
read-write
0
No event occurred on endpoint 1
#0
1
USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status\n
18
1
read-write
0
No event occurred on endpoint 2
#0
1
USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status\n
19
1
read-write
0
No event occurred on endpoint 3
#0
1
USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status\n
20
1
read-write
0
No event occurred on endpoint 4
#0
1
USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status\n
21
1
read-write
0
No event occurred on endpoint 5
#0
1
USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1]
#1
EPEVT6
Endpoint 6's USB Event Status\n
22
1
read-write
0
No event occurred on endpoint 6
#0
1
USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1]
#1
EPEVT7
Endpoint 7's USB Event Status\n
23
1
read-write
0
No event occurred on endpoint 7
#0
1
USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1]
#1
FLDET_STS
Floating Detection Interrupt Status\n
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2]
#1
SETUP
Setup Event Status\n
31
1
read-write
0
No Setup event
#0
1
SETUP event occurred, cleared by write 1 to USB_INTSTS[31]
#1
USB_STS
USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS0~7 to know which kind of USB event occurred. Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31])
#1
WAKEUP_STS
Wake-Up Interrupt Status\n
3
1
read-write
0
No Wake-up event occurred
#0
1
Wake-up event occurred, cleared by write 1 to USB_INTSTS[3]
#1
USB_MXPLD0
USB_MXPLD0
Endpoint 0 Maximal Payload Register
0x504
read-write
n
0x0
0x0
MXPLD
Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
USB_MXPLD1
USB_MXPLD1
Endpoint 1 Maximal Payload Register
0x514
read-write
n
0x0
0x0
USB_MXPLD2
USB_MXPLD2
Endpoint 2 Maximal Payload Register
0x524
read-write
n
0x0
0x0
USB_MXPLD3
USB_MXPLD3
Endpoint 3 Maximal Payload Register
0x534
read-write
n
0x0
0x0
USB_MXPLD4
USB_MXPLD4
Endpoint 4 Maximal Payload Register
0x544
read-write
n
0x0
0x0
USB_MXPLD5
USB_MXPLD5
Endpoint 5 Maximal Payload Register
0x554
read-write
n
0x0
0x0
USB_MXPLD6
USB_MXPLD6
Endpoint 6 Maximal Payload Register
0x564
read-write
n
0x0
0x0
USB_MXPLD7
USB_MXPLD7
Endpoint 7 Maximal Payload Register
0x574
read-write
n
0x0
0x0
USB_STBUFSEG
USB_STBUFSEG
Setup Token Buffer Segmentation Register
0x18
read-write
n
0x0
0x0
STBUFSEG
Setup Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSB_SRAM address + {STBUFSEG[8:3], 3'b000} \nNote: It is used for SETUP token only.
3
6
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
read-write
n
0x0
0x0
DBGACK_WDT
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
WTE
Watchdog Timer Enable Bit (Write Protect)\nNote: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
WDT Disabled. (This action will reset the internal up counter value.)
#0
1
WDT Enabled
#1
WTIE
Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.\n
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
WTIF
Watchdog Timer Time-Out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
WTIS
Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\n
8
3
read-write
0
24 *TWDT
#000
1
26 * TWDT
#001
2
28 * TWDT
#010
3
210 * TWDT
#011
4
212 * TWDT
#100
5
214 * TWDT
#101
6
216 * TWDT
#110
7
218 * TWDT
#111
WTR
Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT up counter value
#1
WTRE
Watchdog Timer Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\n
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
WTRF
Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
WTWKE
Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WTWKF
Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
WTCRALT
WTCRALT
Watchdog Timer Alternative Control Register
0x4
read-write
n
0x0
0x0
WTRDSEL
Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. User can select a suitable value of WDT Reset Delay Period for different WDT time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nNote: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
Watchdog Timer Reset Delay Period is 1026 * WDT_CLK
#00
1
Watchdog Timer Reset Delay Period is 130 * WDT_CLK
#01
2
Watchdog Timer Reset Delay Period is 18 * WDT_CLK
#10
3
Watchdog Timer Reset Delay Period is 3 * WDT_CLK
#11
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
WWDTCR
WWDTCR
Window Watchdog Timer Control Register
0x4
read-write
n
0x0
0x0
DBGACK_WWDT
ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
PERIODSEL
WWDT Counter Prescale Period Selection\n
8
4
read-write
0
Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT
#0000
1
Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT
#0001
2
Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT
#0010
3
Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT
#0011
4
Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT
#0100
5
Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT
#0101
6
Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT
#0110
7
Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT
#0111
8
Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT
#1000
9
Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT
#1001
10
Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT
#1010
11
Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT
#1011
12
Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT
#1100
13
Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT
#1101
14
Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT
#1110
15
Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT
#1111
WINCMP
WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
16
6
read-write
WWDTEN
WWDT Enable Bit\nSet this bit to enable WWDT counter counting\n
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter is starting counting
#1
WWDTIE
WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
WWDTCVR
WWDTCVR
Window Watchdog Timer Counter Value Register
0xC
read-only
n
0x0
0x0
WWDTCVAL
WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value.
0
6
read-only
WWDTRLD
WWDTRLD
Window Watchdog Timer Reload Counter Register
0x0
write-only
n
0x0
0x0
WWDTRLD
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value is larger than WINCMP, WWDT reset signal will generate immediately.
0
32
write-only
WWDTSR
WWDTSR
Window Watchdog Timer Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches WINCMP value
#1
WWDTRF
WWDT Time-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1