nuvoTon
NUC400_v1
2024.04.28
NUC400_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0x14
registers
n
CTL0
ACMP_CTL0
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
ACMPEN
Comparator 0 Enable Bit\nNote: The comparator output needs to wait 2 us stable time after ACMPEN is set.
0
1
read-write
0
Comparator 0 Disabled
#0
1
Comparator 0 Enabled
#1
ACMPIE
Comparator 0 Interrupt Enable Bit\n
1
1
read-write
0
Comparator 0 interrupt Disabled
#0
1
Comparator 0 interrupt Enabled
#1
ACMPOINV
Comparator 0 Output Inverse\n
3
1
read-write
0
Comparator 0 output inverse Disabled
#0
1
Comparator 0 output inverse Enabled
#1
HYSEN
Comparator 0 Hysteresis Enable Bit\n
2
1
read-write
0
Comparator 0 hysteresis Disabled (Default)
#0
1
Comparator 0 hysteresis Enabled (typical range is 20 mV)
#1
NEGSEL
Comparator 0 Negative Input Selection\n
4
1
read-write
0
The source of comparator 0 negative input is from ACMP0_N pin
#0
1
The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 0 negative input
#1
POSSEL
Comparator 0 Positive Input Selection\nThe other options are reserved.
5
3
read-write
0
Input from ACMP0_P0
#000
1
Input from ACMP0_P1
#001
2
Input from ACMP0_P2
#010
3
Input from ACMP0_P3
#011
4
Input from OPA0
#100
CTL1
ACMP_CTL1
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
ACMPEN
Comparator 1 Enable Bit\nThe comparator output needs to wait 2 us stable time after ACMPEN is set.
0
1
read-write
0
Comparator 1 Disabled
#0
1
Comparator 1 Enabled
#1
ACMPIE
Comparator 1 Interrupt Enable Bit\n
1
1
read-write
0
Comparator 1 interrupt Disabled
#0
1
Comparator 1 interrupt Enabled
#1
ACMPOINV
Comparator 1 Output Inverse Control\n
3
1
read-write
0
Comparator 1 output inverse Disabled
#0
1
Comparator 1 output inverse Enabled
#1
HYSEN
Comparator 1 Hysteresis Enable Bit\n
2
1
read-write
0
Comparator 1 hysteresis Disabled (Default)
#0
1
Comparator 1 hysteresis Enabled (typical range is 20 mV)
#1
NEGSEL
Comparator 1 Negative Input Selection\n
4
1
read-write
0
The source of comparator 1 negative input is from ACMP1_N pin
#0
1
The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 1 negative input
#1
POSSEL
Comparator 1 Positive Input Selection\nThe other options are reserved.
5
3
read-write
0
Input from ACMP1_P0
#000
1
Input from ACMP1_P1
#001
2
Input from ACMP1_P2
#010
3
Input from ACMP1_P3
#011
4
Input from OPA1
#100
CTL2
ACMP_CTL2
Analog Comparator 2 Control Register
0x8
read-write
n
0x0
0x0
ACMPEN
Comparator 2 Enable Bit\nThe comparator output needs to wait 2 us stable time after ACMPEN is set.
0
1
read-write
0
Comparator 2 Disabled
#0
1
Comparator 2 Enabled
#1
ACMPIE
Comparator 2 Interrupt Enable Bit\n
1
1
read-write
0
Comparator 2 interrupt Disabled
#0
1
Comparator 2 interrupt Enabled
#1
ACMPOINV
Comparator 2 Output Inverse Control\n
3
1
read-write
0
Comparator 2 output inverse Disabled
#0
1
Comparator 2 output inverse Enabled
#1
HYSEN
Comparator 2 Hysteresis Enable Bit\n
2
1
read-write
0
Comparator 2 hysteresis Disabled (Default)
#0
1
Comparator 2 hysteresis Enabled (typical range is 20 mV)
#1
NEGSEL
Comparator 2 Negative Input Selection\n
4
1
read-write
0
The source of comparator 2 negative input is from ACMP2_N pin
#0
1
The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 2 negative input
#1
POSSEL
Comparator 2 Positive Input Selection\nThe other options are reserved.
5
3
read-write
0
Input from ACMP2_P0
#000
1
Input from ACMP2_P1
#001
2
Input from ACMP2_P2
#010
3
Input from ACMP2_P3
#011
STATUS
ACMP_STATUS
Analog Comparator Status Register
0xC
read-write
n
0x0
0x0
ACMPIF0
Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if ACMP_CTL0[1] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
ACMPIF1
Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if ACMP_CTL1[1] is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
ACMPIF2
Comparator 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state. This will cause an interrupt if ACMP_CTL2[1] is set to 1.\nWrite 1 to clear this bit to 0.
2
1
read-write
ACMPO0
Comparator 0 Output\n
3
1
read-write
ACMPO1
Comparator 1 Output\n
4
1
read-write
ACMPO2
Comparator 2 Output\n
5
1
read-write
VREF
ACMP_VREF
Analog Comparator Reference Voltage Control Register
0x10
read-write
n
0x0
0x0
CRVCTL
Comparator Reference Voltage Setting\n
0
4
read-write
CRVSSEL
CRV Source Voltage Selection\n
6
1
read-write
0
AVDD is selected as CRV source voltage
#0
1
Internal reference voltage is selected as CRV source voltage
#1
IREFSEL
Internal Reference Selection\n
7
1
read-write
0
Band-gap voltage is selected as internal reference
#0
1
CRV is selected as internal reference
#1
ADC
ADC Register Map
ADC
0x0
0x0
0x38
registers
n
0x40
0x18
registers
n
0x60
0x4
registers
n
CHEN
ADC_CHEN
ADC Channel Enable Control Register
0x44
read-write
n
0x0
0x0
ADBGEN
Internal Band-Gap Selection\nADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC
16
1
read-write
0
Internal band-gap is not selected to be the analog input source of ADC
#0
1
Internal band-gap is selected to be the analog input source of ADC
#1
ADTSEN
Internal Temperature Sensor Selection\nADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC.
17
1
read-write
0
Internal temperature sensor is not selected to be the analog input source of ADC
#0
1
Internal temperature sensor is selected to be the analog input source of ADC
#1
CHEN
Analog Input Channel Enable Bit\nSet CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11). If DIFFEN bit is set to 1, only the even number channels need to be enabled \n
0
12
read-write
0
ADC input channel Disabled
0
1
ADC input channel Enabled
1
CMP0
ADC_CMP0
ADC Compare Register 0
0x48
read-write
n
0x0
0x0
ADCMPEN
Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into ADC_DATx register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
ADCMPIE
Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE (ADC_CMPx[1])is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPCH
Compare Channel Selection\n
3
4
read-write
0
Channel 0 conversion result is selected to be compared
#0000
1
Channel 1 conversion result is selected to be compared
#0001
2
Channel 2 conversion result is selected to be compared
#0010
3
Channel 3 conversion result is selected to be compared
#0011
4
Channel 4 conversion result is selected to be compared
#0100
5
Channel 5 conversion result is selected to be compared
#0101
6
Channel 6 conversion result is selected to be compared
#0110
7
Channel 7 conversion result is selected to be compared
#0111
8
Channel 8 conversion result is selected to be compared
#1000
9
Channel 9 conversion result is selected to be compared
#1001
10
Channel 10 conversion result is selected to be compared
#1010
11
Channel 11 conversion result is selected to be compared
#1011
12
band-gap voltage result is selected to be compared
#1100
13
temperature sensor conversion result is selected to be compared
#1101
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one
#1
CMPDAT
Compared Data\nWhen DMOF (ADC_CTL[31]) bit is set to 0, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format. CMPDAT (ADC_CTL[27:16]) should be filled in unsigned format.\nWhen DMOF (ADC_CTL[31]) bit is set to 1, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with 2'complement format. CMPDAT (ADC_CTL[27:16]) should be filled in 2'complement format.
16
12
read-write
CMPMCNT
Compare Match Count\nWhen the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
8
4
read-write
CMP1
ADC_CMP1
ADC Compare Register 1
0x4C
read-write
n
0x0
0x0
CTL
ADC_CTL
ADC Control Register
0x40
read-write
n
0x0
0x0
ADCEN
ADC Enable Bit\nBefore disabling ADC clock, this bit should be cleared to 0 by software.
0
1
read-write
0
ADC analog circuit Disabled
#0
1
ADC analog circuit Enabled
#1
ADCIEN
ADC Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1.
1
1
read-write
0
ADC interrupt function Disabled
#0
1
ADC interrupt function Enabled
#1
DIFFEN
Differential Input Mode Enable Bit\nIn differential input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0]). The conversion result will be placed to the corresponding data register of the enabled channel.
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
ADC Differential Input Mode Output Format\n
31
1
read-write
0
A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with unsigned format
#0
1
A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with 2'complement format
#1
HWTRGCOND
External Pin Trigger Conditions\nThese two bits decide external pin (STADC) trigger event. The signal must be kept at stable state at least 8 system clocks for level trigger and 4 system clocks at high and low state for edge trigger.\n
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
HWTRGEN
External Hardware Trigger Enable Bit\nEnable or disable hardware triggering of A/D conversion. The hardware trigger source include external pin (STADC) or PWM trigger which is controlled by HWTRGSEL (ADC_CTL[5:4]) register.\nADC hardware trigger function is only supported in single-cycle scan mode.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
HWTRGSEL
External Hardware Trigger Source\nSoftware should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]).\nIn hardware trigger mode, the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source.
4
2
read-write
0
A/D conversion is started by external pin (STADC)
#00
1
Reserved
#01
2
Reserved
#10
3
PWM0 or PWM1 trigger condition is matched
#11
OPMODE
ADC Operation Mode\nWhen changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
PDMAEN
PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request.\nWhen PDMAEN (ADC_CTL[9]) is set to 1, software must set ADCIEN (ADC_CTL[1]) bit to 0 to disable interrupt.
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADC_DATx Enabled
#1
PWMTRGDLY
PWM Trigger Delay Time\nSetting this field will delay ADC start conversion time after PWM trigger comes.\nPWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16])
16
8
read-write
SWTRG
A/D Conversion Start\nThe SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger. The SWTRG (ADC_CTL[11]) bit will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
11
1
read-write
0
Conversion stopped and A/D converter enter idle state
#0
1
Conversion start
#1
CURDAT
ADC_CURDAT
ADC PDMA Current Transfer Data Register
0x60
read-only
n
0x0
0x0
CURDAT
ADC PDMA Current Transfer Data Bit (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.
0
18
read-only
DAT0
ADC_DAT0
ADC Data Register 0
0x0
read-only
n
0x0
0x0
OV
Overrun Flag (Read Only)\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone. It is cleared by hardware after ADC_DAT register is read.
16
1
read-only
0
Data in RESULT (ADC_DATx[15:0]) is recent conversion result
#0
1
Data in RESULT (ADC_DATx[15:0]) is overwrite
#1
RESULT
A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF (ADC_CTL[31]) bit is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF (ADC_CTL[31]) bit set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
0
16
read-only
VALID
Valid Flag (Read Only)\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
17
1
read-only
0
Data in RESULT (ADC_DATx[15:0]) bits is not valid
#0
1
Data in RESULT (ADC_DATx[15:0]) bits is valid
#1
DAT1
ADC_DAT1
ADC Data Register 1
0x4
read-write
n
0x0
0x0
DAT10
ADC_DAT10
ADC Data Register 10
0x28
read-write
n
0x0
0x0
DAT11
ADC_DAT11
ADC Data Register 11
0x2C
read-write
n
0x0
0x0
DAT12
ADC_DAT12
ADC Data Register 12 (for Band-gap Voltage)
0x30
read-write
n
0x0
0x0
DAT13
ADC_DAT13
ADC Data Register 13 (for Temperature Sensor)
0x34
read-write
n
0x0
0x0
DAT2
ADC_DAT2
ADC Data Register 2
0x8
read-write
n
0x0
0x0
DAT3
ADC_DAT3
ADC Data Register 3
0xC
read-write
n
0x0
0x0
DAT4
ADC_DAT4
ADC Data Register 4
0x10
read-write
n
0x0
0x0
DAT5
ADC_DAT5
ADC Data Register 5
0x14
read-write
n
0x0
0x0
DAT6
ADC_DAT6
ADC Data Register 6
0x18
read-write
n
0x0
0x0
DAT7
ADC_DAT7
ADC Data Register 7
0x1C
read-write
n
0x0
0x0
DAT8
ADC_DAT8
ADC Data Register 8
0x20
read-write
n
0x0
0x0
DAT9
ADC_DAT9
ADC Data Register 9
0x24
read-write
n
0x0
0x0
STATUS0
ADC_STATUS0
ADC Status Register 0
0x50
read-write
n
0x0
0x0
ADCMPF0
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n
1
1
read-write
0
Conversion result in ADC_DATx does not meet ADCMPR0 setting
#0
1
Conversion result in ADC_DATx meets ADCMPR0 setting
#1
ADCMPF1
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n
2
1
read-write
0
Conversion result in ADC_DATx does not meet ADCMPR1 setting
#0
1
Conversion result in ADC_DATx meets ADCMPR1 setting
#1
ADIF
ADC Interrupt Flag\nA status flag that indicates the end of A/D conversion.\nADIF (ADC_STATUS0[0]) is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode\n2. When A/D conversion ends on all specified channels in Scan mode\nNote: This flag can be cleared by writing 1 to it.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG (ADC_CTL[11]) bit.
3
1
read-only
0
ADC is in idle state
#0
1
ADC is doing conversion
#1
CHANNEL
Current Conversion Channel (Read Only)\n
4
4
read-only
STATUS1
ADC_STATUS1
ADC Status Register 1
0x54
read-only
n
0x0
0x0
OV
Overrun Flag (Read Only)\nIt is a mirror to OV (ADC_DATx[16]) bit.
16
14
read-only
VALID
Data Valid Flag (Read Only)\nIt is a mirror of VALID (ADC_DATx[17]) bit.
0
14
read-only
CAN0
CAN Register Map
CAN
0x0
0x0
0x1C
registers
n
0x100
0x8
registers
n
0x120
0x8
registers
n
0x140
0x8
registers
n
0x160
0x10
registers
n
0x20
0x2C
registers
n
0x80
0x2C
registers
n
CAN_BRPE
CAN_BRPE
Baud Rate Prescaler Extension Register
0x18
read-write
n
0x0
0x0
BRPE
BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
0
4
read-write
CAN_BTIME
CAN_BTIME
Bit Timing Register
0xC
-1
read-write
n
0x0
0x0
BRP
Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
0
6
read-write
SJW
(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
6
2
read-write
TSeg1
Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
8
4
read-write
TSeg2
Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
12
3
read-write
CAN_CON
CAN_CON
Control Register
0x0
-1
read-write
n
0x0
0x0
CCE
Configuration Change Enable Bit\n
6
1
read-write
0
No write access to the Bit Timing Register
#0
1
Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1)
#1
DAR
Automatic Re-Transmission Disable Bit\n
5
1
read-write
0
Automatic Retransmission of disturbed messages enabled
#0
1
Automatic Retransmission disabled
#1
EIE
Error Interrupt Enable Bit\n
3
1
read-write
0
Disabled - No Error Status Interrupt will be generated
#0
1
Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt
#1
IE
Module Interrupt Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
Init
Init Initialization\n
0
1
read-write
0
Normal Operation
#0
1
Initialization is started
#1
SIE
Status Change Interrupt Enable Bit\n
2
1
read-write
0
Disabled - No Status Change Interrupt will be generated
#0
1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
#1
Test
Test Mode Enable Bit\n
7
1
read-write
0
Normal Operation
#0
1
Test Mode
#1
CAN_ERR
CAN_ERR
Error Counter Register
0x8
read-only
n
0x0
0x0
REC
Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
8
7
read-only
RP
Receive Error Passive\n
15
1
read-only
0
The Receive Error Counter is below the error passive level
#0
1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
#1
TEC
Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
0
8
read-only
CAN_IF1_ARB1
CAN_IF1_ARB1
IF1 Arbitration 1 Register
0x30
read-write
n
0x0
0x0
ID
Message Identifier 15-0
ID28 - ID0, 29-bit Identifier ( Extended Frame ).
ID28 - ID18, 11-bit Identifier ( Standard Frame )
0
16
read-write
CAN_IF1_ARB2
CAN_IF1_ARB2
IF1 Arbitration 2 Register
0x34
read-write
n
0x0
0x0
Dir
Message Direction\n
13
1
read-write
0
Direction is receive
#0
1
Direction is transmit
#1
ID
Message Identifier 28-16
ID28 - ID0, 29-bit Identifier ( Extended Frame ).
ID28 - ID18, 11-bit Identifier ( Standard Frame )
0
13
read-write
MsgVal
Message Valid
Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
15
1
read-write
0
The Message Object is ignored by the Message Handler
#0
1
The Message Object is configured and should be considered by the Message Handler
#1
Xtd
Extended Identifier\n
14
1
read-write
0
The 11-bit ( standard ) Identifier will be used for this Message Object
#0
1
The 29-bit ( extended ) Identifier will be used for this Message Object
#1
CAN_IF1_CMASK
CAN_IF1_CMASK
IF1 Command Mask Register
0x24
read-write
n
0x0
0x0
Arb
Access Arbitration Bits\nWrite Operation:\n
5
1
read-write
0
Arbitration bits unchanged
#0
1
Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
#1
ClrIntPnd
Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation:\n
3
1
read-write
0
IntPnd bit (CAN_IFn_MCON[13]) remains unchanged
#0
1
Clear IntPnd bit in the Message Object
#1
Control
Control Access Control Bits\nWrite Operation:\n
4
1
read-write
0
Control Bits unchanged
#0
1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
#1
DAT_A
Access Data Bytes [3:0]\nWrite Operation:\n
1
1
read-write
0
Data Bytes [3:0] unchanged
#0
1
Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
#1
DAT_B
Access Data Bytes [7:4]\nWrite Operation: \n
0
1
read-write
0
Data Bytes [7:4] unchanged
#0
1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
#1
Mask
Access Mask Bits\nWrite Operation:\n
6
1
read-write
0
Mask bits unchanged
#0
1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
#1
TxRqst_NewDat
Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
2
1
read-write
0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#0
1
Set TxRqst bit.\nClear NewDat bit in the Message Object
#1
WR_RD
Write / Read Mode\n
7
1
read-write
0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#0
1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
#1
CAN_IF1_CREQ
CAN_IF1_CREQ
IF1 Command Request Register
0x20
-1
read-write
n
0x0
0x0
Busy
Busy Flag\n
15
1
read-write
0
Read/write action has finished
#0
1
Writing to the IFn Command Request Register is in progress. This bit can only be read by the software
#1
MessageNumber
Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
0
6
read-write
CAN_IF1_DAT_A1
CAN_IF1_DAT_A1
IF1 Data A1 Register
0x3C
read-write
n
0x0
0x0
Data0
Data Byte 0\n1st data byte of a CAN Data Frame
0
8
read-write
Data1
Data Byte 1\n2nd data byte of a CAN Data Frame
8
8
read-write
CAN_IF1_DAT_A2
CAN_IF1_DAT_A2
IF1 Data A2 Register
0x40
read-write
n
0x0
0x0
Data2
Data Byte 2\n3rd data byte of CAN Data Frame
0
8
read-write
Data3
Data Byte 3\n4th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B1
CAN_IF1_DAT_B1
IF1 Data B1 Register
0x44
read-write
n
0x0
0x0
Data4
Data Byte 4\n5th data byte of CAN Data Frame
0
8
read-write
Data5
Data Byte 5\n6th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B2
CAN_IF1_DAT_B2
IF1 Data B2 Register
0x48
read-write
n
0x0
0x0
Data6
Data Byte 6\n7th data byte of CAN Data Frame.
0
8
read-write
Data7
Data Byte 7\n8th data byte of CAN Data Frame.
8
8
read-write
CAN_IF1_MASK1
CAN_IF1_MASK1
IF1 Mask 1 Register
0x28
-1
read-write
n
0x0
0x0
Msk
Identifier Mask 15-0\n
0
16
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
CAN_IF1_MASK2
CAN_IF1_MASK2
IF1 Mask 2 Register
0x2C
-1
read-write
n
0x0
0x0
MDir
Mask Message Direction\n
14
1
read-write
0
The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering
#0
1
The message direction bit (Dir) is used for acceptance filtering
#1
Msk
Identifier Mask 28-16\n
0
13
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
MXtd
Mask Extended Identifier
Note: When 11-bit ( standard ) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
15
1
read-write
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#0
1
The extended identifier bit (IDE) is used for acceptance filtering
#1
CAN_IF1_MCON
CAN_IF1_MCON
IF1 Message Control Register
0x38
read-write
n
0x0
0x0
DLC
Data Length Code
0-8: Data Frame has 0-8 data bytes.
9-15: Data Frame has 8 data bytes
Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
Data 0: 1st data byte of a CAN Data Frame
Data 1: 2nd data byte of a CAN Data Frame
Data 2: 3rd data byte of a CAN Data Frame
Data 3: 4th data byte of a CAN Data Frame
Data 4: 5th data byte of a CAN Data Frame
Data 5: 6th data byte of a CAN Data Frame
Data 6: 7th data byte of a CAN Data Frame
Data 7 : 8th data byte of a CAN Data Frame
Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. I f the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
0
4
read-write
EoB
End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
7
1
read-write
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#0
1
Single Message Object or last Message Object of a FIFO Buffer
#1
IntPnd
Interrupt Pending\n
13
1
read-write
0
This message object is not the source of an interrupt
#0
1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
#1
MsgLst
None
14
1
read-write
0
No message lost since last time this bit was reset by the CPU
#0
1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
#1
NewDat
New Data\n
15
1
read-write
0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
#1
RmtEn
Remote Enable Bit\n
9
1
read-write
0
At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged
#0
1
At the reception of a Remote Frame, TxRqst is set
#1
RxIE
Receive Interrupt Enable Bit\n
10
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame
#0
1
IntPnd will be set after a successful reception of a frame
#1
TxIE
Transmit Interrupt Enable Bit\n
11
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame
#0
1
IntPnd will be set after a successful transmission of a frame
#1
TxRqst
Transmit Request\n
8
1
read-write
0
This Message Object is not waiting for transmission
#0
1
The transmission of this Message Object is requested and is not yet done
#1
UMask
Use Acceptance Mask
Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
12
1
read-write
0
Mask ignored
#0
1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
#1
CAN_IF2_ARB1
CAN_IF2_ARB1
IF2 Arbitration 1 Register
0x90
read-write
n
0x0
0x0
CAN_IF2_ARB2
CAN_IF2_ARB2
IF2 Arbitration 2 Register
0x94
read-write
n
0x0
0x0
CAN_IF2_CMASK
CAN_IF2_CMASK
IF2 Command Mask Register
0x84
read-write
n
0x0
0x0
CAN_IF2_CREQ
CAN_IF2_CREQ
IF2 Command Request Register
0x80
read-write
n
0x0
0x0
CAN_IF2_DAT_A1
CAN_IF2_DAT_A1
IF2 Data A1 Register
0x9C
read-write
n
0x0
0x0
CAN_IF2_DAT_A2
CAN_IF2_DAT_A2
IF2 Data A2 Register
0xA0
read-write
n
0x0
0x0
CAN_IF2_DAT_B1
CAN_IF2_DAT_B1
IF2 Data B1 Register
0xA4
read-write
n
0x0
0x0
CAN_IF2_DAT_B2
CAN_IF2_DAT_B2
IF2 Data B2 Register
0xA8
read-write
n
0x0
0x0
CAN_IF2_MASK1
CAN_IF2_MASK1
IF2 Mask 1 Register
0x88
read-write
n
0x0
0x0
CAN_IF2_MASK2
CAN_IF2_MASK2
IF2 Mask 2 Register
0x8C
read-write
n
0x0
0x0
CAN_IF2_MCON
CAN_IF2_MCON
IF2 Message Control Register
0x98
read-write
n
0x0
0x0
CAN_IIDR
CAN_IIDR
Interrupt Identifier Register
0x10
read-only
n
0x0
0x0
IntId
Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit. The Status Interrupt is cleared by reading the Status Register.
0
16
read-only
CAN_IPND1
CAN_IPND1
Interrupt Pending Register 1
0x140
read-only
n
0x0
0x0
IntPnd16_1
Interrupt Pending Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_IPND2
CAN_IPND2
Interrupt Pending Register 2
0x144
read-only
n
0x0
0x0
IntPnd32_17
Interrupt Pending Bits 32-17(Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_MVLD1
CAN_MVLD1
Message Valid Register 1
0x160
read-only
n
0x0
0x0
MsgVal16_1
Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_MVLD2
CAN_MVLD2
Message Valid Register 2
0x164
read-only
n
0x0
0x0
MsgVal32_17
Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_NDAT1
CAN_NDAT1
New Data Register 1
0x120
read-only
n
0x0
0x0
NewData16_1
New Data Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_NDAT2
CAN_NDAT2
New Data Register 2
0x124
read-only
n
0x0
0x0
NewData32_17
New Data Bits 32-17 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_STATUS
CAN_STATUS
Status Register
0x4
read-write
n
0x0
0x0
BOff
Bus-Off Status (Read Only) \n
7
1
read-only
0
The CAN module is not in bus-off state
#0
1
The CAN module is in bus-off state
#1
EPass
Error Passive (Read Only)\n
5
1
read-only
0
The CAN Core is error active
#0
1
The CAN Core is in the error passive state as defined in the CAN Specification
#1
EWarn
Error Warning Status (Read Only)\n
6
1
read-only
0
Both error counters are below the error warning limit of 96
#0
1
At least one of the error counters in the EML has reached the error warning limit of 96
#1
LEC
Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. The following table describes the error code.
0
3
read-write
RxOK
Received A Message Successfully\n
4
1
read-write
0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#0
1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
#1
TxOK
Transmitted A Message Successfully\n
3
1
read-write
0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#0
1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
#1
CAN_TEST
CAN_TEST
Test Register
0x14
read-write
n
0x0
0x0
Basic
Basic Mode\n
2
1
read-write
0
Basic Mode disabled
#0
1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
#1
LBack
Loop Back Mode Enable Bit\n
4
1
read-write
0
Loop Back Mode is disabled
#0
1
Loop Back Mode is enabled
#1
Res
Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
0
2
read-write
Rx
Monitors The Actual Value Of CAN_RX Pin (Read Only) *(1)\n
7
1
read-only
0
The CAN bus is dominant (CAN_RX = '0')
#0
1
The CAN bus is recessive (CAN_RX = '1')
#1
Silent
Silent Mode\n
3
1
read-write
0
Normal operation
#0
1
The module is in Silent Mode
#1
Tx
Tx[1:0]: Control Of CAN_TX Pin\n
5
2
read-write
0
Reset value, CAN_TX pin is controlled by the CAN Core
#00
1
Sample Point can be monitored at CAN_TX pin
#01
2
CAN_TX pin drives a dominant ('0') value
#10
3
CAN_TX pin drives a recessive ('1') value
#11
CAN_TXREQ1
CAN_TXREQ1
Transmission Request Register 1
0x100
read-only
n
0x0
0x0
TxRqst16_1
Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_TXREQ2
CAN_TXREQ2
Transmission Request Register 2
0x104
read-only
n
0x0
0x0
TxRqst32_17
Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_WU_EN
CAN_WU_EN
Wake-up Enable Control Register
0x168
read-write
n
0x0
0x0
WAKUP_EN
Wake-Up Enable Bit\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin..
0
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
CAN_WU_STATUS
CAN_WU_STATUS
Wake-up Status Register
0x16C
read-write
n
0x0
0x0
WAKUP_STS
Wake-Up Status \nNote: This bit can be cleared by writing '0'.
0
1
read-write
0
No wake-up event occurred
#0
1
Wake-up event occurred
#1
CAN1
CAN Register Map
CAN
0x0
0x0
0x1C
registers
n
0x100
0x8
registers
n
0x120
0x8
registers
n
0x140
0x8
registers
n
0x160
0x10
registers
n
0x20
0x2C
registers
n
0x80
0x2C
registers
n
CAN_BRPE
CAN_BRPE
Baud Rate Prescaler Extension Register
0x18
read-write
n
0x0
0x0
BRPE
BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
0
4
read-write
CAN_BTIME
CAN_BTIME
Bit Timing Register
0xC
-1
read-write
n
0x0
0x0
BRP
Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
0
6
read-write
SJW
(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
6
2
read-write
TSeg1
Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
8
4
read-write
TSeg2
Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
12
3
read-write
CAN_CON
CAN_CON
Control Register
0x0
-1
read-write
n
0x0
0x0
CCE
Configuration Change Enable Bit\n
6
1
read-write
0
No write access to the Bit Timing Register
#0
1
Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1)
#1
DAR
Automatic Re-Transmission Disable Bit\n
5
1
read-write
0
Automatic Retransmission of disturbed messages enabled
#0
1
Automatic Retransmission disabled
#1
EIE
Error Interrupt Enable Bit\n
3
1
read-write
0
Disabled - No Error Status Interrupt will be generated
#0
1
Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt
#1
IE
Module Interrupt Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
Init
Init Initialization\n
0
1
read-write
0
Normal Operation
#0
1
Initialization is started
#1
SIE
Status Change Interrupt Enable Bit\n
2
1
read-write
0
Disabled - No Status Change Interrupt will be generated
#0
1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
#1
Test
Test Mode Enable Bit\n
7
1
read-write
0
Normal Operation
#0
1
Test Mode
#1
CAN_ERR
CAN_ERR
Error Counter Register
0x8
read-only
n
0x0
0x0
REC
Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
8
7
read-only
RP
Receive Error Passive\n
15
1
read-only
0
The Receive Error Counter is below the error passive level
#0
1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
#1
TEC
Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
0
8
read-only
CAN_IF1_ARB1
CAN_IF1_ARB1
IF1 Arbitration 1 Register
0x30
read-write
n
0x0
0x0
ID
Message Identifier 15-0
ID28 - ID0, 29-bit Identifier ( Extended Frame ).
ID28 - ID18, 11-bit Identifier ( Standard Frame )
0
16
read-write
CAN_IF1_ARB2
CAN_IF1_ARB2
IF1 Arbitration 2 Register
0x34
read-write
n
0x0
0x0
Dir
Message Direction\n
13
1
read-write
0
Direction is receive
#0
1
Direction is transmit
#1
ID
Message Identifier 28-16
ID28 - ID0, 29-bit Identifier ( Extended Frame ).
ID28 - ID18, 11-bit Identifier ( Standard Frame )
0
13
read-write
MsgVal
Message Valid
Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
15
1
read-write
0
The Message Object is ignored by the Message Handler
#0
1
The Message Object is configured and should be considered by the Message Handler
#1
Xtd
Extended Identifier\n
14
1
read-write
0
The 11-bit ( standard ) Identifier will be used for this Message Object
#0
1
The 29-bit ( extended ) Identifier will be used for this Message Object
#1
CAN_IF1_CMASK
CAN_IF1_CMASK
IF1 Command Mask Register
0x24
read-write
n
0x0
0x0
Arb
Access Arbitration Bits\nWrite Operation:\n
5
1
read-write
0
Arbitration bits unchanged
#0
1
Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
#1
ClrIntPnd
Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation:\n
3
1
read-write
0
IntPnd bit (CAN_IFn_MCON[13]) remains unchanged
#0
1
Clear IntPnd bit in the Message Object
#1
Control
Control Access Control Bits\nWrite Operation:\n
4
1
read-write
0
Control Bits unchanged
#0
1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
#1
DAT_A
Access Data Bytes [3:0]\nWrite Operation:\n
1
1
read-write
0
Data Bytes [3:0] unchanged
#0
1
Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
#1
DAT_B
Access Data Bytes [7:4]\nWrite Operation: \n
0
1
read-write
0
Data Bytes [7:4] unchanged
#0
1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
#1
Mask
Access Mask Bits\nWrite Operation:\n
6
1
read-write
0
Mask bits unchanged
#0
1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
#1
TxRqst_NewDat
Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
2
1
read-write
0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#0
1
Set TxRqst bit.\nClear NewDat bit in the Message Object
#1
WR_RD
Write / Read Mode\n
7
1
read-write
0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#0
1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
#1
CAN_IF1_CREQ
CAN_IF1_CREQ
IF1 Command Request Register
0x20
-1
read-write
n
0x0
0x0
Busy
Busy Flag\n
15
1
read-write
0
Read/write action has finished
#0
1
Writing to the IFn Command Request Register is in progress. This bit can only be read by the software
#1
MessageNumber
Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
0
6
read-write
CAN_IF1_DAT_A1
CAN_IF1_DAT_A1
IF1 Data A1 Register
0x3C
read-write
n
0x0
0x0
Data0
Data Byte 0\n1st data byte of a CAN Data Frame
0
8
read-write
Data1
Data Byte 1\n2nd data byte of a CAN Data Frame
8
8
read-write
CAN_IF1_DAT_A2
CAN_IF1_DAT_A2
IF1 Data A2 Register
0x40
read-write
n
0x0
0x0
Data2
Data Byte 2\n3rd data byte of CAN Data Frame
0
8
read-write
Data3
Data Byte 3\n4th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B1
CAN_IF1_DAT_B1
IF1 Data B1 Register
0x44
read-write
n
0x0
0x0
Data4
Data Byte 4\n5th data byte of CAN Data Frame
0
8
read-write
Data5
Data Byte 5\n6th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B2
CAN_IF1_DAT_B2
IF1 Data B2 Register
0x48
read-write
n
0x0
0x0
Data6
Data Byte 6\n7th data byte of CAN Data Frame.
0
8
read-write
Data7
Data Byte 7\n8th data byte of CAN Data Frame.
8
8
read-write
CAN_IF1_MASK1
CAN_IF1_MASK1
IF1 Mask 1 Register
0x28
-1
read-write
n
0x0
0x0
Msk
Identifier Mask 15-0\n
0
16
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
CAN_IF1_MASK2
CAN_IF1_MASK2
IF1 Mask 2 Register
0x2C
-1
read-write
n
0x0
0x0
MDir
Mask Message Direction\n
14
1
read-write
0
The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering
#0
1
The message direction bit (Dir) is used for acceptance filtering
#1
Msk
Identifier Mask 28-16\n
0
13
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
MXtd
Mask Extended Identifier
Note: When 11-bit ( standard ) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
15
1
read-write
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#0
1
The extended identifier bit (IDE) is used for acceptance filtering
#1
CAN_IF1_MCON
CAN_IF1_MCON
IF1 Message Control Register
0x38
read-write
n
0x0
0x0
DLC
Data Length Code
0-8: Data Frame has 0-8 data bytes.
9-15: Data Frame has 8 data bytes
Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
Data 0: 1st data byte of a CAN Data Frame
Data 1: 2nd data byte of a CAN Data Frame
Data 2: 3rd data byte of a CAN Data Frame
Data 3: 4th data byte of a CAN Data Frame
Data 4: 5th data byte of a CAN Data Frame
Data 5: 6th data byte of a CAN Data Frame
Data 6: 7th data byte of a CAN Data Frame
Data 7 : 8th data byte of a CAN Data Frame
Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. I f the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
0
4
read-write
EoB
End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
7
1
read-write
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#0
1
Single Message Object or last Message Object of a FIFO Buffer
#1
IntPnd
Interrupt Pending\n
13
1
read-write
0
This message object is not the source of an interrupt
#0
1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
#1
MsgLst
None
14
1
read-write
0
No message lost since last time this bit was reset by the CPU
#0
1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
#1
NewDat
New Data\n
15
1
read-write
0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
#1
RmtEn
Remote Enable Bit\n
9
1
read-write
0
At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged
#0
1
At the reception of a Remote Frame, TxRqst is set
#1
RxIE
Receive Interrupt Enable Bit\n
10
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame
#0
1
IntPnd will be set after a successful reception of a frame
#1
TxIE
Transmit Interrupt Enable Bit\n
11
1
read-write
0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame
#0
1
IntPnd will be set after a successful transmission of a frame
#1
TxRqst
Transmit Request\n
8
1
read-write
0
This Message Object is not waiting for transmission
#0
1
The transmission of this Message Object is requested and is not yet done
#1
UMask
Use Acceptance Mask
Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
12
1
read-write
0
Mask ignored
#0
1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
#1
CAN_IF2_ARB1
CAN_IF2_ARB1
IF2 Arbitration 1 Register
0x90
read-write
n
0x0
0x0
CAN_IF2_ARB2
CAN_IF2_ARB2
IF2 Arbitration 2 Register
0x94
read-write
n
0x0
0x0
CAN_IF2_CMASK
CAN_IF2_CMASK
IF2 Command Mask Register
0x84
read-write
n
0x0
0x0
CAN_IF2_CREQ
CAN_IF2_CREQ
IF2 Command Request Register
0x80
read-write
n
0x0
0x0
CAN_IF2_DAT_A1
CAN_IF2_DAT_A1
IF2 Data A1 Register
0x9C
read-write
n
0x0
0x0
CAN_IF2_DAT_A2
CAN_IF2_DAT_A2
IF2 Data A2 Register
0xA0
read-write
n
0x0
0x0
CAN_IF2_DAT_B1
CAN_IF2_DAT_B1
IF2 Data B1 Register
0xA4
read-write
n
0x0
0x0
CAN_IF2_DAT_B2
CAN_IF2_DAT_B2
IF2 Data B2 Register
0xA8
read-write
n
0x0
0x0
CAN_IF2_MASK1
CAN_IF2_MASK1
IF2 Mask 1 Register
0x88
read-write
n
0x0
0x0
CAN_IF2_MASK2
CAN_IF2_MASK2
IF2 Mask 2 Register
0x8C
read-write
n
0x0
0x0
CAN_IF2_MCON
CAN_IF2_MCON
IF2 Message Control Register
0x98
read-write
n
0x0
0x0
CAN_IIDR
CAN_IIDR
Interrupt Identifier Register
0x10
read-only
n
0x0
0x0
IntId
Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit. The Status Interrupt is cleared by reading the Status Register.
0
16
read-only
CAN_IPND1
CAN_IPND1
Interrupt Pending Register 1
0x140
read-only
n
0x0
0x0
IntPnd16_1
Interrupt Pending Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_IPND2
CAN_IPND2
Interrupt Pending Register 2
0x144
read-only
n
0x0
0x0
IntPnd32_17
Interrupt Pending Bits 32-17(Of All Message Objects)\n
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_MVLD1
CAN_MVLD1
Message Valid Register 1
0x160
read-only
n
0x0
0x0
MsgVal16_1
Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_MVLD2
CAN_MVLD2
Message Valid Register 2
0x164
read-only
n
0x0
0x0
MsgVal32_17
Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_NDAT1
CAN_NDAT1
New Data Register 1
0x120
read-only
n
0x0
0x0
NewData16_1
New Data Bits 16-1 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_NDAT2
CAN_NDAT2
New Data Register 2
0x124
read-only
n
0x0
0x0
NewData32_17
New Data Bits 32-17 (Of All Message Objects)\n
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_STATUS
CAN_STATUS
Status Register
0x4
read-write
n
0x0
0x0
BOff
Bus-Off Status (Read Only) \n
7
1
read-only
0
The CAN module is not in bus-off state
#0
1
The CAN module is in bus-off state
#1
EPass
Error Passive (Read Only)\n
5
1
read-only
0
The CAN Core is error active
#0
1
The CAN Core is in the error passive state as defined in the CAN Specification
#1
EWarn
Error Warning Status (Read Only)\n
6
1
read-only
0
Both error counters are below the error warning limit of 96
#0
1
At least one of the error counters in the EML has reached the error warning limit of 96
#1
LEC
Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. The following table describes the error code.
0
3
read-write
RxOK
Received A Message Successfully\n
4
1
read-write
0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#0
1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
#1
TxOK
Transmitted A Message Successfully\n
3
1
read-write
0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#0
1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
#1
CAN_TEST
CAN_TEST
Test Register
0x14
read-write
n
0x0
0x0
Basic
Basic Mode\n
2
1
read-write
0
Basic Mode disabled
#0
1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
#1
LBack
Loop Back Mode Enable Bit\n
4
1
read-write
0
Loop Back Mode is disabled
#0
1
Loop Back Mode is enabled
#1
Res
Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
0
2
read-write
Rx
Monitors The Actual Value Of CAN_RX Pin (Read Only) *(1)\n
7
1
read-only
0
The CAN bus is dominant (CAN_RX = '0')
#0
1
The CAN bus is recessive (CAN_RX = '1')
#1
Silent
Silent Mode\n
3
1
read-write
0
Normal operation
#0
1
The module is in Silent Mode
#1
Tx
Tx[1:0]: Control Of CAN_TX Pin\n
5
2
read-write
0
Reset value, CAN_TX pin is controlled by the CAN Core
#00
1
Sample Point can be monitored at CAN_TX pin
#01
2
CAN_TX pin drives a dominant ('0') value
#10
3
CAN_TX pin drives a recessive ('1') value
#11
CAN_TXREQ1
CAN_TXREQ1
Transmission Request Register 1
0x100
read-only
n
0x0
0x0
TxRqst16_1
Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_TXREQ2
CAN_TXREQ2
Transmission Request Register 2
0x104
read-only
n
0x0
0x0
TxRqst32_17
Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not yet done
1
CAN_WU_EN
CAN_WU_EN
Wake-up Enable Control Register
0x168
read-write
n
0x0
0x0
WAKUP_EN
Wake-Up Enable Bit\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin..
0
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
CAN_WU_STATUS
CAN_WU_STATUS
Wake-up Status Register
0x16C
read-write
n
0x0
0x0
WAKUP_STS
Wake-Up Status \nNote: This bit can be cleared by writing '0'.
0
1
read-write
0
No wake-up event occurred
#0
1
Wake-up event occurred
#1
CAP
CAP Register Map
CAP
0x0
0x0
0x38
registers
n
0x3C
0x8
registers
n
0x48
0x20
registers
n
0x80
0xC
registers
n
CMPADDR
CAP_CMPADDR
Compare Memory Base Address Register
0x40
-1
read-write
n
0x0
0x0
CMPADDR
Compare Memory Base Address
Word aligns address ignore the bits [1:0].
0
32
read-write
CTL
CAP_CTL
Image Capture Interface Control Register
0x0
-1
read-write
n
0x0
0x0
ADDRSW
Packet Buffer Address Switch\n
3
1
read-write
0
Packet buffer address switch Disabled
#0
1
Packet buffer address switch Enabled
#1
CAPEN
Image Capture Interface Enable\n
0
1
read-write
0
Image Capture Interface Disabled
#0
1
Image Capture Interface Enabled
#1
PKTEN
Packet Output Enable\n
6
1
read-write
0
Packet output Disabled
#0
1
Packet output Enabled
#1
PLNEN
Planar Output Enable\n
5
1
read-write
0
Planar output Disabled
#0
1
Planar output Enabled
#1
SHUTTER
Image Capture Interface Automatically Disable The Capture Inteface After A Frame Had Been Captured\n
16
1
read-write
0
Shutter Disabled
#0
1
Shutter Enabled
#1
UPDATE
Update Register At New Frame\n
20
1
read-write
0
Update register at new frame Disabled
#0
1
Update register at new frame Enabled (Auto clear to 0 when register updated)
#1
VPRST
Capture Interface Reset\n
24
1
read-write
0
Capture interface reset Disabled
#0
1
Capture interface reset Enabled
#1
CURADDRP
CAP_CURADDRP
Current Packet System Memory Address Register
0x50
read-only
n
0x0
0x0
CURADDR
Current Packet Output Memory Address
0
32
read-only
CURADDRU
CAP_CURADDRU
Current Planar U System Memory Address Register
0x58
read-only
n
0x0
0x0
CURADDR
Current Planar U Output Memory Address
0
32
read-only
CURADDRY
CAP_CURADDRY
Current Planar Y System Memory Address Register
0x54
read-only
n
0x0
0x0
CURADDR
Current Planar Y Output Memory Address
0
32
read-only
CURVADDR
CAP_CURVADDR
Current Planar V System Memory Address Register
0x5C
read-only
n
0x0
0x0
CURADDR
Current Planar V Output Memory Address
0
32
read-only
CWS
CAP_CWS
Cropping Window Size Register
0x24
read-write
n
0x0
0x0
CWH
Cropping Window Height
16
11
read-write
CWW
Cropping Window Width
0
12
read-write
CWSP
CAP_CWSP
Cropping Window Starting Address Register
0x20
read-write
n
0x0
0x0
CWSADDRH
Cropping Window Horizontal Starting Address
0
12
read-write
CWSADDRV
Cropping Window Vertical Starting Address
16
11
read-write
FIFOTH
CAP_FIFOTH
FIFO Threshold Register
0x3C
-1
read-write
n
0x0
0x0
OVF
FIFO Overflow Flag
31
1
read-write
PKTFTH
Packet FIFO Threshold
24
5
read-write
PLNUFTH
Planar U FIFO Threshold
8
4
read-write
PLNVFTH
Planar V FIFO Threshold
0
4
read-write
PLNYFTH
Planar Y FIFO Threshold
16
5
read-write
FRCTL
CAP_FRCTL
Scaling Frame Rate Factor Register
0x30
read-write
n
0x0
0x0
FRM
Scaling Frame Rate Factor M\nSpecify the denominator part (M) of the frame rate scaling factor.\nThe output image frame rate will be equal to input image frame rate * (N/M).\nNote: The value of N must be equal to or less than M.
0
6
read-write
FRN
Scaling Frame Rate Factor N\nSpecify the denominator part (N) of the frame rate scaling factor.
8
6
read-write
INT
CAP_INT
Image Capture Interface Interrupt Register
0x8
read-write
n
0x0
0x0
ADDRMIEN
Address Match Interrupt Enable\n
19
1
read-write
0
Address match interrupt Disabled
#0
1
Address match interrupt Enabled
#1
ADDRMINTF
Memory Address Match Interrupt\nIf this bit shows 1, Memory Address Match Interrupt occurred.\nWrite 1 to clear it.
3
1
read-write
MDIEN
Motion Detection Output Finish Interrupt Enable\n
20
1
read-write
0
CAP_MD finish interrupt Disabled
#0
1
CAP_MD finish interrupt Enabled
#1
MDINTF
Motion Detection Output Finish Interrupt\nIf this bit shows 1, Motion Detection Output Finish Interrupt occurred.\nWrite 1 to clear it.
4
1
read-write
MEIEN
System Memory Error Interrupt Enable\n
17
1
read-write
0
System memory error interrupt Disabled
#0
1
System memory error interrupt Enabled
#1
MEINTF
Bus Master Transfer Error Interrupt\nIf this bit shows 1, Transfer Error occurred. Write 1 to clear it.
1
1
read-write
VIEN
Video Frame End Interrupt Enable\n
16
1
read-write
0
Video frame end interrupt Disabled
#0
1
Video frame end interrupt Enabled
#1
VINTF
Video Frame End Interrupt\nIf this bit shows 1, receiving a frame completed.\nWrite 1 to clear it.
0
1
read-write
MD
CAP_MD
Motion Detection Register
0x10
read-write
n
0x0
0x0
MDBS
Motion Detection Block Size\n
8
1
read-write
0
16x16
#0
1
8x8
#1
MDDF
Motion Detection Detect Frequency\n
10
2
read-write
0
Each frame
#00
1
Every 2 frame
#01
2
Every 3 frame
#10
3
Every 4 frame
#11
MDEN
Motion Detection Enable\n
0
1
read-write
0
CAP_MD Disabled
#0
1
CAP_MD Enabled
#1
MDSM
Motion Detection Save Mode\n
9
1
read-write
0
1 bit DIFF + 7 bit Y Differential
#0
1
1 bit DIFF only
#1
MDTHR
Motion Detection Differential Threshold
16
5
read-write
MDADDR
CAP_MDADDR
Motion Detection Output Address Register
0x14
read-write
n
0x0
0x0
MDADDR
Motion Detection Output Address Register (Word Alignment)
0
32
read-write
MDYADDR
CAP_MDYADDR
Motion Detection Temp Y Output Address Register
0x18
read-write
n
0x0
0x0
MDYADDR
Motion Detection Temp Y Output Address Register (Word Alignment)
0
32
read-write
PAR
CAP_PAR
Image Capture Interface Parameter Register
0x4
read-write
n
0x0
0x0
COLORCTL
Special COLORCTL Processing\n
11
2
read-write
0
Normal Color
#00
1
Sepia effect, corresponding U,V component value is set at register CAP_SEPIA
#01
2
Negative picture
#10
3
Posterize image, the Y, U, V components posterizing factor are set at register CAP_POSTERIZE
#11
FBB
Field By Blank\nHardware will tag field0 or field1 by vertical blanking instead of FIELD flag in ccir-656 mode.\n
18
1
read-write
0
Field by blank Disabled
#0
1
Field by blank Enabled
#1
HSP
Sensor Hsync Polarity\n
9
1
read-write
0
Sync Low
#0
1
Sync High
#1
INDATORD
Sensor Input Data Order\n
2
2
read-write
0
Y0 U0 Y1 V0
#00
1
Y0 V0 Y1 U0
#01
2
U0 Y0 V0 Y1
#10
3
V0 Y0 U0 Y1
#11
INFMT
Sensor Input Data Format\n
0
1
read-write
0
YCbCr422
#0
1
RGB565
#1
OUTFMT
Image Data Format Output To System Memory\n
4
2
read-write
0
YCbCr422
#00
1
Only output Y
#01
2
RGB555
#10
3
RGB565
#11
PCLKP
Sensor Pixel Clock Polarity\n
8
1
read-write
0
Input video data and signals are latched by falling edge of Pixel Clock
#0
1
Input video data and signals are latched by rising edge of Pixel Clock
#1
PLNFMT
Planar Output YUV Format\n
7
1
read-write
0
YUV422
#0
1
YUV420
#1
RANGE
Scale Input YUV CCIR601 Color Range To Full Range\n
6
1
read-write
0
default
#0
1
Scale to full range
#1
SENTYPE
Sensor Input Type\n
1
1
read-write
0
CCIR601
#0
1
CCIR656, VSync Hsync embedded in the data signal
#1
VSP
Sensor Vsync Polarity\n
10
1
read-write
0
Sync Low
#0
1
Sync High
#1
PKTBA0
CAP_PKTBA0
System Memory Packet Base Address 0 Register
0x60
read-write
n
0x0
0x0
BASEADDR
System Memory Packet Base Address 0
Word aligns address ignore the bits [1:0].
0
32
read-write
PKTBA1
CAP_PKTBA1
System Memory Packet Base Address 1 Register
0x64
read-write
n
0x0
0x0
BASEADDR
System Memory Packet Base Address 1
Word aligns address ignore the bits [1:0].
0
32
read-write
PKTSL
CAP_PKTSL
Packet Scaling Vertical/Horizontal Factor Register (LSB)
0x28
read-write
n
0x0
0x0
PKTSHML
Packet Scaling Horizontal Factor M (Lower 8-Bit)\nSpecifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.\nThe output image width will be equal to the image width * N/M.\nNote: The value of N must be equal to or less than M.
0
8
read-write
PKTSHNL
Packet Scaling Horizontal Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
8
8
read-write
PKTSVML
Packet Scaling Vertical Factor M (Lower 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the vertical scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.\nThe output image width will be equal to the image height * N/M.\nNote: The value of N must be equal to or less than M.
16
8
read-write
PKTSVNL
Packet Scaling Vertical Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the vertical scaling factor. \nThe lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor.
24
8
read-write
PKTSM
CAP_PKTSM
Packet Scaling Vertical/Horizontal Factor Register (MSB)
0x48
read-write
n
0x0
0x0
PKTSHMH
Packet Scaling Horizontal Factor M (Higher 8-Bit)
Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
Please refer to the register CAP_PKTSL for the detailed operation.
0
8
read-write
PKTSHNH
Packet Scaling Horizontal Factor N (Higher 8-Bit)
Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
Please refer to the register CAP_PKTSL for the detailed operation.
8
8
read-write
PKTSVMH
Packet Scaling Vertical Factor M (Higher 8-Bit)
Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
Please refer to the register CAP_PKTSL to check the cooperation between these two registers.
16
8
read-write
PKTSVNH
Packet Scaling Vertical Factor N (Higher 8-Bit)
Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
Please refer to the register CAP_PKTSL to check the cooperation between these two registers.
24
8
read-write
PLNSL
CAP_PLNSL
Planar Scaling Vertical/Horizontal Factor Register (LSB)
0x2C
read-write
n
0x0
0x0
PLNSHML
Planar Scaling Horizontal Factor M (Lower 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.\nThe output image width will be equal to the image width * N/M.\nNote: The value of N must be equal to or less than M.
0
8
read-write
PLNSHNL
Planar Scaling Horizontal Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
8
8
read-write
PLNSVML
Planar Scaling Vertical Factor M (Lower 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the vertical scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.\nThe output image width will be equal to the image height * N/M.\nNote: The value of N must be equal to or less than M.
16
8
read-write
PLNSVNL
Planar Scaling Vertical Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the vertical scaling factor. \nThe lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
24
8
read-write
PLNSM
CAP_PLNSM
Planar Scaling Vertical/Horizontal Factor Register (MSB)
0x4C
read-write
n
0x0
0x0
PLNSHMH
Planar Scaling Horizontal Factor M (Higher 8-Bit)
Specifies the higher 8-bit of denominator part (M) of the horizontal scaling factor
For detailed programming, please refer to the register CAP_PLNSL .
0
8
read-write
PLNSHNH
Planar Scaling Horizontal Factor N (Higher 8-Bit)
Specifies the higher 8-bit of numerator part (N) of the horizontal scaling factor.
For detailed programming, please refer to the register CAP_PLNSL .
8
8
read-write
PLNSVMH
Planar Scaling Vertical Factor M (Higher 8-Bit)
Specifies the lower 8-bit of denominator part (M) of the vertical scaling factor.
For detailed programming, please refer to the register CAP_PLNSL .
16
8
read-write
PLNSVNH
Planar Scaling Vertical Factor N (Higher 8-Bit)
Specifies the higher 8-bit of numerator part (N) of the vertical scaling factor.
For detailed programming, please refer to the register CAP_PLNSL .
24
8
read-write
POSTERIZE
CAP_POSTERIZE
YUV Component Posterizing Factor Register
0xC
read-write
n
0x0
0x0
UCOMP
U Component Posterizing Factor\n
8
8
read-write
VCOMP
V Component Posterizing Factor\n
0
8
read-write
YCOMP
Y Component Posterizing Factor\n
16
8
read-write
SEPIA
CAP_SEPIA
Sepia Effect Control Register
0x1C
read-write
n
0x0
0x0
UCOMP
Define the constant U component while Sepia color effect is turned on.
8
8
read-write
VCOMP
Define the constant V component while Sepia color effect is turned on.
0
8
read-write
STRIDE
CAP_STRIDE
Frame Output Pixel Stride Width Register
0x34
read-write
n
0x0
0x0
PKTSTRIDE
Packet Frame Output Pixel Stride Width\nThe output pixel stride size of packet pipe.
0
14
read-write
PLNSTRIDE
Planar Frame Output Pixel Stride Width\nThe output pixel stride size of planar pipe.
16
14
read-write
UBA
CAP_UBA
System Memory Planar U Base Address Register
0x84
read-write
n
0x0
0x0
BASEADDR
System Memory Planar U Base Address
Word aligns address ignore the bits [1:0].
0
32
read-write
VBA
CAP_VBA
System Memory Planar V Base Address Register
0x88
read-write
n
0x0
0x0
BASEADDR
System Memory Planar V Base Address
Word aligns address ignore the bits [1:0].
0
32
read-write
YBA
CAP_YBA
System Memory Planar Y Base Address Register
0x80
read-write
n
0x0
0x0
BASEADDR
System Memory Planar Y Base Address
Word aligns address ignore the bits [1:0].
0
32
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x30
registers
n
0x40
0x8
registers
n
0x50
0x4
registers
n
0x60
0x4
registers
n
0x70
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
CAPCKEN
Image Capture Interface Controller Clock Enable Bit \n
8
1
read-write
0
CAP controller's clock Disabled
#0
1
CAP controller's clock Enabled
#1
CRCCKEN
CRC Generator Controller Clock Enable Bit\n
7
1
read-write
0
CRC engine clock Disabled
#0
1
CRC engine clock Enabled
#1
CRPTCKEN
Cryptographic Accelerator Clock Enable Bit \n
12
1
read-write
0
Cryptographic Accelerator clock Disabled
#0
1
Cryptographic Accelerator clock Enabled
#1
EBICKEN
EBI Controller Clock Enable Bit \n
3
1
read-write
0
EBI engine clock Disabled
#0
1
EBI engine clock Enabled
#1
EMACCKEN
Ethernet Controller Clock Enable Bit (NUC472 Only)\n
5
1
read-write
0
Ethernet Controller engine clock Disabled
#0
1
Ethernet Controller engine clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit\n
2
1
read-write
0
Flash ISP engine clock Disabled
#0
1
Flash ISP engine clock Enabled
#1
PDMACKEN
PDMA Controller Clock Enable Bit\n
1
1
read-write
0
PDMA engine clock Disabled
#0
1
PDMA engine clock Enabled
#1
SDHCKEN
SDHOST Controller Clock Enable Bit \n
6
1
read-write
0
SDHOST engine clock Disabled
#0
1
SDHOST engine clock Enabled
#1
SENCKEN
Sensor Clock Enable Bit \n
9
1
read-write
0
Sensor clock Disabled
#0
1
Sensor clock Enabled
#1
USBDCKEN
USB 2.0 Device Clock Enable Bit\n
10
1
read-write
0
USB device controller's clock Disabled
#0
1
USB device controller's clock Enabled
#1
USBHCKEN
USB HOST Controller Clock Enable Bit \n
4
1
read-write
0
USB HOST engine clock Disabled
#0
1
USB HOST engine clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
-1
read-write
n
0x0
0x0
ACMPCKEN
Analog Comparator Clock Enable Bit\n
7
1
read-write
0
Analog Comparator Clock Disabled
#0
1
Analog Comparator Clock Enabled
#1
ADCCKEN
Analog-Digital-Converter (ADC) Clock Enable Bit\n
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
CAN0CKEN
CAN Bus Controller-0 Clock Enable Bit\n
24
1
read-write
0
CAN0 clock Disabled
#0
1
CAN0 clock Enabled
#1
CAN1CKEN
CAN Bus Controller-1 Clock Enable Bit\n
25
1
read-write
0
CAN1 clock Disabled
#0
1
CAN1 clock Enabled
#1
FDIVCKEN
Frequency Divider Output Clock Enable Bit\n
6
1
read-write
0
FDIV Clock Disabled
#0
1
FDIV Clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit\n
8
1
read-write
0
I2C0 Clock Disabled
#0
1
I2C0 Clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit\n
9
1
read-write
0
I2C1 Clock Disabled
#0
1
I2C1 Clock Enabled
#1
I2C2CKEN
I2C2 Clock Enable Bit\n
10
1
read-write
0
I2C2 Clock Disabled
#0
1
I2C2 Clock Enabled
#1
I2C3CKEN
I2C3 Clock Enable Bit\n
11
1
read-write
0
I2C3 Clock Disabled
#0
1
I2C3 Clock Enabled
#1
I2S0CKEN
I2S0 Clock Enable Bit\n
29
1
read-write
0
I2S Clock Disabled
#0
1
I2S Clock Enabled
#1
I2S1CKEN
I2S1 Clock Enable Bit\n
30
1
read-write
0
I2S1 Clock Disabled
#0
1
I2S1 Clock Enabled
#1
OTGCKEN
USB 2.0 OTG Device Controller Clock Enable Bit\n
26
1
read-write
0
OTG clock Disabled
#0
1
OTG clock Enabled
#1
PS2CKEN
PS/2 Clock Enable Bit\n
31
1
read-write
0
PS/2 clock Disabled
#0
1
PS/2 clock Enabled
#1
RTCCKEN
Real-Time-Clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768 kHz external low-speed crystal.\n
1
1
read-write
0
RTC Clock Disabled
#0
1
RTC Clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit\n
12
1
read-write
0
SPI0 Clock Disabled
#0
1
SPI0 Clock Enabled
#1
SPI1CKEN
SPI1 Clock Enable Bit\n
13
1
read-write
0
SPI1 Clock Disabled
#0
1
SPI1 Clock Enabled
#1
SPI2CKEN
SPI2 Clock Enable Bit\n
14
1
read-write
0
SPI2 Clock Disabled
#0
1
SPI2 Clock Enabled
#1
SPI3CKEN
SPI3 Clock Enable Bit \n
15
1
read-write
0
SPI3 Clock Disabled
#0
1
SPI3 Clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit\n
2
1
read-write
0
Timer0 Clock Disabled
#0
1
Timer0 Clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit\n
3
1
read-write
0
Timer1 Clock Disabled
#0
1
Timer1 Clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit\n
4
1
read-write
0
Timer2 Clock Disabled
#0
1
Timer2 Clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit\n
5
1
read-write
0
Timer3 Clock Disabled
#0
1
Timer3 Clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit\n
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit\n
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2CKEN
UART2 Clock Enable Bit \n
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
UART3CKEN
UART3 Clock Enable Bit \n
19
1
read-write
0
UART3 clock Disabled
#0
1
UART3 clock Enabled
#1
UART4CKEN
UART4 Clock Enable Bit \n
20
1
read-write
0
UART4 clock Disabled
#0
1
UART4 clock Enabled
#1
UART5CKEN
UART5 Clock Enable Bit \n
21
1
read-write
0
UART5 clock Disabled
#0
1
UART5 clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Watchdog Timer Clock Disabled
#0
1
Watchdog Timer Clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0xC
read-write
n
0x0
0x0
EADCCKEN
Enhanced Analog-Digital-Converter (E ADC) Clock Enable Bit\n
31
1
read-write
0
EADC clock Disabled
#0
1
EADC clock Enabled
#1
ECAP0CKEN
Enhanced CAP (ECAP0) Clock Enable Bit
26
1
read-write
0
ECAP0 clock Disabled
#0
1
ECAP0 clock Enabled
#1
ECAP1CKEN
Enhanced CAP (ECAP1) Clock Enable Bit
27
1
read-write
0
ECAP1 clock Disabled
#0
1
ECAP1 clock Enabled
#1
EPWM0CKEN
Enhanced PWM0 (EPWM) Clock Enable Bit\n
28
1
read-write
0
EPWM0 clock Disabled
#0
1
EPWM0 clock Enabled
#1
EPWM1CKEN
Enhanced PWM1 (EPWM) Clock Enable Bit\n
29
1
read-write
0
EPWM1 clock Disabled
#0
1
EPWM1 clock Enabled
#1
I2C4CKEN
I2C4 Clock Enable Bit\n
8
1
read-write
0
I2C4 Clock Disabled
#0
1
I2C4 Clock Enabled
#1
OPACKEN
OP Amplifier (OPA) Clock Enable Bit\n
30
1
read-write
0
OPA clock Disabled
#0
1
OPA clock Enabled
#1
PWM0CH01CKEN
PWM0_01 Clock Enable Bit\n
16
1
read-write
0
PWM0_01 Clock Disabled
#0
1
PWM0_01 Clock Enabled
#1
PWM0CH23CKEN
PWM0_23 Clock Enable Bit\n
17
1
read-write
0
PWM0_23 Clock Disabled
#0
1
PWM0_23 Clock Enabled
#1
PWM0CH45CKEN
PWM0_45 Clock Enable Bit\n
18
1
read-write
0
PWM0_45 Clock Disabled
#0
1
PWM0_45 Clock Enabled
#1
PWM1CH01CKEN
PWM1_01 Clock Enable Bit\n
19
1
read-write
0
PWM1_01 Clock Disabled
#0
1
PWM1_01 Clock Enabled
#1
PWM1CH23CKEN
PWM1_23 Clock Enable Bit\n
20
1
read-write
0
PWM1_23 Clock Disabled
#0
1
PWM1_23 Clock Enabled
#1
PWM1CH45CKEN
PWM1_45 Clock Enable Bit\n
21
1
read-write
0
PWM1_45 Clock Disabled
#0
1
PWM1_45 Clock Enabled
#1
QEI0CKEN
Quadrature Encoder Interface (QEI0) Clock Enable Bit\n
22
1
read-write
0
QEI0 clock Disabled
#0
1
QEI0 clock Enabled
#1
QEI1CKEN
Quadrature Encoder Interface (QEI1) Clock Enable Bit\n
23
1
read-write
0
QEI1 clock Disabled
#0
1
QEI1 clock Enabled
#1
SC0CKEN
SC0 Clock Enable Bit\n
0
1
read-write
0
SC0 Clock Disabled
#0
1
SC0 Clock Enabled
#1
SC1CKEN
SC1 Clock Enable Bit\n
1
1
read-write
0
SC1 Clock Disabled
#0
1
SC1 Clock Enabled
#1
SC2CKEN
SC2 Clock Enable Bit\n
2
1
read-write
0
SC2 Clock Disabled
#0
1
SC2 Clock Enabled
#1
SC3CKEN
SC3 Clock Enable Bit\n
3
1
read-write
0
SC3 Clock Disabled
#0
1
SC3 Clock Enabled
#1
SC4CKEN
SC4 Clock Enable Bit\n
4
1
read-write
0
SC4 Clock Disabled
#0
1
SC4 Clock Enabled
#1
SC5CKEN
SC5 Clock Enable Bit\n
5
1
read-write
0
SC5 Clock Disabled
#0
1
SC5 Clock Enabled
#1
CLKDCTL
CLK_CLKDCTL
Clock Fail Detector Control Register
0x70
-1
read-write
n
0x0
0x0
IRCDEN
Internal RC Clock Detector Enable Bit
8
1
read-write
0
IRC clock fail interrupt disabled
#0
1
IRC clock fail interrupt enabled
#1
IRCFIEN
Internal RC Clock Detector Interrupt Enable Bit
9
1
read-write
0
IRC clock fail interrupt disabled
#0
1
IRC clock fail interrupt enabled
#1
IRCFIF
Internal RC Clock Fail Flag\n
10
1
read-write
0
IRC clock normal
#0
1
IRC abnormal (write 1 to clear)
#1
SYSFDEN
System Clock Detector Enable Bit
0
1
read-write
0
system clock fail interrupt disabled
#0
1
system clock fail interrupt enabled
#1
SYSFIEN
System Clock Detector Interrupt Enable Bit
1
1
read-write
0
system clock fail interrupt disabled
#0
1
system clock fail interrupt enabled
#1
SYSFIF
System Clock Detect Fail Flag\n
2
1
read-write
0
System clock normal
#0
1
System clock abnormal (write 1 to clear)
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x20
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source\n
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source\n
0
4
read-write
SDHDIV
SDHOST Clock Divide Number From SDHOST Clock Source\n
24
8
read-write
UARTDIV
UART Clock Divide Number From UART Clock Source\n
8
4
read-write
USBHDIV
USB Host Clock Divide Number From PLL Clock\n
4
4
read-write
CLKDIV1
CLK_CLKDIV1
Clock Divider Number Register 1
0x24
read-write
n
0x0
0x0
SC0DIV
SC0 Clock Divide Number From SC0 Clock Source\n
0
8
read-write
SC1DIV
SC1 Clock Divide Number From SC1 Clock Source\n
8
8
read-write
SC2DIV
SC2 Clock Divide Number From SC2 Clock Source\n
16
8
read-write
SC3DIV
SC3 Clock Divide Number From SC3 Clock Source\n
24
8
read-write
CLKDIV2
CLK_CLKDIV2
Clock Divider Number Register 2
0x28
read-write
n
0x0
0x0
SC4DIV
SC4 Clock Divide Number From SC4 Clock Source\n
0
8
read-write
SC5DIV
SC5 Clock Divide Number From SC5 Clock Source\n
8
8
read-write
CLKDIV3
CLK_CLKDIV3
Clock Divider Number Register 3
0x2C
read-write
n
0x0
0x0
CAPDIV
Image Capture Seneor Clock Divide Number From ICAP Clock Source\n
0
8
read-write
EMACDIV
Ethernet Clock Divide Number Form HCLK (NUC472 Only)\n
16
8
read-write
VSENSEDIV
Video Pixel Clock Divide Number From ICAP Clock Source\n
8
8
read-write
CLKOCTL
CLK_CLKOCTL
Frequency Divider Control Register
0x60
read-write
n
0x0
0x0
CLKOEN
Clock Output Enable Bit\n
4
1
read-write
0
Clock output disabled
#0
1
Clock output enabled
#1
DIV1EN
Frequency Divider 1 Enable Bit \n
5
1
read-write
0
Divider output frequency is dependent on FSEL value when FDIVEN is enabled
#0
1
Divider output frequency is input clock frequency
#1
FSEL
Divider Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on
The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
These bits are protected bit, it means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PLL clock
#010
3
Clock source from LIRC clock
#011
4
Clock source from PLL2 clock
#100
7
Clock source from HIRC clock
#111
ICAPSEL
Image Capture Interface Clock Source Selection
These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
16
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from HIRC clock
#11
PCLKSEL
PCLK Clock Source Selection (Write Protect)
These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
6
1
read-write
0
Clock source from HCLK
#0
1
Clock source from HCLK/2
#1
SDHSEL
SDHOST Engine Clock Source Selection
These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
20
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from HIRC clock
#11
STCLKSEL
Cortex-M4 SysTick Clock Source Selection (Write Protect)\n
3
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from HXT clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC clock/2
#111
USBHSEL
USB Host Clock Source Selection (Write Protect)
These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
8
1
read-write
0
Clock source from PLL2
#0
1
Clock source from PLL
#1
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection\n
28
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from LXT clock
#01
2
Clock source from HCLK
#10
3
Clock source from HIRC clock
#11
EADCSEL
ADC Clock Source Selection\n
2
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
Clock source from PCLK
#10
3
Clock source from HIRC clock
#11
SPI0SEL
SPI0 Clock Source Selection\n
4
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from PCLK
#1
SPI1SEL
SPI1 Clock Source Selection\n
5
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from PCLK
#1
SPI2SEL
SPI2 Clock Source Selection\n
6
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from PCLK
#1
SPI3SEL
SPI3 Clock Source Selection\n
7
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from PCLK
#1
TMR0SEL
TIMER0 Clock Source Selection\n
8
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from external trigger
#011
5
Clock source from LIRC clock
#101
7
Clock source from HIRC clock
#111
TMR1SEL
TIMER1 Clock Source Selection\n
12
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from external trigger
#011
5
Clock source from LIRC clock
#101
7
Clock source from HIRC clock
#111
TMR2SEL
TIMER2 Clock Source Selection\n
16
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from external trigger
#011
5
Clock source from LIRC clock
#101
7
Clock source from HIRC clock
#111
TMR3SEL
TIMER3 Clock Source Selection\n
20
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from external trigger
#011
5
Clock source from LIRC clock
#101
7
Clock source from HIRC clock
#111
UARTSEL
UART Clock Source Selection\n
24
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)
These bits are protected bit,and programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
2
read-write
0
Clock source from 4~24 MHz external high-speed crystal clock
#00
1
Clock source from LXT clock
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from LIRC clock
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection\n
30
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from LIRC clock
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x18
-1
read-write
n
0x0
0x0
PPWM0CH23SEL
PWM0_2 And PWM0_3 Clock Source Selection\nPWM0_2 and PWM0_3 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM0_2 and PWM0_3 is defined by PPWM0CH23SEL[2:0] \n
4
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from HIRC clock
#011
4
Clock source from LIRC clock
#100
PWM0CH01SEL
PWM0_0 And PWM0_1 Clock Source Selection\nPWM0_0 and PWM0_1 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM0_0 and PWM0_1 is defined by PWM0CH01SEL[2:0] \n
0
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from HIRC clock
#011
4
Clock source from LIRC clock
#100
PWM0CH45SEL
PWM0_4 And PWM0_5 Clock Source Selection
PWM0_4 and PWM0_5 used the same Engine clock source both of them use the same prescaler. The Engine clock source of PWM0_4 and PWM0_5 is defined by PWM0CH45SEL[2:0]
8
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from HIRC clock
#011
4
Clock source from LIRC clock
#100
PWM1CH01SEL
PWM1_0 And PWM1_1 Clock Source Selection\nPWM1_0 and PWM1_1 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0] \n
12
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from HIRC clock
#011
4
Clock source from LIRC clock
#100
PWM1CH23SEL
PWM1_2 And PWM1_3 Clock Source Selection\nPWM1_2 and PWM1_3 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM1_2 and PWM1_3 is defined by PWM1CH23SEL[2:0] \n
16
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from HIRC clock
#011
4
Clock source from LIRC clock
#100
PWM1CH45SEL
PWM1_4 And PWM1_5 Clock Source Selection
PWM1_4 and PWM1_5 used the same Engine clock source both of them use the same prescaler. The Engine clock source of PWM1_4 and PWM1_5 is defined by PWM1CH45SEL[2:0]
20
3
read-write
0
Clock source from HXT clock
#000
1
Clock source from LXT clock
#001
2
Clock source from PCLK
#010
3
Clock source from HIRC clock
#011
4
Clock source from LIRC clock
#100
CLKSEL3
CLK_CLKSEL3
Clock Source Select Control Register 3
0x1C
-1
read-write
n
0x0
0x0
I2S0SEL
I2S0 Clock Source Selection\n
16
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
Clock source from PCLK
#10
3
Clock source from HIRC clock
#11
I2S1SEL
I2S1 Clock Source Selection\n
18
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
Clock source from PCLK
#10
3
Clock source from HIRC clock
#11
SC0SEL
SC0 Clock Source Selection\n
0
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
PCLK
#10
3
Clock source from HIRC clock
#11
SC1SEL
SC1 Clock Source Selection\n
2
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
PCLK
#10
3
Clock source from HIRC clock
#11
SC2SEL
SC2 Clock Source Selection\n
4
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
PCLK
#10
3
Clock source from HIRC clock
#11
SC3SEL
SC3 Clock Source Selection\n
6
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
PCLK
#10
3
Clock source from HIRC clock
#11
SC4SEL
SC4 Clock Source Selection\n
8
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
PCLK
#10
3
Clock source from HIRC clock
#11
SC5SEL
SC5 Clock Source Selection\n
10
2
read-write
0
Clock source from HXT clock
#00
1
Clock source from PLL clock
#01
2
PCLK
#10
3
Clock source from HIRC clock
#11
PLL2CTL
CLK_PLL2CTL
PLL2 Control Register
0x44
read-write
n
0x0
0x0
PLL2CKEN
USB PHY 480 MHz Enable Bit\nThis bit enables USB PHY PLL (480 MHz), and user needs to care the extenal crystal is 12 MHz or 24 MHz source.\nNote: Refer to OTG_PHYCTL[8] register to set the exteranl crystal frequency HXT.
8
1
read-write
0
USB PHY PLL (480 MHz) Disabled
#0
1
USB PHY PLL (480 MHz) Enabled
#1
PLL2DIV
PLL2 Divider Control
Note: Max. PLL2 frequency is 240 MHz when HXT is1 2 MHz.
0
8
read-write
PLLCTL
CLK_PLLCTL
PLL Control Register
0x40
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control\n
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as clock input (XTALin)
#1
FBDIV
PLL Feedback Divider Control Pins\nRefer to the formulas below the table.
0
9
read-write
INDIV
PLL Input Divider Control Pins\nRefer to the formulas below the table.
9
5
read-write
OE
PLL OE (FOUT Enable) Pin Control\n
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDV
PLL Output Divider Control Pins\nRefer to the formulas below the table.
14
2
read-write
PD
Power-Down Mode\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\n
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLLREMAP
PLL Remap Enable Bit\n
20
1
read-write
0
PLL remap enable
#0
1
PLL remap disable
#1
PLLSRC
PLL Source Clock Selection\n
19
1
read-write
0
PLL source clock from HXT
#0
1
PLL source clock from HIRC
#1
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
DBPDEN
Chip Entering Power-Down Even ICE Connected\n
9
1
read-write
0
Chip enters power-down disabled in Debug mode
#0
1
Chip enters power-down enabled in Debug mode
#1
HIRCEN
22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Enable Bit (Write Protect)\n
2
1
read-write
0
HIRC Disabled
#0
1
HIRC Enabled
#1
HXTEN
4~24 MHz External High-Speed Crystal Clock (HXT) Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. \nWhen the default clock source is from 4~24 MHz external high-speed crystal, this bit is set to 1 automatically\n
0
1
read-write
0
HXT Disabled
#0
1
HXT Enabled
#1
LIRCEN
10 KHz Internal Low-Speed Oscillator (LIRC) Enable Bit (Write Protect)\n
3
1
read-write
0
LIRC Disabled
#0
1
LIRC Enabled (default 1)
#1
LXTEN
32.768 KHz External Low-Speed Crystal Clock (LXT) Enable Bit (Write Protect)\n
1
1
read-write
0
LXT Disabled
#0
1
LXT (Normal operation) Enabled
#1
PDEN
System Power-Down Enable Bit (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PDWTCPU bit.\n(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set. ( default)\n(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next power-down.\nIn Power-down mode, HXT and the HIRC will be disabled in this mode, but the LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or the LIRC.\n
7
1
read-write
0
Chip operating normally or chip in idle mode by WFI command
#0
1
Chip enters Power-down mode instant or waits CPU sleep command WFI
#1
PDWKDLY
Wake-Up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at HXT, and 256 clock cycles when chip works at HIRC.\n
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high.
5
1
read-write
0
Power-down Mode Wake-up Interrupt Disabled
#0
1
Power-down Mode Wake-up Interrupt Enabled
#1
PDWKIF
Power-Down Mode Wake-Up Interrupt Status
Set by power-down wake-up event , it indicates that resume from Power-down mode
The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake-up occurred
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
6
1
read-write
PDWTCPU
This Bit Control The Power-Down Entry Condition (Write Protect)\n
8
1
read-write
0
Chip enters Power-down mode when the PDEN bit is set to 1
#0
1
Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction
#1
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
read-write
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: Write 1 to clear the bit to 0.
7
1
read-write
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag\nNote: This bit is read only.
4
1
read-write
0
HIRC clock is not stable or disabled
#0
1
HIRC clock is stable
#1
HXTSTB
4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag\nNote: This bit is read only.
0
1
read-write
0
HXT clock is not stable or disabled
#0
1
HXT clock is stable
#1
LIRCSTB
10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag\nNote: This bit is read only.
3
1
read-write
0
LIRC clock is not stable or disabled
#0
1
LIRC clock is stable
#1
LXTSTB
32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag\nNote: This is read only.
1
1
read-write
0
LXT clock is not stable or disabled
#0
1
LXT clock is stabled
#1
PLL2STB
Internal PLL2 Clock Source Stable Flag\nNote: This bit is read only.
5
1
read-write
0
Internal PLL2 clock is not stable or disabled
#0
1
Internal PLL2 clock is stable
#1
PLLSTB
Internal PLL Clock Source Stable Flag\nNote: This bit is read only.
2
1
read-write
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable
#1
CRC
CRC Register Map
CRC
0x0
0x0
0x10
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Bits\nThis field indicates the CRC checksum.
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum Complement\n
27
1
read-write
0
No bit order reverse for CRC checksum
#0
1
1's complement for CRC checksum
#1
CHKSREV
Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
No bit order reverse for CRC checksum
#0
1
Bit order reverse for CRC checksum
#1
CRCEN
CRC Channel Enable Bit\n
0
1
read-write
0
CRC function Disabled
#0
1
CRC function Enabled
#1
CRCMODE
CRC Polynomial Mode Selection\n
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
CRCRST
CRC Engine Reset\nNote: Setting this bit will reload the initial seed value.
1
1
read-write
0
No effect
#0
1
Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles
#1
DATFMT
Write Data Complement\n
26
1
read-write
0
No bit order reversed for CRC write data in
#0
1
1's complement for CRC write data in
#1
DATLEN
CPU Write Data Length
This field indicates the write data length.
Note: When the data length is 8-bit mode, the valid data is DATA [7:0] if the data length is 16-bit mode, the valid data is DATA [15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.\nData length is 32-bit mode
#01
DATREV
Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
24
1
read-write
0
No bit order reversed for CRC write data in
#0
1
Bit order reversed for CRC write data in (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
read-write
n
0x0
0x0
DATA
CRC Write Data Bits\nSoftware can write data to this field to perform CRC operation, or uses PDMA function to get the data from memory\n
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
-1
read-write
n
0x0
0x0
SEED
CRC Seed Bits\nThis field indicates the CRC seed value.
0
32
read-write
CRYP
CRYPTO Register Map
CRYPTO
0x0
0x0
0x30
registers
n
0x100
0x13C
registers
n
0x248
0x2C
registers
n
0x288
0x2C
registers
n
0x2C8
0x2C
registers
n
0x300
0x28
registers
n
0x348
0x10
registers
n
0x50
0x18
registers
n
CRPT_AES0_CNT
CRPT_AES0_CNT
AES Byte Count Register for Channel 0
0x148
read-write
n
0x0
0x0
CNT
AES Byte Count\nThe CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRPT_AESn_CNT can be read and written. Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRPT_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block. Operations that are less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
0
32
read-write
CRPT_AES0_DADDR
CRPT_AES0_DADDR
AES DMA Destination Address Register for Channel 0
0x144
read-write
n
0x0
0x0
DADDR
AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. \nThe value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
0
32
read-write
CRPT_AES0_IV0
CRPT_AES0_IV0
AES Initial Vector Word 0 Register for Channel 0
0x130
read-write
n
0x0
0x0
IV
CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
0
32
read-write
CRPT_AES0_IV1
CRPT_AES0_IV1
AES Initial Vector Word 1 Register for Channel 0
0x134
read-write
n
0x0
0x0
CRPT_AES0_IV2
CRPT_AES0_IV2
AES Initial Vector Word 2 Register for Channel 0
0x138
read-write
n
0x0
0x0
CRPT_AES0_IV3
CRPT_AES0_IV3
AES Initial Vector Word 3 Register for Channel 0
0x13C
read-write
n
0x0
0x0
CRPT_AES0_KEY0
CRPT_AES0_KEY0
AES Key Word 0 Register for Channel 0
0x110
read-write
n
0x0
0x0
KEY
CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. {CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation. {CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation. {CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
0
32
read-write
CRPT_AES0_KEY1
CRPT_AES0_KEY1
AES Key Word 1 Register for Channel 0
0x114
read-write
n
0x0
0x0
CRPT_AES0_KEY2
CRPT_AES0_KEY2
AES Key Word 2 Register for Channel 0
0x118
read-write
n
0x0
0x0
CRPT_AES0_KEY3
CRPT_AES0_KEY3
AES Key Word 3 Register for Channel 0
0x11C
read-write
n
0x0
0x0
CRPT_AES0_KEY4
CRPT_AES0_KEY4
AES Key Word 4 Register for Channel 0
0x120
read-write
n
0x0
0x0
CRPT_AES0_KEY5
CRPT_AES0_KEY5
AES Key Word 5 Register for Channel 0
0x124
read-write
n
0x0
0x0
CRPT_AES0_KEY6
CRPT_AES0_KEY6
AES Key Word 6 Register for Channel 0
0x128
read-write
n
0x0
0x0
CRPT_AES0_KEY7
CRPT_AES0_KEY7
AES Key Word 7 Register for Channel 0
0x12C
read-write
n
0x0
0x0
CRPT_AES0_SADDR
CRPT_AES0_SADDR
AES DMA Source Address Register for Channel 0
0x140
read-write
n
0x0
0x0
SADDR
AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.\nThe value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
0
32
read-write
CRPT_AES1_CNT
CRPT_AES1_CNT
AES Byte Count Register for Channel 1
0x184
read-write
n
0x0
0x0
CRPT_AES1_DADDR
CRPT_AES1_DADDR
AES DMA Destination Address Register for Channel 1
0x180
read-write
n
0x0
0x0
CRPT_AES1_IV0
CRPT_AES1_IV0
AES Initial Vector Word 0 Register for Channel 1
0x16C
read-write
n
0x0
0x0
CRPT_AES1_IV1
CRPT_AES1_IV1
AES Initial Vector Word 1 Register for Channel 1
0x170
read-write
n
0x0
0x0
CRPT_AES1_IV2
CRPT_AES1_IV2
AES Initial Vector Word 2 Register for Channel 1
0x174
read-write
n
0x0
0x0
CRPT_AES1_IV3
CRPT_AES1_IV3
AES Initial Vector Word 3 Register for Channel 1
0x178
read-write
n
0x0
0x0
CRPT_AES1_KEY0
CRPT_AES1_KEY0
AES Key Word 0 Register for Channel 1
0x14C
read-write
n
0x0
0x0
CRPT_AES1_KEY1
CRPT_AES1_KEY1
AES Key Word 1 Register for Channel 1
0x150
read-write
n
0x0
0x0
CRPT_AES1_KEY2
CRPT_AES1_KEY2
AES Key Word 2 Register for Channel 1
0x154
read-write
n
0x0
0x0
CRPT_AES1_KEY3
CRPT_AES1_KEY3
AES Key Word 3 Register for Channel 1
0x158
read-write
n
0x0
0x0
CRPT_AES1_KEY4
CRPT_AES1_KEY4
AES Key Word 4 Register for Channel 1
0x15C
read-write
n
0x0
0x0
CRPT_AES1_KEY5
CRPT_AES1_KEY5
AES Key Word 5 Register for Channel 1
0x160
read-write
n
0x0
0x0
CRPT_AES1_KEY6
CRPT_AES1_KEY6
AES Key Word 6 Register for Channel 1
0x164
read-write
n
0x0
0x0
CRPT_AES1_KEY7
CRPT_AES1_KEY7
AES Key Word 7 Register for Channel 1
0x168
read-write
n
0x0
0x0
CRPT_AES1_SADDR
CRPT_AES1_SADDR
AES DMA Source Address Register for Channel 1
0x17C
read-write
n
0x0
0x0
CRPT_AES2_CNT
CRPT_AES2_CNT
AES Byte Count Register for Channel 2
0x1C0
read-write
n
0x0
0x0
CRPT_AES2_DADDR
CRPT_AES2_DADDR
AES DMA Destination Address Register for Channel 2
0x1BC
read-write
n
0x0
0x0
CRPT_AES2_IV0
CRPT_AES2_IV0
AES Initial Vector Word 0 Register for Channel 2
0x1A8
read-write
n
0x0
0x0
CRPT_AES2_IV1
CRPT_AES2_IV1
AES Initial Vector Word 1 Register for Channel 2
0x1AC
read-write
n
0x0
0x0
CRPT_AES2_IV2
CRPT_AES2_IV2
AES Initial Vector Word 2 Register for Channel 2
0x1B0
read-write
n
0x0
0x0
CRPT_AES2_IV3
CRPT_AES2_IV3
AES Initial Vector Word 3 Register for Channel 2
0x1B4
read-write
n
0x0
0x0
CRPT_AES2_KEY0
CRPT_AES2_KEY0
AES Key Word 0 Register for Channel 2
0x188
read-write
n
0x0
0x0
CRPT_AES2_KEY1
CRPT_AES2_KEY1
AES Key Word 1 Register for Channel 2
0x18C
read-write
n
0x0
0x0
CRPT_AES2_KEY2
CRPT_AES2_KEY2
AES Key Word 2 Register for Channel 2
0x190
read-write
n
0x0
0x0
CRPT_AES2_KEY3
CRPT_AES2_KEY3
AES Key Word 3 Register for Channel 2
0x194
read-write
n
0x0
0x0
CRPT_AES2_KEY4
CRPT_AES2_KEY4
AES Key Word 4 Register for Channel 2
0x198
read-write
n
0x0
0x0
CRPT_AES2_KEY5
CRPT_AES2_KEY5
AES Key Word 5 Register for Channel 2
0x19C
read-write
n
0x0
0x0
CRPT_AES2_KEY6
CRPT_AES2_KEY6
AES Key Word 6 Register for Channel 2
0x1A0
read-write
n
0x0
0x0
CRPT_AES2_KEY7
CRPT_AES2_KEY7
AES Key Word 7 Register for Channel 2
0x1A4
read-write
n
0x0
0x0
CRPT_AES2_SADDR
CRPT_AES2_SADDR
AES DMA Source Address Register for Channel 2
0x1B8
read-write
n
0x0
0x0
CRPT_AES3_CNT
CRPT_AES3_CNT
AES Byte Count Register for Channel 3
0x1FC
read-write
n
0x0
0x0
CRPT_AES3_DADDR
CRPT_AES3_DADDR
AES DMA Destination Address Register for Channel 3
0x1F8
read-write
n
0x0
0x0
CRPT_AES3_IV0
CRPT_AES3_IV0
AES Initial Vector Word 0 Register for Channel 3
0x1E4
read-write
n
0x0
0x0
CRPT_AES3_IV1
CRPT_AES3_IV1
AES Initial Vector Word 1 Register for Channel 3
0x1E8
read-write
n
0x0
0x0
CRPT_AES3_IV2
CRPT_AES3_IV2
AES Initial Vector Word 2 Register for Channel 3
0x1EC
read-write
n
0x0
0x0
CRPT_AES3_IV3
CRPT_AES3_IV3
AES Initial Vector Word 3 Register for Channel 3
0x1F0
read-write
n
0x0
0x0
CRPT_AES3_KEY0
CRPT_AES3_KEY0
AES Key Word 0 Register for Channel 3
0x1C4
read-write
n
0x0
0x0
CRPT_AES3_KEY1
CRPT_AES3_KEY1
AES Key Word 1 Register for Channel 3
0x1C8
read-write
n
0x0
0x0
CRPT_AES3_KEY2
CRPT_AES3_KEY2
AES Key Word 2 Register for Channel 3
0x1CC
read-write
n
0x0
0x0
CRPT_AES3_KEY3
CRPT_AES3_KEY3
AES Key Word 3 Register for Channel 3
0x1D0
read-write
n
0x0
0x0
CRPT_AES3_KEY4
CRPT_AES3_KEY4
AES Key Word 4 Register for Channel 3
0x1D4
read-write
n
0x0
0x0
CRPT_AES3_KEY5
CRPT_AES3_KEY5
AES Key Word 5 Register for Channel 3
0x1D8
read-write
n
0x0
0x0
CRPT_AES3_KEY6
CRPT_AES3_KEY6
AES Key Word 6 Register for Channel 3
0x1DC
read-write
n
0x0
0x0
CRPT_AES3_KEY7
CRPT_AES3_KEY7
AES Key Word 7 Register for Channel 3
0x1E0
read-write
n
0x0
0x0
CRPT_AES3_SADDR
CRPT_AES3_SADDR
AES DMA Source Address Register for Channel 3
0x1F4
read-write
n
0x0
0x0
CRPT_AES_CTL
CRPT_AES_CTL
AES Control Register
0x100
read-write
n
0x0
0x0
CHANNEL
AES Engine Working Channel\n
24
2
read-write
0
Current control register setting is for channel 0
#00
1
Current control register setting is for channel 1
#01
2
Current control register setting is for channel 2
#10
3
Current control register setting is for channel 3
#11
DMACSCAD
AES Engine DMA With Cascade Mode\n
6
1
read-write
0
DMA cascade function Disabled
#0
1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
#1
DMAEN
AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
7
1
read-write
0
AES DMA engine Disabled
#0
1
AES DMA engine Enabled
#1
DMALAST
AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered.
5
1
read-write
ENCRPT
AES Encryption/Decryption\n
16
1
read-write
0
AES engine executes decryption operation
#0
1
AES engine executes encryption operation
#1
INSWAP
AES Engine Input Data Swap \n
23
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
KEYPRT
Protect Key\nRead as a flag to reflect KEYPRT.\n
31
1
read-write
0
No effect
#0
1
Protect the content of the AES key from reading. The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well
#1
KEYSZ
AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
2
2
read-write
KEYUNPRT
Unprotect Key
Writing 0 to CRPT_AES_CTL [31] and 10110 to CRPT_AES_CTL [30:26] is to unprotect the AES key.
The KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
26
5
read-write
OPMODE
AES Engine Operation Modes\n
8
8
read-write
0
ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode)
0x00
2
CFB (Cipher Feedback Mode)
0x02
3
OFB (Output Feedback Mode)
0x03
4
CTR (Counter Mode)
0x04
16
CBC-CS1 (CBC Ciphertext-Stealing 1 Mode)
0x10
17
CBC-CS2 (CBC Ciphertext-Stealing 2 Mode)
0x11
18
CBC-CS3 (CBC Ciphertext-Stealing 3 Mode)
0x12
OUTSWAP
AES Engine Output Data Swap \n
22
1
read-write
0
Keep the original order
#0
1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
START
AES Engine Start\nNote: This bit is always 0 when it's read back.
0
1
read-write
0
No effect
#0
1
Start AES engine. BUSY flag will be set
#1
STOP
AES Engine Stop\nNote: This bit is always 0 when it's read back.
1
1
read-write
0
No effect
#0
1
Stop AES engine
#1
CRPT_AES_DATIN
CRPT_AES_DATIN
AES Engine Data Input Port Register
0x108
read-write
n
0x0
0x0
DATIN
AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
0
32
read-write
CRPT_AES_DATOUT
CRPT_AES_DATOUT
AES Engine Data Output Port Register
0x10C
read-only
n
0x0
0x0
DATOUT
AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRPT_AES_STS. Get data as OUTBUFEMPTY is 0.
0
32
read-only
CRPT_AES_FDBCK0
CRPT_AES_FDBCK0
AES Engine Output Feedback Data After Cryptographic Operation
0x50
read-only
n
0x0
0x0
FDBCK
AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
0
32
read-only
CRPT_AES_FDBCK1
CRPT_AES_FDBCK1
AES Engine Output Feedback Data After Cryptographic Operation
0x54
read-write
n
0x0
0x0
CRPT_AES_FDBCK2
CRPT_AES_FDBCK2
AES Engine Output Feedback Data After Cryptographic Operation
0x58
read-write
n
0x0
0x0
CRPT_AES_FDBCK3
CRPT_AES_FDBCK3
AES Engine Output Feedback Data After Cryptographic Operation
0x5C
read-write
n
0x0
0x0
CRPT_AES_STS
CRPT_AES_STS
AES Engine Flag
0x104
-1
read-only
n
0x0
0x0
BUSERR
AES DMA Access Bus Error Flag\n
20
1
read-only
0
No error
#0
1
Bus error will stop DMA operation and AES engine
#1
BUSY
AES Engine Busy\n
0
1
read-only
0
The AES engine is idle or finished
#0
1
The AES engine is under processing
#1
CNTERR
AES_CNT Setting Error\n
12
1
read-only
0
No error in AES_CNT setting
#0
1
AES_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode
#1
INBUFEMPTY
AES Input Buffer Empty\n
8
1
read-only
0
There are some data in input buffer waiting for the AES engine to process
#0
1
AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data
#1
INBUFERR
AES Input Buffer Error Flag\n
10
1
read-only
0
No error
#0
1
Error happens during feeding data to the AES engine
#1
INBUFFULL
AES Input Buffer Full Flag\n
9
1
read-only
0
AES input buffer is not full. Software can feed the data into the AES engine
#0
1
AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1
#1
OUTBUFEMPTY
AES Out Buffer Empty\n
16
1
read-only
0
AES output buffer is not empty. There are some valid data kept in output buffer
#0
1
AES output buffer is empty. Software cannot get data from AES_DATA_OUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty
#1
OUTBUFERR
AES Out Buffer Error Flag\n
18
1
read-only
0
No error
#0
1
Error happens during getting the result from AES engine
#1
OUTBUFFULL
AES Out Buffer Full Flag\n
17
1
read-only
0
AES output buffer is not full
#0
1
AES output buffer is full, and software needs to get data from AES_DATA_OUT. Otherwise, the AES engine will be pending since the output buffer is full
#1
CRPT_INTEN
CRPT_INTEN
Crypto Interrupt Enable Control Register
0x0
read-write
n
0x0
0x0
AESERRIEN
AES Error Flag Enable Bit\n
1
1
read-write
0
AES error interrupt flag Disabled
#0
1
AES error interrupt flag Enabled
#1
AESIEN
AES Interrupt Enable Bit\nIn DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
0
1
read-write
0
AES interrupt Disabled
#0
1
AES interrupt Enabled
#1
PRNGIEN
PRNG Interrupt Enable Bit \n
16
1
read-write
0
PRNG interrupt Disabled
#0
1
PRNG interrupt Enabled
#1
SHAERRIEN
SHA Error Interrupt Enable Bit\n
25
1
read-write
0
SHA error interrupt flag Disabled
#0
1
SHA error interrupt flag Enabled
#1
SHAIEN
SHA Interrupt Enable Bit\nIn DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
24
1
read-write
0
SHA interrupt Disabled
#0
1
SHA interrupt Enabled
#1
TDESERRIEN
TDES/DES Error Flag Enable Bit\n
9
1
read-write
0
TDES/DES error interrupt flag Disabled
#0
1
TDES/DES error interrupt flag Enabled
#1
TDESIEN
TDES/DES Interrupt Enable Bit\nIn DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.\nIn Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
8
1
read-write
0
TDES/DES interrupt Disabled
#0
1
TDES/DES interrupt Enabled
#1
CRPT_INTSTS
CRPT_INTSTS
Crypto Interrupt Flag
0x4
read-write
n
0x0
0x0
AESERRIF
AES Error Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
1
1
read-write
0
No AES error
#0
1
AES encryption/decryption done interrupt
#1
AESIF
AES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
0
1
read-write
0
No AES interrupt
#0
1
AES encryption/decryption done interrupt
#1
PRNGIF
PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
16
1
read-write
0
No PRNG interrupt
#0
1
PRNG key generation done interrupt
#1
SHAERRIF
SHA Error Flag\nThis register includes operating and setting error. The detail flag is shown in SHA _FLAG register.\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
25
1
read-write
0
No SHA error
#0
1
SHA error interrupt
#1
SHAIF
SHA Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
24
1
read-write
0
No SHA interrupt
#0
1
SHA operation done interrupt
#1
TDESERRIF
TDES/DES Error Flag\nThis bit includes the operating and setting error. The detailed flag is shown in the TDES _FLAG register. This includes operating and setting error.\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
9
1
read-write
0
No TDES/DES error
#0
1
TDES/DES encryption/decryption error interrupt
#1
TDESIF
TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
8
1
read-write
0
No TDES/DES interrupt
#0
1
TDES/DES encryption/decryption done interrupt
#1
CRPT_PRNG_CTL
CRPT_PRNG_CTL
PRNG Control Register
0x8
read-write
n
0x0
0x0
BUSY
PRNG Busy (Read Only)\n
8
1
read-only
0
PRNG engine is idle
#0
1
Indicate that the PRNG engine is generating CRPT_PRNG_KEYx
#1
KEYSZ
PRNG Generate Key Size\n
2
2
read-write
0
64 bits
#00
1
128 bits
#01
2
192 bits
#10
3
256 bits
#11
SEEDRLD
Reload New Seed For PRNG Engine\n
1
1
read-write
0
Generating key based on the current seed
#0
1
Reload new seed
#1
START
Start PRNG Engine\n
0
1
read-write
0
Stop PRNG engine
#0
1
Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated
#1
CRPT_PRNG_KEY0
CRPT_PRNG_KEY0
PRNG Generated Key0
0x10
read-only
n
0x0
0x0
KEYx
Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG.
0
32
read-only
CRPT_PRNG_KEY1
CRPT_PRNG_KEY1
PRNG Generated Key1
0x14
read-write
n
0x0
0x0
CRPT_PRNG_KEY2
CRPT_PRNG_KEY2
PRNG Generated Key2
0x18
read-write
n
0x0
0x0
CRPT_PRNG_KEY3
CRPT_PRNG_KEY3
PRNG Generated Key3
0x1C
read-write
n
0x0
0x0
CRPT_PRNG_KEY4
CRPT_PRNG_KEY4
PRNG Generated Key4
0x20
read-write
n
0x0
0x0
CRPT_PRNG_KEY5
CRPT_PRNG_KEY5
PRNG Generated Key5
0x24
read-write
n
0x0
0x0
CRPT_PRNG_KEY6
CRPT_PRNG_KEY6
PRNG Generated Key6
0x28
read-write
n
0x0
0x0
CRPT_PRNG_KEY7
CRPT_PRNG_KEY7
PRNG Generated Key7
0x2C
read-write
n
0x0
0x0
CRPT_PRNG_SEED
CRPT_PRNG_SEED
Seed for PRNG
0xC
write-only
n
0x0
0x0
SEED
Seed For PRNG (Write Only)\nThe bits store the seed for PRNG engine.
0
32
write-only
CRPT_SHA_CTL
CRPT_SHA_CTL
SHA Control Register
0x300
read-write
n
0x0
0x0
DMAEN
SHA Engine DMA Enable Bit\nThe SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
7
1
read-write
0
SHA_DMA engine Disabled
#0
1
SHA_DMA engine Enabled
#1
DMALAST
SHA Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last byte of data.
5
1
read-write
INSWAP
SHA Engine Input Data Swap\n
23
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
OPMODE
SHA Engine Operation Modes\nNote: These bits can be read and written, but writing to them wouldn't take effect as BUSY is 1.
8
3
read-write
0
SHA160
#000
4
SHA256
#100
5
SHA224
#101
OUTSWAP
SHA Engine Output Data Swap\n
22
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
START
SHA Engine Start\nNote: This bit is always 0 when it's read back.
0
1
read-write
0
No effect
#0
1
Start SHA engine. BUSY flag will be set
#1
STOP
SHA Engine Stop\nNote: This bit is always 0 when it's read back.
1
1
read-write
0
No effect
#0
1
Stop SHA engine
#1
CRPT_SHA_DATIN
CRPT_SHA_DATIN
SHA Engine Non-dMA Mode Data Input Port Register
0x354
read-write
n
0x0
0x0
DATIN
SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRPT_SHA_STS. Feed data as DATINREQ is 1.
0
32
read-write
CRPT_SHA_DGST0
CRPT_SHA_DGST0
SHA Digest Message 0
0x308
read-only
n
0x0
0x0
DGST
SHA Digest Message Word\nFor SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.\nFor SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.\nFor SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
0
32
read-only
CRPT_SHA_DGST1
CRPT_SHA_DGST1
SHA Digest Message 1
0x30C
read-write
n
0x0
0x0
CRPT_SHA_DGST2
CRPT_SHA_DGST2
SHA Digest Message 2
0x310
read-write
n
0x0
0x0
CRPT_SHA_DGST3
CRPT_SHA_DGST3
SHA Digest Message 3
0x314
read-write
n
0x0
0x0
CRPT_SHA_DGST4
CRPT_SHA_DGST4
SHA Digest Message 4
0x318
read-write
n
0x0
0x0
CRPT_SHA_DGST5
CRPT_SHA_DGST5
SHA Digest Message 5
0x31C
read-write
n
0x0
0x0
CRPT_SHA_DGST6
CRPT_SHA_DGST6
SHA Digest Message 6
0x320
read-write
n
0x0
0x0
CRPT_SHA_DGST7
CRPT_SHA_DGST7
SHA Digest Message 7
0x324
read-write
n
0x0
0x0
CRPT_SHA_DMACNT
CRPT_SHA_DMACNT
SHA Byte Count Register
0x350
read-write
n
0x0
0x0
DMACNT
SHA Operation Byte Count\nThe CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. The CRPT_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRPT_SHA_DMACNT can be read and written. Writing to CRPT_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRPT_SHA_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA operation.\nIn Non-DMA mode, CRPT_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
0
32
read-write
CRPT_SHA_KEYCNT
CRPT_SHA_KEYCNT
SHA Key Byte Count Register
0x348
read-write
n
0x0
0x0
KEYCNT
SHA Key Byte Count\nThe CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRPT_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation. But the value of CRPT_SHA_KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA operation.
0
32
read-write
CRPT_SHA_SADDR
CRPT_SHA_SADDR
SHA DMA Source Address Register
0x34C
read-write
n
0x0
0x0
SADDR
SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. The CRPT_SHA_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA accelerator can read the plain text from system memory and do SHA operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRPT_SHA_SADDR are ignored.\nCRPT_SHA_SADDR can be read and written. Writing to CRPT_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRPT_SHA_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA operation.\nIn DMA mode, software can update the next TDES_SADR before triggering START.\nCRPT_SHA_SADDR and CRPT_SHA_DADDR can be the same in the value.
0
32
read-write
CRPT_SHA_STS
CRPT_SHA_STS
SHA Status Flag
0x304
read-only
n
0x0
0x0
BUSY
SHA Engine Busy \n
0
1
read-only
0
SHA engine is idle or finished
#0
1
SHA engine is busy
#1
DATINREQ
SHA Non-DMA Mode Data Input Request\n
16
1
read-only
0
No effect
#0
1
Request SHA Non-DMA mode data input
#1
DMABUSY
SHA Engine DMA Busy Flag\n
1
1
read-only
0
SHA DMA engine is idle or finished
#0
1
SHA DMA engine is busy
#1
DMAERR
SHA Engine DMA Error Flag\n
8
1
read-only
0
Show the SHA engine access normal
#0
1
Show the SHA engine access error
#1
CRPT_TDES0_CNT
CRPT_TDES0_CNT
TDES/DES Byte Count Register for Channel 0
0x230
read-write
n
0x0
0x0
CNT
TDES/DES Byte Count \nThe CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRPT_TDESn_CNT can be read and written. Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRPT_TDESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next TDES /DES operation.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
0
32
read-write
CRPT_TDES0_DADDR
CRPT_TDES0_DADDR
TDES/DES DMA Destination Address Register for Channel 0
0x22C
read-write
n
0x0
0x0
DADDR
TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. The CRPT_TDESn_DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of CRPT_TDESn_DADDR are ignored.\nTDES_DADR can be read and written. Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRPT_TDESn_DADDR will be updated later on. Consequently, software can prepare the destination address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRPT_TDESn_DADDR before triggering START. \nCRPT_TDESn_SADDR and CRPT_TDESn_DADDR can be the same in the value.
0
32
read-write
CRPT_TDES0_IVH
CRPT_TDES0_IVH
TDES/DES Initial Vector High Word Register for Channel 0
0x220
read-write
n
0x0
0x0
IVH_IVL
TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. IV is Nonce counter for TDES/DES engine in CTR mode.
0
32
read-write
CRPT_TDES0_IVL
CRPT_TDES0_IVL
TDES/DES Initial Vector Low Word Register for Channel 0
0x224
read-write
n
0x0
0x0
CRPT_TDES0_KEY1H
CRPT_TDES0_KEY1H
TDES/DES Key 1 High Word Register for Channel 0
0x208
read-write
n
0x0
0x0
KEYH_KEYL
TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits. Thus, it needs two 32-bit registers to store a security key. The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
0
32
read-write
CRPT_TDES0_KEY1L
CRPT_TDES0_KEY1L
TDES/DES Key 1 Low Word Register for Channel 0
0x20C
read-write
n
0x0
0x0
CRPT_TDES0_KEY2H
CRPT_TDES0_KEY2H
TDES Key 2 High Word Register for Channel 0
0x210
read-write
n
0x0
0x0
CRPT_TDES0_KEY2L
CRPT_TDES0_KEY2L
TDES Key 2 Low Word Register for Channel 0
0x214
read-write
n
0x0
0x0
CRPT_TDES0_KEY3H
CRPT_TDES0_KEY3H
TDES Key 3 High Word Register for Channel 0
0x218
read-write
n
0x0
0x0
CRPT_TDES0_KEY3L
CRPT_TDES0_KEY3L
TDES Key 3 Low Word Register for Channel 0
0x21C
read-write
n
0x0
0x0
CRPT_TDES0_SADDR
CRPT_TDES0_SADDR
TDES/DES DMA Source Address Register for Channel 0
0x228
read-write
n
0x0
0x0
SADDR
TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. The CRPT_TDESn_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRPT_TDESn_SADDR are ignored.\nTDES_SADR can be read and written. Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRPT_TDESn_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRPT_TDESn_SADDR before triggering START.\nCRPT_TDESn_SADDR and CRPT_TDESn_DADDR can be the same in the value.
0
32
read-write
CRPT_TDES1_CNT
CRPT_TDES1_CNT
TDES/DES Byte Count Register for Channel 1
0x270
read-write
n
0x0
0x0
CRPT_TDES1_DADDR
CRPT_TDES1_DADDR
TDES/DES DMA Destination Address Register for Channel 1
0x26C
read-write
n
0x0
0x0
CRPT_TDES1_IVH
CRPT_TDES1_IVH
TDES/DES Initial Vector High Word Register for Channel 1
0x260
read-write
n
0x0
0x0
CRPT_TDES1_IVL
CRPT_TDES1_IVL
TDES/DES Initial Vector Low Word Register for Channel 1
0x264
read-write
n
0x0
0x0
CRPT_TDES1_KEY1H
CRPT_TDES1_KEY1H
TDES/DES Key 1 High Word Register for Channel 1
0x248
read-write
n
0x0
0x0
CRPT_TDES1_KEY1L
CRPT_TDES1_KEY1L
TDES/DES Key 1 Low Word Register for Channel 1
0x24C
read-write
n
0x0
0x0
CRPT_TDES1_KEY2H
CRPT_TDES1_KEY2H
TDES Key 2 High Word Register for Channel 1
0x250
read-write
n
0x0
0x0
CRPT_TDES1_KEY2L
CRPT_TDES1_KEY2L
TDES Key 2 Low Word Register for Channel 1
0x254
read-write
n
0x0
0x0
CRPT_TDES1_KEY3H
CRPT_TDES1_KEY3H
TDES Key 3 High Word Register for Channel 1
0x258
read-write
n
0x0
0x0
CRPT_TDES1_KEY3L
CRPT_TDES1_KEY3L
TDES Key 3 Low Word Register for Channel 1
0x25C
read-write
n
0x0
0x0
CRPT_TDES1_SADDR
CRPT_TDES1_SADDR
TDES/DES DMA Source Address Register for Channel 1
0x268
read-write
n
0x0
0x0
CRPT_TDES2_CNT
CRPT_TDES2_CNT
TDES/DES Byte Count Register for Channel 2
0x2B0
read-write
n
0x0
0x0
CRPT_TDES2_DADDR
CRPT_TDES2_DADDR
TDES/DES DMA Destination Address Register for Channel 2
0x2AC
read-write
n
0x0
0x0
CRPT_TDES2_IVH
CRPT_TDES2_IVH
TDES/DES Initial Vector High Word Register for Channel 2
0x2A0
read-write
n
0x0
0x0
CRPT_TDES2_IVL
CRPT_TDES2_IVL
TDES/DES Initial Vector Low Word Register for Channel 2
0x2A4
read-write
n
0x0
0x0
CRPT_TDES2_KEY1H
CRPT_TDES2_KEY1H
TDES/DES Key 1 High Word Register for Channel 2
0x288
read-write
n
0x0
0x0
CRPT_TDES2_KEY1L
CRPT_TDES2_KEY1L
TDES/DES Key 1 Low Word Register for Channel 2
0x28C
read-write
n
0x0
0x0
CRPT_TDES2_KEY2H
CRPT_TDES2_KEY2H
TDES Key 2 High Word Register for Channel 2
0x290
read-write
n
0x0
0x0
CRPT_TDES2_KEY2L
CRPT_TDES2_KEY2L
TDES Key 2 Low Word Register for Channel 2
0x294
read-write
n
0x0
0x0
CRPT_TDES2_KEY3H
CRPT_TDES2_KEY3H
TDES Key 3 High Word Register for Channel 2
0x298
read-write
n
0x0
0x0
CRPT_TDES2_KEY3L
CRPT_TDES2_KEY3L
TDES Key 3 Low Word Register for Channel 2
0x29C
read-write
n
0x0
0x0
CRPT_TDES2_SADDR
CRPT_TDES2_SADDR
TDES/DES DMA Source Address Register for Channel 2
0x2A8
read-write
n
0x0
0x0
CRPT_TDES3_CNT
CRPT_TDES3_CNT
TDES/DES Byte Count Register for Channel 3
0x2F0
read-write
n
0x0
0x0
CRPT_TDES3_DADDR
CRPT_TDES3_DADDR
TDES/DES DMA Destination Address Register for Channel 3
0x2EC
read-write
n
0x0
0x0
CRPT_TDES3_IVH
CRPT_TDES3_IVH
TDES/DES Initial Vector High Word Register for Channel 3
0x2E0
read-write
n
0x0
0x0
CRPT_TDES3_IVL
CRPT_TDES3_IVL
TDES/DES Initial Vector Low Word Register for Channel 3
0x2E4
read-write
n
0x0
0x0
CRPT_TDES3_KEY1H
CRPT_TDES3_KEY1H
TDES/DES Key 1 High Word Register for Channel 3
0x2C8
read-write
n
0x0
0x0
CRPT_TDES3_KEY1L
CRPT_TDES3_KEY1L
TDES/DES Key 1 Low Word Register for Channel 3
0x2CC
read-write
n
0x0
0x0
CRPT_TDES3_KEY2H
CRPT_TDES3_KEY2H
TDES Key 2 High Word Register for Channel 3
0x2D0
read-write
n
0x0
0x0
CRPT_TDES3_KEY2L
CRPT_TDES3_KEY2L
TDES Key 2 Low Word Register for Channel 3
0x2D4
read-write
n
0x0
0x0
CRPT_TDES3_KEY3H
CRPT_TDES3_KEY3H
TDES Key 3 High Word Register for Channel 3
0x2D8
read-write
n
0x0
0x0
CRPT_TDES3_KEY3L
CRPT_TDES3_KEY3L
TDES Key 3 Low Word Register for Channel 3
0x2DC
read-write
n
0x0
0x0
CRPT_TDES3_SADDR
CRPT_TDES3_SADDR
TDES/DES DMA Source Address Register for Channel 3
0x2E8
read-write
n
0x0
0x0
CRPT_TDES_CTL
CRPT_TDES_CTL
TDES/DES Control Register
0x200
read-write
n
0x0
0x0
BLKSWAP
TDES/DES Engine Block Double Word Endian Swap \n
21
1
read-write
0
Keep the original order, e.g. {WORD_H, WORD_L}
#0
1
When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}
#1
CHANNEL
TDES/DES Engine Working Channel\n
24
2
read-write
0
Current control register setting is for channel 0
#00
1
Current control register setting is for channel 1
#01
2
Current control register setting is for channel 2
#10
3
Current control register setting is for channel 3
#11
DMACSCAD
TDES/DES Engine DMA With Cascade Mode\n
6
1
read-write
0
DMA cascade function Disabled
#0
1
In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
#1
DMAEN
TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
7
1
read-write
0
TDES_DMA engine Disabled
#0
1
TDES_DMA engine Enabled
#1
DMALAST
TDES/DES Engine Start For The Last Block \nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last block of data.
5
1
read-write
ENCRPT
TDES/DES Encryption/Decryption\n
16
1
read-write
0
TDES engine executes decryption operation
#0
1
TDES engine executes encryption operation
#1
INSWAP
TDES/DES Engine Input Data Swap \n
23
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
KEYPRT
Protect Key\nRead as a flag to reflect KEYPRT.\n
31
1
read-write
0
No effect
#0
1
This bit is to protect the content of TDES key from reading. The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L. Once it is set, it can be cleared by asserting KEYUNPRT. The key content would be cleared as well
#1
KEYUNPRT
Unprotect Key
Writing 0 to CRPT_TDES_CTL [31] and 10110 to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
The KEYUNPRT can be read and written. When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
26
5
read-write
OPMODE
TDES/DES Engine Operation Mode\n
8
3
read-write
0
ECB (Electronic Codebook Mode)
0x00
1
CBC (Cipher Block Chaining Mode)
0x01
2
CFB (Cipher Feedback Mode)
0x02
3
OFB (Output Feedback Mode)
0x03
4
CTR (Counter Mode)
0x04
OUTSWAP
TDES/DES Engine Output Data Swap \n
22
1
read-write
0
Keep the original order
#0
1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
START
TDES/DES Engine Start\nNote: The bit is always 0 when it's read back.
0
1
read-write
0
No effect
#0
1
Start TDES/DES engine. The flag BUSY would be set
#1
STOP
TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back.
1
1
read-write
0
No effect
#0
1
Stop TDES/DES engine
#1
TMODE
TDES/DES Engine Operating Mode\n
2
1
read-write
0
Set DES mode for TDES/DES engine
#0
1
Set Triple DES mode for TDES/DES engine
#1
_3KEYS
TDES/DES Key Number\n
3
1
read-write
0
Select KEY1 and KEY2 in TDES/DES engine
#0
1
Triple keys in TDES/DES engine Enabled
#1
CRPT_TDES_DATIN
CRPT_TDES_DATIN
TDES/DES Engine Input Data Word Register
0x234
read-write
n
0x0
0x0
DATIN
TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS. Feed data as INBUFFULL is 0.
0
32
read-write
CRPT_TDES_DATOUT
CRPT_TDES_DATOUT
TDES/DES Engine Output Data Word Register
0x238
read-only
n
0x0
0x0
DATOUT
TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS. Get data as OUTBUFEMPTY is 0.
0
32
read-only
CRPT_TDES_FDBCKH
CRPT_TDES_FDBCKH
TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation
0x60
read-only
n
0x0
0x0
FDBCK
TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode. The feedback register is for CBC, CFB, and OFB mode.\nTDES/DES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to this register in the same channel operation. Then can continue the operation with the original setting.
0
32
read-only
CRPT_TDES_FDBCKL
CRPT_TDES_FDBCKL
TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation
0x64
read-write
n
0x0
0x0
CRPT_TDES_STS
CRPT_TDES_STS
TDES/DES Engine Flag
0x204
-1
read-only
n
0x0
0x0
BUSERR
TDES/DES DMA Access Bus Error Flag\n
20
1
read-only
0
No error
#0
1
Bus error will stop DMA operation and TDES/DES engine
#1
BUSY
TDES/DES Engine Busy \n
0
1
read-only
0
TDES/DES engine is idle or finished
#0
1
TDES/DES engine is under processing
#1
INBUFEMPTY
TDES/DES In Buffer Empty\n
8
1
read-only
0
There are some data in input buffer waiting for the TDES/DES engine to process
#0
1
TDES/DES input buffer is empty. Software needs to feed data to the TDES/DES engine. Otherwise, the TDES/DES engine will be pending to wait for input data
#1
INBUFERR
TDES/DES In Buffer Error Flag\n
10
1
read-only
0
No error
#0
1
Error happens during feeding data to the TDES/DES engine
#1
INBUFFULL
TDES/DES In Buffer Full Flag\n
9
1
read-only
0
TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine
#0
1
TDES input buffer is full. Software cannot feed data to the TDES/DES engine. Otherwise, the flag INBUFERR will be set to 1
#1
OUTBUFEMPTY
TDES/DES Output Buffer Empty Flag\n
16
1
read-only
0
TDES/DES output buffer is not empty. There are some valid data kept in output buffer
#0
1
TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT. Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty
#1
OUTBUFERR
TDES/DES Out Buffer Error Flag\n
18
1
read-only
0
No error
#0
1
Error happens during getting test result from TDES/DES engine
#1
OUTBUFFULL
TDES/DES Output Buffer Full Flag\n
17
1
read-only
0
TDES/DES output buffer is not full
#0
1
TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT. Otherwise, the TDES/DES engine will be pending since output buffer is full
#1
EADC
EADC Register Map
EADC
0x0
0x0
0x44
registers
n
0x100
0x10
registers
n
0x120
0x44
registers
n
0x48
0x50
registers
n
0xA4
0x18
registers
n
AD0DAT0
EADC_AD0DAT0
A/D Data Register 0 for SAMPLE00
0x0
read-only
n
0x0
0x0
OV
Overrun Flag\n
16
1
read-only
0
Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result
#0
1
Data in RESULT (EADC_ADnDATx[11:0]) is overwrite
#1
RESULT
A/D Conversion Result\nThis field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag\n
17
1
read-only
0
Data in RESULT (EADC_ADnDATx[11:0]) is not valid
#0
1
Data in RESULT (EADC_ADnDATx[11:0]) is valid
#1
AD0DAT1
EADC_AD0DAT1
A/D Data Register 1 for SAMPLE01
0x4
read-write
n
0x0
0x0
AD0DAT2
EADC_AD0DAT2
A/D Data Register 2 for SAMPLE02
0x8
read-write
n
0x0
0x0
AD0DAT3
EADC_AD0DAT3
A/D Data Register 3 for SAMPLE03
0xC
read-write
n
0x0
0x0
AD0DAT4
EADC_AD0DAT4
A/D Data Register 4 for SAMPLE04
0x10
read-write
n
0x0
0x0
AD0DAT5
EADC_AD0DAT5
A/D Data Register 5 for SAMPLE05
0x14
read-write
n
0x0
0x0
AD0DAT6
EADC_AD0DAT6
A/D Data Register 6 for SAMPLE06
0x18
read-write
n
0x0
0x0
AD0DAT7
EADC_AD0DAT7
A/D Data Register 7 for SAMPLE07
0x1C
read-write
n
0x0
0x0
AD0DDAT0
EADC_AD0DDAT0
A/D Double Data Register 0 for SAMPLE00
0x100
read-only
n
0x0
0x0
RESULT
A/D Conversion Result\nThis field contains 12 bits conversion result.
0
12
read-only
VALID
Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
16
1
read-only
0
Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid
#0
1
Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid
#1
AD0DDAT1
EADC_AD0DDAT1
A/D Double Data Register 1 for SAMPLE01
0x104
read-write
n
0x0
0x0
AD0DDAT2
EADC_AD0DDAT2
A/D Double Data Register 2 for SAMPLE02
0x108
read-write
n
0x0
0x0
AD0DDAT3
EADC_AD0DDAT3
A/D Double Data Register 3 for SAMPLE03
0x10C
read-write
n
0x0
0x0
AD0SPCTL0
EADC_AD0SPCTL0
A/D SAMPLE00 Control Register
0x58
read-write
n
0x0
0x0
CHSEL
A/D SAMPLE MODULE 0,1 Channel Selection\n
0
4
read-write
0
ADCn_CH0
#0000
1
ADCn_CH1
#0001
2
ADCn_CH2
#0010
3
ADCn_CH3
#0011
4
ADCn_CH4
#0100
5
ADCn_CH5
#0101
6
ADCn_CH6
#0110
7
ADCn_CH7
#0111
8
VBG.\nOP1
#1000
9
VTEMP
#1001
10
AVSS
#1010
11
OP0
#1011
EXTFEN
A/D External Pin Falling Edge Trigger Enable Bit\n
21
1
read-write
0
A/D external pin falling edge trigger Disabled
#0
1
A/D external pin falling edge trigger Enabled
#1
EXTREN
A/D External Pin Rising Edge Trigger Enable Bit\n
20
1
read-write
0
A/D external pin rising edge trigger Disabled
#0
1
A/D external pin rising edge trigger Enabled
#1
TRGDLYCNT
A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n
8
8
read-write
TRGDLYDIV
A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n
16
2
read-write
0
ADC_CLK/1
#00
1
ADC_CLK/2
#01
2
ADC_CLK/4
#10
3
ADC_CLK/16
#11
TRGSEL
A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n
4
4
read-write
0
Disable hardware trigger
#0000
1
External pin (STADC) trigger
#0001
2
ADC ADINT0 interrupt EOC pulse trigger
#0010
3
ADC ADINT1 interrupt EOC pulse trigger
#0011
4
Timer0 overflow pulse trigger
#0100
5
Timer1 overflow pulse trigger
#0101
6
Timer2 overflow pulse trigger
#0110
7
Timer3 overflow pulse trigger
#0111
8
EPWM0_CH0 trigger
#1000
9
EPWM0_CH2 trigger
#1001
10
EPWM0_CH4 trigger
#1010
11
EPWM1_CH0 trigger
#1011
12
EPWM1_CH2 trigger
#1100
13
EPWM1_CH4 trigger
#1101
14
PWM0_CH0 trigger
#1110
15
PWM0_CH1 trigger
#1111
AD0SPCTL1
EADC_AD0SPCTL1
A/D SAMPLE01 Control Register
0x5C
read-write
n
0x0
0x0
AD0SPCTL2
EADC_AD0SPCTL2
A/D SAMPLE02 Control Register
0x60
read-write
n
0x0
0x0
AD0SPCTL3
EADC_AD0SPCTL3
A/D SAMPLE03 Control Register
0x64
read-write
n
0x0
0x0
AD0SPCTL4
EADC_AD0SPCTL4
A/D SAMPLE04 Control Register
0x68
read-write
n
0x0
0x0
SIMUSEL0
A/D SAMPLE00, SAMPLE10 Simultaneous Sampling Mode Selection\n
0
1
read-write
0
SAMPLE00, SAMPLE10 are in single sampling mode, both SAMPLE00 and SAMPLE10's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE00, SAMPLE10 are in simultaneous sampling mode, Only SAMPLE00 can trigger the both ADC conversions of SAMPLE00 and SAMPLE10, SAMPLE10 trigger select TRGSEL is ignored. If SAMPLE00's CHSEL = 1, and SAMPLE10's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL1
A/D SAMPLE01, SAMPLE11 Simultaneous Sampling Mode Selection\n
1
1
read-write
0
SAMPLE01, SAMPLE11 are in single sampling mode, both SAMPLE01 and SAMPLE11's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE01, SAMPLE11 are in simultaneous sampling mode, Only SAMPLE01 can trigger the both ADC conversions of SAMPLE01 and SAMPLE11, SAMPLE11 trigger select TRGSEL is ignored. If SAMPLE01's CHSEL = 1, and SAMPLE11's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL2
A/D SAMPLE02, SAMPLE12 Simultaneous Sampling Mode Selection\n
2
1
read-write
0
SAMPLE02, SAMPLE12 are in single sampling mode, both SAMPLE02 and SAMPLE12's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE02, SAMPLE12 are in simultaneous sampling mode, Only SAMPLE02 can trigger the both ADC conversions of SAMPLE02 and SAMPLE12, SAMPLE12 trigger select TRGSEL is ignored. If SAMPLE02's CHSEL = 1, and SAMPLE12's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL3
A/D SAMPLE03, SAMPLE13 Simultaneous Sampling Mode Selection\n
3
1
read-write
0
SAMPLE03, SAMPLE13 are in single sampling mode, both SAMPLE03 and SAMPLE13's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE03, SAMPLE13 are in simultaneous sampling mode, Only SAMPLE03 can trigger the both ADC conversions of SAMPLE03 and SAMPLE13, SAMPLE13 trigger select TRGSEL is ignored. If SAMPLE03's CHSEL = 1, and SAMPLE13's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL4
A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection\n
4
1
read-write
0
SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored. If SAMPLE04's CHSEL = 1, and SAMPLE14's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL5
A/D SAMPLE05, SAMPLE15 Simultaneous Sampling Mode Selection\n
5
1
read-write
0
SAMPLE05, SAMPLE15 are in single sampling mode, both SAMPLE05 and SAMPLE15's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE05, SAMPLE15 are in simultaneous sampling mode, Only SAMPLE05 can trigger the both ADC conversions of SAMPLE05 and SAMPLE15, SAMPLE15 trigger select TRGSEL is ignored. if SAMPLE05's CHSEL = 1, and SAMPLE15's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL6
A/D SAMPLE06, SAMPLE16 Simultaneous Sampling Mode Selection\n
6
1
read-write
0
SAMPLE06, SAMPLE16 are in single sampling mode, both SAMPLE06 and SAMPLE16's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE06, SAMPLE16 are in simultaneous sampling mode, Only SAMPLE06 can trigger the both ADC conversions of SAMPLE06 and SAMPLE16, SAMPLE16 trigger select TRGSEL is ignored. If SAMPLE06's CHSEL = 1, and SAMPLE16's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
SIMUSEL7
A/D SAMPLE07, SAMPLE17 Simultaneous Sampling Mode Selection \n
7
1
read-write
0
SAMPLE07, SAMPLE17 are in single sampling mode, both SAMPLE07 and SAMPLE17's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLE07, SAMPLE17 are in simultaneous sampling mode, Only SAMPLE07 can trigger the both ADC conversions of SAMPLE07 and SAMPLE17, SAMPLE17 trigger select TRGSEL is ignored. If SAMPLE07's CHSEL = 1, SAMPLE17's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
#1
AD0SPCTL5
EADC_AD0SPCTL5
A/D SAMPLE05 Control Register
0x6C
read-write
n
0x0
0x0
AD0SPCTL6
EADC_AD0SPCTL6
A/D SAMPLE06 Control Register
0x70
read-write
n
0x0
0x0
AD0SPCTL7
EADC_AD0SPCTL7
A/D SAMPLE07 Control Register
0x74
read-write
n
0x0
0x0
AD0TRGEN0
EADC_AD0TRGEN0
A/D Trigger Condition for SAMPLE00
0x144
read-write
n
0x0
0x0
EPWM00CEN
EPWM0_CH0 Center Trigger Enable Bit\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM00FEN
EPWM0_CH0 Falling Edge Trigger Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM00PEN
EPWM0_CH0 Period Trigger Enable Bit\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM00REN
EPWM0_CH0 Rising Edge Trigger Enable Bit\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM02CEN
EPWM0_CH2 Center Trigger Enable Bit\n
7
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM02FEN
EPWM0_CH2 Falling Edge Trigger Enable Bit\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM02PEN
EPWM0_CH2 Period Trigger Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM02REN
EPWM0_CH2 Rising Edge Trigger Enable Bit\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM04CEN
EPWM0_CH4 Center Trigger Enable Bit\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM04FEN
EPWM0_CH4 Falling Rdge Trigger Enable Bit\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM04PEN
EPWM0_CH4 Period Trigger Enable Bit\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM04REN
EPWM0_CH4 Rising Edge Trigger Enable Bit\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM10CEN
EPWM1_CH0 Center Trigger Enable Bit\n
15
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM10FEN
EPWM1_CH0 Falling Edge Trigger Enable Bit\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM10PEN
EPWM1_CH0 Period Trigger Enable Bit\n
14
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM10REN
EPWM1_CH0 Rising Edge Trigger Enable Bit\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM120FEN
EPWM1_CH2 Falling Edge Trigger Enable Bit\n
17
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM12CEN
EPWM1_CH2 Center Trigger Enable Bit\n
19
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM12PEN
EPWM1_CH2 Period Trigger Enable Bit\n
18
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM12REN
EPWM1_CH2 Rising Edge Trigger Enable Bit\n
16
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM14CEN
EPWM1_CH4 Center Trigger Enable Bit\n
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM14FEN
EPWM1_CH4 Falling Edge Trigger Enable Bit\n
21
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM14PEN
EPWM1_CH4 Period Trigger Enable Bit\n
22
1
read-write
0
Disabled
#0
1
Enabled
#1
EPWM14REN
EPWM1_CH4 Rising Edge Trigger Enable Bit\n
20
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM00CEN
PWM0_CH0 Center Trigger Enable Bit\n
27
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM00FEN
PWM0_CH0 Falling Edge Trigger Enable Bit\n
25
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM00PEN
PWM0_CH0 Period Trigger Enable Bit\n
26
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM00REN
PWM0_CH0 Rising Edge Trigger Enable Bit\n
24
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01CEN
PWM0_CH1 Center Trigger Enable Bit\n
31
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01FEN
PWM0_CH1 Falling Edge Trigger Enable Bit\n
29
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01PEN
PWM0_CH1 Period Trigger Enable Bit\n
30
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01REN
PWM0_CH1 Rising Edge Trigger Enable Bit\n
28
1
read-write
0
Disabled
#0
1
Enabled
#1
AD0TRGEN1
EADC_AD0TRGEN1
A/D Trigger Condition for SAMPLE01
0x148
read-write
n
0x0
0x0
AD0TRGEN2
EADC_AD0TRGEN2
A/D Trigger Condition for SAMPLE02
0x14C
read-write
n
0x0
0x0
AD0TRGEN3
EADC_AD0TRGEN3
A/D Trigger Condition for SAMPLE03
0x150
read-write
n
0x0
0x0
AD1DAT0
EADC_AD1DAT0
A/D Data Register 8 for SAMPLE10
0x20
read-write
n
0x0
0x0
AD1DAT1
EADC_AD1DAT1
A/D Data Register 9 for SAMPLE11
0x24
read-write
n
0x0
0x0
AD1DAT2
EADC_AD1DAT2
A/D Data Register 10 for SAMPLE12
0x28
read-write
n
0x0
0x0
AD1DAT3
EADC_AD1DAT3
A/D Data Register 11 for SAMPLE13
0x2C
read-write
n
0x0
0x0
AD1DAT4
EADC_AD1DAT4
A/D Data Register 12 for SAMPLE14
0x30
read-write
n
0x0
0x0
AD1DAT5
EADC_AD1DAT5
A/D Data Register 13 for SAMPLE15
0x34
read-write
n
0x0
0x0
AD1DAT6
EADC_AD1DAT6
A/D Data Register 14 for SAMPLE16
0x38
read-write
n
0x0
0x0
AD1DAT7
EADC_AD1DAT7
A/D Data Register 15 for SAMPLE17
0x3C
read-write
n
0x0
0x0
AD1DDAT0
EADC_AD1DDAT0
A/D Double Data Register 0 for SAMPLE10
0x120
read-write
n
0x0
0x0
AD1DDAT1
EADC_AD1DDAT1
A/D Double Data Register 1 for SAMPLE11
0x124
read-write
n
0x0
0x0
AD1DDAT2
EADC_AD1DDAT2
A/D Double Data Register 2 for SAMPLE12
0x128
read-write
n
0x0
0x0
AD1DDAT3
EADC_AD1DDAT3
A/D Double Data Register 3 for SAMPLE13
0x12C
read-write
n
0x0
0x0
AD1SPCTL0
EADC_AD1SPCTL0
A/D SAMPLE10 Control Register
0x78
read-write
n
0x0
0x0
AD1SPCTL1
EADC_AD1SPCTL1
A/D SAMPLE11 Control Register
0x7C
read-write
n
0x0
0x0
AD1SPCTL2
EADC_AD1SPCTL2
A/D SAMPLE12 Control Register
0x80
read-write
n
0x0
0x0
AD1SPCTL3
EADC_AD1SPCTL3
A/D SAMPLE13 Control Register
0x84
read-write
n
0x0
0x0
AD1SPCTL4
EADC_AD1SPCTL4
A/D SAMPLE14 Control Register
0x88
read-write
n
0x0
0x0
AD1SPCTL5
EADC_AD1SPCTL5
A/D SAMPLE15 Control Register
0x8C
read-write
n
0x0
0x0
AD1SPCTL6
EADC_AD1SPCTL6
A/D SAMPLE16 Control Register
0x90
read-write
n
0x0
0x0
AD1SPCTL7
EADC_AD1SPCTL7
A/D SAMPLE17 Control Register
0x94
read-write
n
0x0
0x0
AD1TRGEN0
EADC_AD1TRGEN0
A/D Trigger Condition for SAMPLE10
0x154
read-write
n
0x0
0x0
AD1TRGEN1
EADC_AD1TRGEN1
A/D Trigger Condition for SAMPLE11
0x158
read-write
n
0x0
0x0
AD1TRGEN2
EADC_AD1TRGEN2
A/D Trigger Condition for SAMPLE12
0x15C
read-write
n
0x0
0x0
AD1TRGEN3
EADC_AD1TRGEN3
A/D Trigger Condition for SAMPLE13
0x160
read-write
n
0x0
0x0
ADIFOV
EADC_ADIFOV
A/D ADINT3~0 Interrupt Flag Overrun Register
0x50
read-write
n
0x0
0x0
SPOVF15_8
A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag\n
8
8
read-write
0
No SAMPLE1x event overrun
0
1
Indicates a new SAMPLE1x event is generated while an old one event is pending
1
SPOVF7_0
A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag\n
0
8
read-write
0
No SAMPLE0x event overrun
0
1
Indicates a new SAMPLE0x event is generated while an old one event is pending
1
CMP0
EADC_CMP0
A/D Result Compare Register 0
0xA8
read-write
n
0x0
0x0
ADCMPEN
A/D Result Compare Enable Bit\nSet this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE MODULE conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare Disabled
#0
1
Compare Enabled
#1
ADCMPIE
A/D Result Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]), ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted, in the meanwhile, if ADCMPIE (EADC_CMPx[1]) is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1, the CMPF bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one
#1
CMPDAT
Compared Data\nThe 12 bits data is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
16
12
read-write
CMPMCNT
Compare Match Count\nWhen the specified A/D SAMPLE MODULE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]), the internal match counter will increase 1. When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8] + 1, the ADCMPF (EADC_STATUS1 [7:6]) bit will be set.
8
4
read-write
CMPSPL
Compare SAMPLE MODULE Selection\n
3
3
read-write
0
SAMPLE00 conversion result EADC_AD0DAT0 is selected to be compared
#000
1
SAMPLE01 conversion result EADC_AD0DAT1 is selected to be compared
#001
2
SAMPLE02 conversion result EADC_AD0DAT2 is selected to be compared
#010
3
SAMPLE03 conversion result EADC_AD0DAT3 is selected to be compared
#011
4
SAMPLE10 conversion result EADC_AD1DAT0 is selected to be compared
#100
5
SAMPLE11 conversion result EADC_AD1DAT1 is selected to be compared
#101
6
SAMPLE12 conversion result EADC_AD1DAT2 is selected to be compared
#110
7
SAMPLE13 conversion result EADC_AD1DAT3 is selected to be compared
#111
CMP1
EADC_CMP1
A/D Result Compare Register 1
0xAC
read-write
n
0x0
0x0
CTL
EADC_CTL
A/D Control Register
0x40
read-write
n
0x0
0x0
SWTRG15_8
A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion\n
8
8
read-write
0
No effect
0
1
Start an ADC conversion when the priority is given to SAMPLE1x
1
SWTRG7_0
A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion\n
0
8
read-write
0
No effect
0
1
Start an ADC conversion when the priority is given to SAMPLE0x
1
DBMEN
EADC_DBMEN
A/D Double Buffer Mode Select
0x130
read-write
n
0x0
0x0
AD0DBM0
Double Buffer Mode For SAMPLE00 \n
0
1
read-write
0
SAMPLE00 has one sample result register. (default)
#0
1
SAMPLE00 has two sample result registers
#1
AD0DBM1
Double Buffer Mode For SAMPLE01 \n
1
1
read-write
0
SAMPLE01 has one sample result register. (default)
#0
1
SAMPLE01 has two sample result registers
#1
AD0DBM2
Double Buffer Mode For SAMPLE02 \n
2
1
read-write
0
SAMPLE02 has one sample result register. (default).
#0
1
SAMPLE02 has two sample result registers
#1
AD0DBM3
Double Buffer Mode For SAMPLE03 \n
3
1
read-write
0
SAMPLE03 has one sample result register. (default)
#0
1
SAMPLE03 has two sample result registers
#1
AD1DBM0
Double Buffer Mode For SAMPLE10 \n
8
1
read-write
0
SAMPLE10 has one sample result register. (default)
#0
1
SAMPLE10 has two sample result registers
#1
AD1DBM1
Double Buffer Mode For SAMPLE11 \n
9
1
read-write
0
SAMPLE11 has one sample result register. (default)
#0
1
SAMPLE11 has two sample result registers
#1
AD1DBM2
Double Buffer Mode For SAMPLE12 \n
10
1
read-write
0
SAMPLE12 has one sample result register. (default).
#0
1
SAMPLE12 has two sample result registers
#1
AD1DBM3
Double Buffer Mode For SAMPLE13 \n
11
1
read-write
0
SAMPLE13 has one sample result register. (default)
#0
1
SAMPLE13 has two sample result registers
#1
EXTSMPT
EADC_EXTSMPT
A/D Timing Control Register
0xB8
read-write
n
0x0
0x0
EXTSMPT0
ADC0 Extend Sampling Time
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
0
8
read-write
EXTSMPT1
ADC1 Extend Sampling Time
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
16
8
read-write
INTSRC0
EADC_INTSRC0
A/D Interrupt 0 Source Enable Control Register
0x134
read-write
n
0x0
0x0
AD0SPIE0
SAMPLE00 Interrupt Mask Enable Bit\n
0
1
read-write
0
SAMPLE00 interrupt mask Disabled
#0
1
SAMPLE00 interrupt mask Enabled
#1
AD0SPIE1
SAMPLE01 Interrupt Mask Enable Bit\n
1
1
read-write
0
SAMPLE01 interrupt mask Disabled
#0
1
SAMPLE01 interrupt mask Enabled
#1
AD0SPIE2
SAMPLE02 Interrupt Mask Enable Bit\n
2
1
read-write
0
SAMPLE02 interrupt mask Disabled
#0
1
SAMPLE02 interrupt mask Enabled
#1
AD0SPIE3
SAMPLE03 Interrupt Mask Enable Bit\n
3
1
read-write
0
SAMPLE03 interrupt mask Disabled
#0
1
SAMPLE03 interrupt mask Enabled
#1
AD0SPIE4
SAMPLE04 Interrupt Mask Enable Bit\n
4
1
read-write
0
SAMPLE04 interrupt mask Disabled
#0
1
SAMPLE04 interrupt mask Enabled
#1
AD0SPIE5
SAMPLE05 Interrupt Mask Enable Bit\n
5
1
read-write
0
SAMPLE05 interrupt mask Disabled
#0
1
SAMPLE05 interrupt mask Enabled
#1
AD0SPIE6
SAMPLE06 Interrupt Mask Enable Bit\n
6
1
read-write
0
SAMPLE06 interrupt mask Disabled
#0
1
SAMPLE06 interrupt mask Enabled
#1
AD0SPIE7
SAMPLE07 Interrupt Mask Enable Bit\n
7
1
read-write
0
SAMPLE07 interrupt mask Disabled
#0
1
SAMPLE07 interrupt mask Enabled
#1
AD1SPIE0
SAMPLE10 Interrupt Mask Enable Bit\n
8
1
read-write
0
SAMPLE10 interrupt mask Disabled
#0
1
SAMPLE10 interrupt mask Enabled
#1
AD1SPIE1
SAMPLE11 Interrupt Mask Enable Bit\n
9
1
read-write
0
SAMPLE11 interrupt mask Disabled
#0
1
SAMPLE11 interrupt mask Enabled
#1
AD1SPIE2
SAMPLE12 Interrupt Mask Enable Bit\n
10
1
read-write
0
SAMPLE12 interrupt mask Disabled
#0
1
SAMPLE12 interrupt mask Enabled
#1
AD1SPIE3
SAMPLE13 Interrupt Mask Enable Bit\n
11
1
read-write
0
SAMPLE13 interrupt mask Disabled
#0
1
SAMPLE13 interrupt mask Enabled
#1
AD1SPIE4
SAMPLE14 Interrupt Mask Enable Bit\n
12
1
read-write
0
SAMPLE14 interrupt mask Disabled
#0
1
SAMPLE14 interrupt mask Enabled
#1
AD1SPIE5
SAMPLE15 Interrupt Mask Enable Bit\n
13
1
read-write
0
SAMPLE15 interrupt mask Disabled
#0
1
SAMPLE15 interrupt mask Enabled
#1
AD1SPIE6
SAMPLE16 Interrupt Mask Enable Bit\n
14
1
read-write
0
SAMPLE16 interrupt mask Disabled
#0
1
SAMPLE16 interrupt mask Enabled
#1
AD1SPIE7
SAMPLE17 Interrupt Mask Enable Bit\n
15
1
read-write
0
SAMPLE17 interrupt mask Disabled
#0
1
SAMPLE17 interrupt mask Enabled
#1
INTSRC1
EADC_INTSRC1
A/D Interrupt 1 Source Enable Control Register
0x138
read-write
n
0x0
0x0
INTSRC2
EADC_INTSRC2
A/D Interrupt 2 Source Enable Control Register
0x13C
read-write
n
0x0
0x0
INTSRC3
EADC_INTSRC3
A/D Interrupt 3 Source Enable Control Register
0x140
read-write
n
0x0
0x0
OVSTS
EADC_OVSTS
A/D SAMPLE Module Start of Conversion Overrun Flag Register
0x54
read-write
n
0x0
0x0
PENDSTS
EADC_PENDSTS
A/D Start of Conversion Pending Flag Register
0x4C
read-only
n
0x0
0x0
STPF15_8
A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag \n
8
8
read-only
0
There is no pending conversion for SAMPLE1x
0
1
SAMPLE1x ADC start of conversion is pending
1
STPF7_0
A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag\n
0
8
read-only
0
There is no pending conversion for SAMPLE0x
0
1
SAMPLE0x ADC start of conversion is pending
1
SIMUSEL
EADC_SIMUSEL
A/D SAMPLE Module Simultaneous Sampling Mode Select Register
0xA4
read-write
n
0x0
0x0
STATUS0
EADC_STATUS0
A/D Status Register 0
0xB0
read-only
n
0x0
0x0
OV15_8
ADDR17~ADDR10 Overrun Flag (Read Only)\nIt is a mirror to OV bit in SAMPLE 1 A/D result data register EADC_AD0DAT1x.\n
24
8
read-only
OV7_0
ADDR07~ ADDR00 Overrun Flag (Read Only)\nIt is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.\n
16
8
read-only
VALID15_8
ADDR17~ ADDR10 Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.\n
8
8
read-only
VALID7_0
ADDR07~ ADDR00 Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.\n
0
8
read-only
STATUS1
EADC_STATUS1
A/D Status Register 1
0xB4
read-write
n
0x0
0x0
ADCMPF0
ADC Compare 0 Flag\nWhen the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
6
1
read-write
0
Conversion result in ADDR does not meet EADC_CMP0 setting
#0
1
Conversion result in ADDR meets EADC_CMP0 setting
#1
ADCMPF1
ADC Compare 1 Flag\nWhen the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
7
1
read-write
0
Conversion result in ADDR does not meet EADC_CMP1 setting
#0
1
Conversion result in ADDR meets EADC_CMP1 setting
#1
ADCMPO0
ADC Compare 0 Output Status
The 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE MODULE. Software can use it to monitor the external analog input pin voltage status.
4
1
read-write
0
Conversion result in ADDR less than CMPDAT (EADC_CMP0 [27:16]) setting
#0
1
Conversion result in ADDR great than or equal CMPDAT (EADC_CMP0 [27:16]) setting
#1
ADCMPO1
ADC Compare 1 Output Status
The 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE MODULE. Software can use it to monitor the external analog input pin voltage status.
5
1
read-write
0
Conversion result in ADDR less than CMPDAT EADC_CMP1 [27:16]) setting
#0
1
Conversion result in ADDR great than or equal CMPDAT (EADC_CMP1 [27:16]) setting
#1
ADIF0
A/D ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
0
1
read-write
0
No ADINT0 interrupt pulse received
#0
1
ADINT0 interrupt pulse has been received
#1
ADIF1
A/D ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
1
1
read-write
0
No ADINT1 interrupt pulse received
#0
1
ADINT1 interrupt pulse has been received
#1
ADIF2
A/D ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it. \nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
2
1
read-write
0
no ADINT2 interrupt pulse received
#0
1
ADINT2 interrupt pulse has been received
#1
ADIF3
A/D ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
3
1
read-write
0
No ADINT3 interrupt pulse received
#0
1
ADINT3 interrupt pulse has been received
#1
ADOVIF
All A/D Interrupt Flag Overrun Bits Check \nNote: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1.
24
1
read-write
0
None of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1
#0
1
Any one of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1
#1
AOV
For All SAMPLE MODULE A/D Result Data Register Overrun Flags Check \nNote: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1.
27
1
read-write
0
None of SAMPLE MODULE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1
#0
1
Any one of SAMPLE MODULE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1
#1
AVALID
For All SAMPLE MODULE A/D Result Data Register ADDR Data Valid Flag Check\nNote: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1.
26
1
read-write
0
None of SAMPLE MODULE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1
#0
1
Any one of SAMPLE MODULE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1
#1
BUSY0
Busy/Idle (Read Only)\n
8
1
read-only
0
A/D converter 0 (ADC0) is in idle state
#0
1
A/D converter 0 (ADC0) is doing conversion
#1
BUSY1
Busy/Idle\n
16
1
read-write
0
A/D converter 1 (ADC1) is in idle state
#0
1
A/D converter 1 (ADC1) is doing conversion
#1
CHANNEL0
Current Conversion Channel (Read Only)\n
12
4
read-only
0
ADC0_CH0
#0000
1
ADC0_CH1
#0001
2
ADC0_CH2
#0010
3
ADC0_CH3
#0011
4
ADC0_CH4.\nADC0_CH5
#0100
6
ADC0_CH6
#0110
7
ADC0_CH7
#0111
8
VBG
#1000
9
VTEMP
#1001
10
AVSS
#1010
11
OPA0_O
#1011
CHANNEL1
Current Conversion Channel (Read Only)\n
20
4
read-only
0
ADC1_CH0
#0000
1
ADC1_CH1
#0001
2
ADC1_CH2
#0010
3
ADC1_CH3
#0011
4
ADC1_CH4
#0100
5
ADC1_CH5
#0101
6
ADC1_CH6
#0110
7
ADC1_CH7
#0111
8
OPA1_O
#1000
STOVF
For All A/D SAMPLE MODULE Start Of Conversion Overrun Flags Check\nNote: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1.
25
1
read-write
0
None of SAMPLE MODULE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1
#0
1
Any one of SAMPLE MODULE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1
#1
SWTRG
EADC_SWTRG
A/D SAMPLE Module Software Start Register
0x48
write-only
n
0x0
0x0
EBI
EBI Register Map
EBI
0x0
0x0
0x24
registers
n
CTL
EBI_CTL
External Bus Interface General Control Register
0x0
read-write
n
0x0
0x0
CRYPTOEN
Encrypt/Decrypt Function Enable Bits (For 4 Individual Chip Select)\n
24
4
read-write
0
Encrypt/Decrypt function Disabled
0
1
Encrypt/Decrypt function Enabled
1
CSPOLINV
Reverse Chip Select\n
28
4
read-write
0
nCS (chip select active low)
0
1
CS (chip select active high)
1
MCLKDIV
External Output Clock Divider\nThe frequency of EBI output clock is controlled by MCLKDIV as below:\nNote: Default value of output clock is HCLK/1
8
3
read-write
0
HCLK/1
#000
1
HCLK/2
#001
2
HCLK/4
#010
3
HCLK/8.\nDefault
#011
4
HCLK/16
#100
5
HCLK/32
#101
KEY0
EBI_KEY0
External Bus Interface Crypto Key Word 0
0x14
read-write
n
0x0
0x0
KEY
Crypto Key Word 0 (key[31:0]).
0
32
read-write
KEY1
EBI_KEY1
External Bus Interface Crypto Key Word 1
0x18
read-write
n
0x0
0x0
KEY
Crypto Key Word 1 (key[63:32]).
0
32
read-write
KEY2
EBI_KEY2
External Bus Interface Crypto Key Word 2
0x1C
read-write
n
0x0
0x0
KEY
Crypto Key Word 2 (key[95:64]).
0
32
read-write
KEY3
EBI_KEY3
External Bus Interface Crypto Key Word 3
0x20
read-write
n
0x0
0x0
KEY
Crypto Key Word 3 (key[127:96]).
0
32
read-write
TCTL0
EBI_TCTL0
External Bus Interface Bank0 Timing Control Register
0x4
read-write
n
0x0
0x0
CSEN
EBI Bank0 Enable Bit\nThis bit is the functional enable bit for EBI.\n
28
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
DW16
EBI Bank0 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
29
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
R2R
Bank0 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[0] return to high if R2R is not zero.\n
24
4
read-write
0
reserved
0
R2W
Bank0 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[0] return to high if R2W is not zero.\n
16
4
read-write
0
reserved
0
SEPEN
EBI Bank0 Address/Data Bus Separating Enable Bit\n
30
1
read-write
0
Address/Data Bus Separating Disabled
#0
1
Address/Data Bus Separating Enabled
#1
TACC
EBI Bank0 Data Access Time\nTACC define data access time (tACC).\n
3
5
read-write
TAHD
EBI Bank0 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
8
3
read-write
TALE
Bank0 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
0
3
read-write
W2X
Bank0 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[0] return to high if W2X is not zero.\n
12
4
read-write
0
reserved
0
TCTL1
EBI_TCTL1
External Bus Interface Bank1 Timing Control Register
0x8
read-write
n
0x0
0x0
CSEN
EBI Bank1 Enable Bit\nThis bit is the functional enable bit for EBI.\n
28
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
DW16
EBI Bank1 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
29
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
R2R
Bank1 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[1] return to high if R2R is not zero.\n
24
4
read-write
0
reserved
0
R2W
Bank1 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[1] return to high if R2W is not zero.\n
16
4
read-write
0
reserved
0
SEPEN
EBI Bank1 Address/Data Bus Separating Enable Bit\n
30
1
read-write
0
Address/Data Bus Separating Disabled
#0
1
Address/Data Bus Separating Enabled
#1
TACC
EBI Bank1 Data Access Time\nTACC define data access time (tACC).\n
3
5
read-write
TAHD
EBI Bank1 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
8
3
read-write
TALE
Bank1 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
0
3
read-write
W2X
Bank1 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[1] return to high if W2X is not zero.\n
12
4
read-write
0
reserved
0
TCTL2
EBI_TCTL2
External Bus Interface Bank2 Timing Control Register
0xC
read-write
n
0x0
0x0
CSEN
EBI Bank2 Enable Bit\nThis bit is the functional enable bit for EBI.\n
28
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
DW16
EBI Bank2 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
29
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
R2R
Bank2 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[2] return to high if R2R is not 0.\n
24
4
read-write
0
Reserved
0
R2W
Bank2 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[2] return to high if R2W is not 0.\n
16
4
read-write
0
Reserved
0
SEPEN
EBI Bank2 Address/Data Bus Separating Enable Bit\n
30
1
read-write
0
Address/Data Bus Separating Disabled
#0
1
Address/Data Bus Separating Enabled
#1
TACC
EBI Bank2 Data Access Time\nTACC define data access time (tACC).\n
3
5
read-write
TAHD
EBI Bank2 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
8
3
read-write
TALE
Bank2 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
0
3
read-write
W2X
Bank2 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[2] return to high if W2X is not zero.\n
12
4
read-write
0
reserved
0
TCTL3
EBI_TCTL3
External Bus Interface Bank3 Timing Control Register
0x10
read-write
n
0x0
0x0
CSEN
EBI Bank3 Enable Bit\nThis bit is the functional enable bit for EBI.\n
28
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
DW16
EBI Bank3 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
29
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
R2R
Bank3 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[3] return to high if R2R is not zero.\n0 : reserved.
24
4
read-write
R2W
Bank3 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[3] return to high if R2W is not zero.\n0 : reserved.
16
4
read-write
SEPEN
EBI Bank3 Address/Data Bus Separating Enable Bit\n
30
1
read-write
0
Address/Data Bus Separating Disabled
#0
1
Address/Data Bus Separating Enabled
#1
TACC
EBI Bank3 Data Access Time\nTACC define data access time (tACC).\n
3
5
read-write
TAHD
EBI Bank3 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
8
3
read-write
TALE
Bank3 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
0
3
read-write
W2X
Bank3 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[3] return to high if W2X is not zero.\n0 : reserved.
12
4
read-write
ECAP0
ECAP Register Map
ECAP
0x0
0x0
0x20
registers
n
ECAP_CNT
ECAP_CNT
Input Capture Counter (24-bit Up Counter)
0x0
read-write
n
0x0
0x0
VAL
Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
0
24
read-write
ECAP_CNTCMP
ECAP_CNTCMP
Input Capture Counter Compare Register
0x10
read-write
n
0x0
0x0
VAL
Input Capture Counter Compare Register\n
0
24
read-write
ECAP_CTL0
ECAP_CTL0
Input Capture Control Register 0
0x14
read-write
n
0x0
0x0
CAPEN
Input Capture Timer/Counter Enable Bit\n
29
1
read-write
0
Input Capture function Disabled
#0
1
Input Capture function Enabled
#1
CAPEN0
Port Pin IC0 Input To Input Capture Unit Enable Bit\n
4
1
read-write
0
IC0 input to Input Capture Unit Disabled
#0
1
IC0 input to Input Capture Unit Enabled
#1
CAPEN1
Port Pin IC1 Input To Input Capture Unit Enable Bit\n
5
1
read-write
0
IC1 input to Input Capture Unit Disabled
#0
1
IC1 input to Input Capture Unit Enabled
#1
CAPEN2
Port Pin IC2 Input To Input Capture Unit Enable Bit\n
6
1
read-write
0
IC2 input to Input Capture Unit Disabled
#0
1
IC2 input to Input Capture Unit Enabled
#1
CAPIEN0
Input Capture Channel 0 Interrupt Enable Bit\n
16
1
read-write
0
The flag CAPF0 can trigger Input Capture interrupt Disabled
#0
1
The flag CAPF0 can trigger Input Capture interrupt Enabled
#1
CAPIEN1
Input Capture Channel 1 Interrupt Enable Bit\n
17
1
read-write
0
The flag CAPF1 can trigger Input Capture interrupt Disabled
#0
1
The flag CAPF1 can trigger Input Capture interrupt Enabled
#1
CAPIEN2
Input Capture Channel 2 Interrupt Enable Bit\n
18
1
read-write
0
The flag CAPF2 can trigger Input Capture interrupt Disabled
#0
1
The flag CAPF2 can trigger Input Capture interrupt Enabled
#1
CAPNF_DIS
Input Capture Noise Filter Disable Bit\n
3
1
read-write
0
Noise filter of Input Capture Enabled
#0
1
Noise filter of Input Capture Disabled
#1
CAPSEL0
CAP0 Input Source Selection\n
8
2
read-write
0
CAP0 input is from port pin IC0
#00
1
CAP0 input is from signal CPO0 (Analog comparator 0 output)
#01
2
CAP0 input is from signal CHA of QEI controller unit x
#10
3
CAP0 input is from signal OPDO0 (OP0 digital output)
#11
CAPSEL1
CAP1 Input Source Selection\n
10
2
read-write
0
CAP1 input is from port pin IC1
#00
1
CAP1 input is from signal CPO1 (Analog comparator 1 output)
#01
2
CAP1 input is from signal CHB of QEI controller unit x
#10
3
CAP1 input is from signal OPDO1 (OP1 digital output)
#11
CAPSEL2
CAP2 Input Source Selection\n
12
2
read-write
0
CAP2 input is from port pin IC2
#00
1
CAP2 input is from signal CPO2 (Analog comparator 2 output)
#01
2
CAP2 input is from signal CHX of QEI controller unit x
#10
3
CAP2 input is from signal ADCMPOx (ADC compare output x)
#11
CMPCLR
Input Capture Counter Cleared By Compare-Match Control\n
25
1
read-write
0
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled
#0
1
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled
#1
CMPEN
Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set. \n
28
1
read-write
0
The compare function Disabled
#0
1
The compare function Enabled
#1
CMPIEN
CMPF Trigger Input Capture Interrupt Enable Bit\n
21
1
read-write
0
The flag CMPF can trigger Input Capture interrupt Disabled
#0
1
The flag CMPF can trigger Input Capture interrupt Enabled
#1
CNTEN
Input Capture Counter Start\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n
24
1
read-write
0
ECAP_CNT stop counting
#0
1
ECAP_CNT starts up-counting
#1
CPTCLR
Input Capture Counter Cleared By Capture Events Control\nIf this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs. \n
26
1
read-write
0
Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled
#0
1
Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled
#1
NFDIS
Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n
0
2
read-write
0
CAP_CLK
#00
1
CAP_CLK/2
#01
2
CAP_CLK/4
#10
3
CAP_CLK/16
#11
OVIEN
OVF Trigger Input Capture Interrupt Enable Bit\n
20
1
read-write
0
The flag OVUNF can trigger Input Capture interrupt Disabled
#0
1
The flag OVUNF can trigger Input Capture interrupt Enabled
#1
RLDEN
Reload Function Enable Bit \nSetting this bit to enable the reload function. If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n
27
1
read-write
0
The reload function Disabled
#0
1
The reload function Enabled
#1
ECAP_CTL1
ECAP_CTL1
Input Capture Control Register 1
0x18
read-write
n
0x0
0x0
CLKSEL
Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n
12
3
read-write
0
CAP_CLK/1
#000
1
CAP_CLK/4
#001
2
CAP_CLK/16
#010
3
CAP_CLK/32
#011
4
CAP_CLK/64
#100
5
CAP_CLK/96
#101
6
CAP_CLK/112
#110
7
CAP_CLK/128
#111
EDGESEL0
Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
0
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
EDGESEL1
Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
2
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
EDGESEL2
Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only, or one of both edge changes. \n
4
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
RLDSEL
ECAP_CNT Reload Trigger Source Selection\n
8
3
read-write
0
CAPF0
#000
1
CAPF1
#001
2
CAPF2
#010
4
OVF
#100
SRCSEL
Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n
16
2
read-write
0
CAP_CLK (default)
#00
1
CAP0
#01
2
CAP1
#10
3
CAP2
#11
ECAP_HOLD0
ECAP_HOLD0
Input Capture Counter Hold Register 0
0x4
read-write
n
0x0
0x0
VAL
Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
0
24
read-write
ECAP_HOLD1
ECAP_HOLD1
Input Capture Counter Hold Register 1
0x8
read-write
n
0x0
0x0
ECAP_HOLD2
ECAP_HOLD2
Input Capture Counter Hold Register 2
0xC
read-write
n
0x0
0x0
ECAP_STATUS
ECAP_STATUS
Input Capture Status Register
0x1C
read-write
n
0x0
0x0
CAPF0
Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. \nNote: This bit is only cleared by writing 1 to it.
0
1
read-write
0
No valid edge change is detected at CAP0 input
#0
1
A valid edge change is detected at CAP0 input
#1
CAPF1
Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high. \nNote: This bit is only cleared by writing 1 to it.
1
1
read-write
0
No valid edge change is detected at CAP1 input
#0
1
A valid edge change is detected at CAP1 input
#1
CAPF2
Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high. \nNote: This bit is only cleared by writing 1 to it.
2
1
read-write
0
No valid edge change is detected at CAP2 input
#0
1
A valid edge change is detected at CAP2 input
#1
CMPF
Input Capture Compare-Match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it.
4
1
read-write
0
ECAP_CNT does not match with ECAP_CNTCMP value
#0
1
ECAP_CNT counts to the same as ECAP_CNTCMP value
#1
OVF
Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it.
5
1
read-write
0
No overflow occurs in ECAP_CNT
#0
1
ECAP_CNT overflows
#1
ECAP1
ECAP Register Map
ECAP
0x0
0x0
0x20
registers
n
ECAP_CNT
ECAP_CNT
Input Capture Counter (24-bit Up Counter)
0x0
read-write
n
0x0
0x0
VAL
Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
0
24
read-write
ECAP_CNTCMP
ECAP_CNTCMP
Input Capture Counter Compare Register
0x10
read-write
n
0x0
0x0
VAL
Input Capture Counter Compare Register\n
0
24
read-write
ECAP_CTL0
ECAP_CTL0
Input Capture Control Register 0
0x14
read-write
n
0x0
0x0
CAPEN
Input Capture Timer/Counter Enable Bit\n
29
1
read-write
0
Input Capture function Disabled
#0
1
Input Capture function Enabled
#1
CAPEN0
Port Pin IC0 Input To Input Capture Unit Enable Bit\n
4
1
read-write
0
IC0 input to Input Capture Unit Disabled
#0
1
IC0 input to Input Capture Unit Enabled
#1
CAPEN1
Port Pin IC1 Input To Input Capture Unit Enable Bit\n
5
1
read-write
0
IC1 input to Input Capture Unit Disabled
#0
1
IC1 input to Input Capture Unit Enabled
#1
CAPEN2
Port Pin IC2 Input To Input Capture Unit Enable Bit\n
6
1
read-write
0
IC2 input to Input Capture Unit Disabled
#0
1
IC2 input to Input Capture Unit Enabled
#1
CAPIEN0
Input Capture Channel 0 Interrupt Enable Bit\n
16
1
read-write
0
The flag CAPF0 can trigger Input Capture interrupt Disabled
#0
1
The flag CAPF0 can trigger Input Capture interrupt Enabled
#1
CAPIEN1
Input Capture Channel 1 Interrupt Enable Bit\n
17
1
read-write
0
The flag CAPF1 can trigger Input Capture interrupt Disabled
#0
1
The flag CAPF1 can trigger Input Capture interrupt Enabled
#1
CAPIEN2
Input Capture Channel 2 Interrupt Enable Bit\n
18
1
read-write
0
The flag CAPF2 can trigger Input Capture interrupt Disabled
#0
1
The flag CAPF2 can trigger Input Capture interrupt Enabled
#1
CAPNF_DIS
Input Capture Noise Filter Disable Bit\n
3
1
read-write
0
Noise filter of Input Capture Enabled
#0
1
Noise filter of Input Capture Disabled
#1
CAPSEL0
CAP0 Input Source Selection\n
8
2
read-write
0
CAP0 input is from port pin IC0
#00
1
CAP0 input is from signal CPO0 (Analog comparator 0 output)
#01
2
CAP0 input is from signal CHA of QEI controller unit x
#10
3
CAP0 input is from signal OPDO0 (OP0 digital output)
#11
CAPSEL1
CAP1 Input Source Selection\n
10
2
read-write
0
CAP1 input is from port pin IC1
#00
1
CAP1 input is from signal CPO1 (Analog comparator 1 output)
#01
2
CAP1 input is from signal CHB of QEI controller unit x
#10
3
CAP1 input is from signal OPDO1 (OP1 digital output)
#11
CAPSEL2
CAP2 Input Source Selection\n
12
2
read-write
0
CAP2 input is from port pin IC2
#00
1
CAP2 input is from signal CPO2 (Analog comparator 2 output)
#01
2
CAP2 input is from signal CHX of QEI controller unit x
#10
3
CAP2 input is from signal ADCMPOx (ADC compare output x)
#11
CMPCLR
Input Capture Counter Cleared By Compare-Match Control\n
25
1
read-write
0
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled
#0
1
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled
#1
CMPEN
Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set. \n
28
1
read-write
0
The compare function Disabled
#0
1
The compare function Enabled
#1
CMPIEN
CMPF Trigger Input Capture Interrupt Enable Bit\n
21
1
read-write
0
The flag CMPF can trigger Input Capture interrupt Disabled
#0
1
The flag CMPF can trigger Input Capture interrupt Enabled
#1
CNTEN
Input Capture Counter Start\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n
24
1
read-write
0
ECAP_CNT stop counting
#0
1
ECAP_CNT starts up-counting
#1
CPTCLR
Input Capture Counter Cleared By Capture Events Control\nIf this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs. \n
26
1
read-write
0
Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled
#0
1
Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled
#1
NFDIS
Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n
0
2
read-write
0
CAP_CLK
#00
1
CAP_CLK/2
#01
2
CAP_CLK/4
#10
3
CAP_CLK/16
#11
OVIEN
OVF Trigger Input Capture Interrupt Enable Bit\n
20
1
read-write
0
The flag OVUNF can trigger Input Capture interrupt Disabled
#0
1
The flag OVUNF can trigger Input Capture interrupt Enabled
#1
RLDEN
Reload Function Enable Bit \nSetting this bit to enable the reload function. If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n
27
1
read-write
0
The reload function Disabled
#0
1
The reload function Enabled
#1
ECAP_CTL1
ECAP_CTL1
Input Capture Control Register 1
0x18
read-write
n
0x0
0x0
CLKSEL
Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n
12
3
read-write
0
CAP_CLK/1
#000
1
CAP_CLK/4
#001
2
CAP_CLK/16
#010
3
CAP_CLK/32
#011
4
CAP_CLK/64
#100
5
CAP_CLK/96
#101
6
CAP_CLK/112
#110
7
CAP_CLK/128
#111
EDGESEL0
Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
0
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
EDGESEL1
Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
2
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
EDGESEL2
Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only, or one of both edge changes. \n
4
2
read-write
0
Detect rising edge
#00
1
Detect falling edge.\nDetect either rising or falling edge
#01
RLDSEL
ECAP_CNT Reload Trigger Source Selection\n
8
3
read-write
0
CAPF0
#000
1
CAPF1
#001
2
CAPF2
#010
4
OVF
#100
SRCSEL
Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n
16
2
read-write
0
CAP_CLK (default)
#00
1
CAP0
#01
2
CAP1
#10
3
CAP2
#11
ECAP_HOLD0
ECAP_HOLD0
Input Capture Counter Hold Register 0
0x4
read-write
n
0x0
0x0
VAL
Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
0
24
read-write
ECAP_HOLD1
ECAP_HOLD1
Input Capture Counter Hold Register 1
0x8
read-write
n
0x0
0x0
ECAP_HOLD2
ECAP_HOLD2
Input Capture Counter Hold Register 2
0xC
read-write
n
0x0
0x0
ECAP_STATUS
ECAP_STATUS
Input Capture Status Register
0x1C
read-write
n
0x0
0x0
CAPF0
Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. \nNote: This bit is only cleared by writing 1 to it.
0
1
read-write
0
No valid edge change is detected at CAP0 input
#0
1
A valid edge change is detected at CAP0 input
#1
CAPF1
Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high. \nNote: This bit is only cleared by writing 1 to it.
1
1
read-write
0
No valid edge change is detected at CAP1 input
#0
1
A valid edge change is detected at CAP1 input
#1
CAPF2
Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high. \nNote: This bit is only cleared by writing 1 to it.
2
1
read-write
0
No valid edge change is detected at CAP2 input
#0
1
A valid edge change is detected at CAP2 input
#1
CMPF
Input Capture Compare-Match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it.
4
1
read-write
0
ECAP_CNT does not match with ECAP_CNTCMP value
#0
1
ECAP_CNT counts to the same as ECAP_CNTCMP value
#1
OVF
Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it.
5
1
read-write
0
No overflow occurs in ECAP_CNT
#0
1
ECAP_CNT overflows
#1
EMAC
EMAC Register Map
EMAC
0x0
0x0
0xC0
registers
n
0x100
0x4
registers
n
0x110
0x20
registers
n
0xC8
0x14
registers
n
ALMSEC
EMAC_ALMSEC
Time Stamp Alarm Second Register
0x128
read-write
n
0x0
0x0
SEC
Time Stamp Counter Second Alarm\nTime stamp counter second part alarm value.\nThis value is only useful when ALMEN (EMAC_TSCTL[5]) high. If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
0
32
read-write
ALMSUBSEC
EMAC_ALMSUBSEC
Time Stamp Alarm Sub Second Register
0x12C
read-write
n
0x0
0x0
SUBSEC
Time Stamp Counter Sub-Second Alarm\nTime stamp counter sub-second part alarm value.\nThis value is only useful when ALMEN (EMAC_TSCTL[5]) high. If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
0
32
read-write
CAM0L
EMAC_CAM0L
CAM0 Least Significant Word Register
0xC
read-write
n
0x0
0x0
MACADDR0
MAC Address Byte 0
16
8
read-write
MACADDR1
MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.\nFor example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
24
8
read-write
CAM0M
EMAC_CAM0M
CAM0 Most Significant Word Register
0x8
read-write
n
0x0
0x0
MACADDR2
MAC Address Byte 2
0
8
read-write
MACADDR3
MAC Address Byte 3
8
8
read-write
MACADDR4
MAC Address Byte 4
16
8
read-write
MACADDR5
MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.\nFor example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
24
8
read-write
CAM10L
EMAC_CAM10L
CAM10 Least Significant Word Register
0x5C
read-write
n
0x0
0x0
CAM10M
EMAC_CAM10M
CAM10 Most Significant Word Register
0x58
read-write
n
0x0
0x0
CAM11L
EMAC_CAM11L
CAM11 Least Significant Word Register
0x64
read-write
n
0x0
0x0
CAM11M
EMAC_CAM11M
CAM11 Most Significant Word Register
0x60
read-write
n
0x0
0x0
CAM12L
EMAC_CAM12L
CAM12 Least Significant Word Register
0x6C
read-write
n
0x0
0x0
CAM12M
EMAC_CAM12M
CAM12 Most Significant Word Register
0x68
read-write
n
0x0
0x0
CAM13L
EMAC_CAM13L
CAM13 Least Significant Word Register
0x74
read-write
n
0x0
0x0
CAM13M
EMAC_CAM13M
CAM13 Most Significant Word Register
0x70
read-write
n
0x0
0x0
CAM14L
EMAC_CAM14L
CAM14 Least Significant Word Register
0x7C
read-write
n
0x0
0x0
CAM14M
EMAC_CAM14M
CAM14 Most Significant Word Register
0x78
read-write
n
0x0
0x0
CAM15LSB
EMAC_CAM15LSB
CAM15 Least Significant Word Register
0x84
read-write
n
0x0
0x0
OPERAND
Pause Parameter\nIn the PAUSE control frame, an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused. The unit of the OPERAND is a slot time, the 512 bits time.
24
8
read-write
CAM15MSB
EMAC_CAM15MSB
CAM15 Most Significant Word Register
0x80
read-write
n
0x0
0x0
LENGTH
LENGTH Field Of PAUSE Control Frame\nIn the PAUSE control frame, a LENGTH field defined and is 16 h8808.
16
16
read-write
OPCODE
OP Code Field Of PAUSE Control Frame\nIn the PAUSE control frame, an op code field defined and is 16 h0001.
0
16
read-write
CAM1L
EMAC_CAM1L
CAM1 Least Significant Word Register
0x14
read-write
n
0x0
0x0
CAM1M
EMAC_CAM1M
CAM1 Most Significant Word Register
0x10
read-write
n
0x0
0x0
CAM2L
EMAC_CAM2L
CAM2 Least Significant Word Register
0x1C
read-write
n
0x0
0x0
CAM2M
EMAC_CAM2M
CAM2 Most Significant Word Register
0x18
read-write
n
0x0
0x0
CAM3L
EMAC_CAM3L
CAM3 Least Significant Word Register
0x24
read-write
n
0x0
0x0
CAM3M
EMAC_CAM3M
CAM3 Most Significant Word Register
0x20
read-write
n
0x0
0x0
CAM4L
EMAC_CAM4L
CAM4 Least Significant Word Register
0x2C
read-write
n
0x0
0x0
CAM4M
EMAC_CAM4M
CAM4 Most Significant Word Register
0x28
read-write
n
0x0
0x0
CAM5L
EMAC_CAM5L
CAM5 Least Significant Word Register
0x34
read-write
n
0x0
0x0
CAM5M
EMAC_CAM5M
CAM5 Most Significant Word Register
0x30
read-write
n
0x0
0x0
CAM6L
EMAC_CAM6L
CAM6 Least Significant Word Register
0x3C
read-write
n
0x0
0x0
CAM6M
EMAC_CAM6M
CAM6 Most Significant Word Register
0x38
read-write
n
0x0
0x0
CAM7L
EMAC_CAM7L
CAM7 Least Significant Word Register
0x44
read-write
n
0x0
0x0
CAM7M
EMAC_CAM7M
CAM7 Most Significant Word Register
0x40
read-write
n
0x0
0x0
CAM8L
EMAC_CAM8L
CAM8 Least Significant Word Register
0x4C
read-write
n
0x0
0x0
CAM8M
EMAC_CAM8M
CAM8 Most Significant Word Register
0x48
read-write
n
0x0
0x0
CAM9L
EMAC_CAM9L
CAM9 Least Significant Word Register
0x54
read-write
n
0x0
0x0
CAM9M
EMAC_CAM9M
CAM9 Most Significant Word Register
0x50
read-write
n
0x0
0x0
CAMCTL
EMAC_CAMCTL
CAM Comparison Control Register
0x0
read-write
n
0x0
0x0
ABP
Accept Broadcast Packet\nThe ABP controls the broadcast packet reception. If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.\n
2
1
read-write
0
EMAC receives packet depends on the CAM comparison result
#0
1
EMAC receives all broadcast packets
#1
AMP
Accept Multicast Packet\nThe AMP controls the multicast packet reception. If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.\n
1
1
read-write
0
EMAC receives packet depends on the CAM comparison result
#0
1
EMAC receives all multicast packets
#1
AUP
Accept Unicast Packet\nThe AUP controls the unicast packet reception. If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.\n
0
1
read-write
0
EMAC receives packet depends on the CAM comparison result
#0
1
EMAC receives all unicast packets
#1
CMPEN
CAM Compare Enable\nThe CMPEN controls the enable of CAM comparison function for destination MAC address recognition. If software wants to receive a packet with specific destination MAC address, configures the MAC address into CAM 12~0, then enables that CAM entry and set CMPEN to 1.\n
4
1
read-write
0
CAM comparison function for destination MAC address recognition disabled
#0
1
CAM comparison function for destination MAC address recognition enabled
#1
COMPEN
Complement CAM Comparison Enable\nThe COMPEN controls the complement of the CAM comparison result. If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped. And the incoming packet with destination MAC address does not configured in any CAM entry will be received.\n
3
1
read-write
0
The CAM comparison result does not complement
#0
1
The CAM comparison result complemented
#1
CRXBSA
EMAC_CRXBSA
Current Receive Buffer Start Address Register
0xD8
read-only
n
0x0
0x0
CRXBSA
Current Receive Buffer Start Address\nThe CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently. The CRXBSA is read only and write to this register has no effect.
0
32
read-only
CRXDSA
EMAC_CRXDSA
Current Receive Descriptor Start Address Register
0xD4
read-only
n
0x0
0x0
CRXDSA
Current Receive Descriptor Start Address\nThe CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently. The CRXDSA is read only and write to this register has no effect.
0
32
read-only
CTL
EMAC_CTL
MAC Control Register
0x90
-1
read-write
n
0x0
0x0
ACP
Accept Control Packet\nThe ACP controls the control frame reception. If the ACP is set to high, the EMAC will accept the control frame. Otherwise, the control frame will be dropped. It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.\n
3
1
read-write
0
Ethernet MAC controller dropped the control frame
#0
1
Ethernet MAC controller received the control frame
#1
AEP
Accept CRC Error Packet\nThe AEP controls the EMAC accepts or drops the CRC error packet. If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.\n
4
1
read-write
0
Ethernet MAC controller dropped the CRC error packet
#0
1
Ethernet MAC controller received the CRC error packet
#1
ALP
Accept Long Packet\nThe ALP controls the long packet, which packet length is greater than 1518 bytes, reception. If the ALP is set to high, the EMAC will accept the long packet.\nOtherwise, the long packet will be dropped.\n
1
1
read-write
0
Ethernet MAC controller dropped the long packet
#0
1
Ethernet MAC controller received the long packet
#1
ARP
Accept Runt Packet\nThe ARP controls the runt packet, which length is less than 64 bytes, reception. If the ARP is set to high, the EMAC will accept the runt packet.\nOtherwise, the runt packet will be dropped.\n
2
1
read-write
0
Ethernet MAC controller dropped the runt packet
#0
1
Ethernet MAC controller received the runt packet
#1
FUDUP
Full Duplex Mode Selection\nThe FUDUP controls that if EMAC is operating on full or half duplex mode.\n
18
1
read-write
0
EMAC operates in half duplex mode
#0
1
EMAC operates in full duplex mode
#1
NODEF
No Deferral\nThe NODEF controls the enable of deferral exceed counter. If NODEF is set to high, the deferral exceed counter is disabled. The NODEF is only useful while EMAC is operating on half duplex mode.\n
9
1
read-write
0
The deferral exceed counter Enabled
#0
1
The deferral exceed counter Disabled
#1
OPMODE
Operation Mode Selection\nThe OPMODE defines that if the EMAC is operating on 10M or 100M bps mode. The RST (EMAC_CTL[24]) would not affect OPMODE value.\n
20
1
read-write
0
EMAC operates in 10Mbps mode
#0
1
EMAC operates in 100Mbps mode
#1
RMIIEN
RMII Mode Enable\nThis bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface. The RST (EMAC_CTL[24]) would not affect RMIIEN value.\n
22
1
read-write
0
Ethernet MAC controller MII mode Enabled
#0
1
Ethernet MAC controller RMII mode Enabled
#1
RMIIRXCTL
RMII RX Control\nThe RMIIRXCTL control the receive data sample in RMII mode. It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.\n
19
1
read-write
0
RMII RX control disabled
#0
1
RMII RX control enabled
#1
RST
Software Reset\nThe RST implements a reset function to make the EMAC return default state. The RST is a self-clear bit. This means after the software reset finished, the RST will be cleared automatically. Enable RST can also reset all control and status registers, exclusive of the control bits RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).\nThe EMAC re-initial is necessary after the software reset completed.\n
24
1
read-write
0
Software reset completed
#0
1
Software reset Enabled
#1
RXON
Frame Reception ON\nThe RXON controls the normal packet reception of EMAC. If the RXON is set to high, the EMAC starts the packet reception process, including the RX descriptor fetching, packet reception and RX descriptor modification.\nIt is necessary to finish EMAC initial sequence before enable RXON. Otherwise, the EMAC operation is undefined.\nIf the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet reception process after the current packet reception finished.\n
0
1
read-write
0
Packet reception process stopped
#0
1
Packet reception process started
#1
SDPZ
Send PAUSE Frame\nThe SDPZ controls the PAUSE control frame transmission.\nIf S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set. Then, set SDPZ to 1 enables the PAUSE control frame transmission.\nThe SDPZ is a self-clear bit. This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.\nIt is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.\n
16
1
read-write
0
PAUSE control frame transmission completed
#0
1
PAUSE control frame transmission Enabled
#1
SQECHKEN
SQE Checking Enable\nThe SQECHKEN controls the enable of SQE checking. The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode. In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100M bps or full duplex mode.\n
17
1
read-write
0
SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode
#0
1
SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode
#1
STRIPCRC
Strip CRC Checksum\nThe STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum. If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.\n
5
1
read-write
0
The 4 bytes CRC checksum is included in packet length calculation
#0
1
The 4 bytes CRC checksum is excluded in packet length calculation
#1
TXON
Frame Transmission ON\nThe TXON controls the normal packet transmission of EMAC. If the TXON is set to high, the EMAC starts the packet transmission process, including the TX descriptor fetching, packet transmission and TX descriptor modification.\nIt is must to finish EMAC initial sequence before enable TXON. Otherwise, the EMAC operation is undefined.\nIf the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet transmission process after the current packet transmission finished.\n
8
1
read-write
0
Packet transmission process stopped
#0
1
Packet transmission process started
#1
WOLEN
Wake On LAN Enable\nThe WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode.\nIf incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller would generate a wakeup event to wake system up from Power-down mode.\n
6
1
read-write
0
Wake-up by Magic Packet function Disabled
#0
1
Wake-up by Magic Packet function Enabled
#1
CTXBSA
EMAC_CTXBSA
Current Transmit Buffer Start Address Register
0xD0
read-only
n
0x0
0x0
CTXBSA
Current Transmit Buffer Start Address\nThe CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently. The CTXBSA is read only and write to this register has no effect.
0
32
read-only
CTXDSA
EMAC_CTXDSA
Current Transmit Descriptor Start Address Register
0xCC
read-only
n
0x0
0x0
CTXDSA
Current Transmit Descriptor Start Address\nThe CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently. The CTXDSA is read only and write to this register has no effect.
0
32
read-only
ECAM_CAMEN
ECAM_CAMEN
CAM Enable Register
0x4
read-write
n
0x0
0x0
CAMxEN
CAM Entry X Enable Bit\nThe CAMxEN controls the validation of CAM entry x.\nThe CAM entry 13, 14 and 15 are for PAUSE control frame transmission. If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first.\n
0
1
read-write
0
CAM entry x Disabled
#0
1
CAM entry x Enabled
#1
FIFOCTL
EMAC_FIFOCTL
FIFO Threshold Control Register
0x9C
-1
read-write
n
0x0
0x0
BURSTLEN
DMA Burst Length\nThis defines the burst length of AHB bus cycle while EMAC accesses system memory.\n
20
2
read-write
0
16 words
#00
1
16 words
#01
2
8 words
#10
3
4 words
#11
RXFIFOTH
RXFIFO Low Threshold\nThe RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory. The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold. The low threshold is the half of high threshold always. During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to transfer frame data from RXFIFO to system memory. If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame data to system memory.\n
0
2
read-write
0
Depend on the burst length setting. If the burst length is 8 words, high threshold is 8 words, too
#00
1
RXFIFO high threshold is 64B and low threshold is 32B
#01
2
RXFIFO high threshold is 128B and low threshold is 64B
#10
3
RXFIFO high threshold is 192B and low threshold is 96B
#11
TXFIFOTH
TXFIFO Low Threshold\nThe TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO. The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold. The high threshold is the twice of low threshold always. During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO. If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data from system memory to TXFIFO.\nThe TXFIFOTH also defines when the TXMAC starts to transmit frame out to network. The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold during the transmission of the frame. If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO.\n
8
2
read-write
0
Undefined
#00
1
TXFIFO low threshold is 64B and high threshold is 128B
#01
2
TXFIFO low threshold is 80B and high threshold is 160B
#10
3
TXFIFO low threshold is 96B and high threshold is 192B
#11
FRSTS
EMAC_FRSTS
DMA Receive Frame Status Register
0xC8
read-write
n
0x0
0x0
RXFLT
Receive Frame LENGTH\nThe RXFLT keeps the LENGTH field of each incoming Ethernet packet. If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. And, the content of LENGTH field will be stored in RXFLT.
0
16
read-write
GENSTS
EMAC_GENSTS
MAC General Status Register
0xB4
read-write
n
0x0
0x0
CFR
Control Frame Received\nThe CFRIF high indicates EMAC receives a flow control frame. The CFRIF only available while EMAC is operating on full duplex mode.\n
0
1
read-write
0
The EMAC does not receive the flow control frame
#0
1
The EMAC receives a flow control frame
#1
COLCNT
Collision Count\nThe COLCNT indicates that how many collisions occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 4 h0 and bit TXABTIF will be set to 1.
4
4
read-write
DEF
Deferred Transmission\nThe DEF high indicates the packet transmission has deferred once. The DEF is only available while EMAC is operating on half-duplex mode.\n
8
1
read-write
0
Packet transmission does not defer
#0
1
Packet transmission has deferred once
#1
RPSTS
Remote Pause Status\nThe RPSTS indicates that remote pause counter down counting actives.\nAfter Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause counter down counting. When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet transmission until the down counting done.\n
12
1
read-write
0
Remote pause counter down counting done
#0
1
Remote pause counter down counting actives
#1
RXFFULL
RXFIFO Full\nThe RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped.\n
2
1
read-write
0
The RXFIFO is not full
#0
1
The RXFIFO is full and the following incoming packet will be dropped
#1
RXHALT
Receive Halted\nThe RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W.\n
1
1
read-write
0
Next normal packet reception process will go on
#0
1
Next normal packet reception process will be halted
#1
SQE
Signal Quality Error\nThe SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC is operating on 10Mbps half-duplex mode.\n
10
1
read-write
0
No SQE error found at end of packet transmission
#0
1
SQE error found at end of packet transmission
#1
TXHALT
Transmission Halted\nThe TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W.\n
11
1
read-write
0
Next normal packet transmission process will go on
#0
1
Next normal packet transmission process will be halted
#1
TXPAUSED
Transmission Paused\nThe TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame.\n
9
1
read-write
0
Next normal packet transmission process will go on
#0
1
Next normal packet transmission process will be paused
#1
INTEN
EMAC_INTEN
MAC Interrupt Enable Register
0xAC
read-write
n
0x0
0x0
ALIEIEN
Alignment Error Interrupt Enable Bit\nThe ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation. If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the ALIEIF (EMAC_INTSTS[5]) is set.\n
5
1
read-write
0
ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled
#0
1
ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled
#1
CFRIEN
Control Frame Receive Interrupt Enable Bit\nThe CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation. If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CFRIF (EMAC_INTSTS[14]) register is set.\n
14
1
read-write
0
CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled
#0
1
CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled
#1
CRCEIEN
CRC Error Interrupt Enable Bit\nThe CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation. If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CRCEIF (EMAC_INTSTS[1]) is set.\n
1
1
read-write
0
CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled
#0
1
CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled
#1
DENIEN
DMA Early Notification Interrupt Enable Bit\nThe DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation. If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the DENIF (EMAC_INTSTS[9]) is set.\n
9
1
read-write
0
TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled
#0
1
TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled
#1
EXDEFIEN
Defer Exceed Interrupt Enable Bit\nThe EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation. If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the EXDEFIF (EMAC_INTSTS[19]) is set.\n
19
1
read-write
0
EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled
#0
1
EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled
#1
LCIEN
Late Collision Interrupt Enable Bit\nThe LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation. If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the LCIF (EMAC_INTSTS[22]) is set.\n
22
1
read-write
0
LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled
#0
1
LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled
#1
LPIEN
Long Packet Interrupt Enable\nThe LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation. If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF (EMAC_INTSTS[3]) is set.\n
3
1
read-write
0
LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled
#0
1
LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled
#1
MFLEIEN
Maximum Frame Length Exceed Interrupt Enable\nThe MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation. If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set.\n
8
1
read-write
0
MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled
#0
1
MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled
#1
MPCOVIEN
Miss Packet Counter Overrun Interrupt Enable\nThe MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation. If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MPCOVIF (EMAC_INTSTS[7]) is set.\n
7
1
read-write
0
MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled
#0
1
MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled
#1
NCSIEN
No Carrier Sense Interrupt Enable Bit\nThe NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation. If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the NCSIF (EMAC_INTSTS[20]) is set.\n
20
1
read-write
0
NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled
#0
1
NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled
#1
RDUIEN
Receive Descriptor Unavailable Interrupt Enable Bit\nThe RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation. If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RDUIF (EMAC_MIOSTA[10]) register is set.\n
10
1
read-write
0
RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled
#0
1
RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled
#1
RPIEN
Runt Packet Interrupt Enable Bit\nThe RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation. If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RPIF (EMAC_INTSTS[6]) is set.\n
6
1
read-write
0
RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled
#0
1
RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled
#1
RXBEIEN
Receive Bus Error Interrupt Enable Bit\nThe RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation. If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXBEIF (EMAC_INTSTS[11]) is set.\n
11
1
read-write
0
RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled
#0
1
RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled
#1
RXGDIEN
Receive Good Interrupt Enable Bit\nThe RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation. If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXGDIF (EMAC_INTSTS[4]) is set.\n
4
1
read-write
0
RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled
#0
1
RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled
#1
RXIEN
Receive Interrupt Enable Bit\nThe RXIEN controls the RX interrupt generation.\nIf RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU. If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] is set and the corresponding bit of EMAC_INTEN is enabled. In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled. And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.\n
0
1
read-write
0
RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled
#0
1
RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled
#1
RXOVIEN
Receive FIFO Overflow Interrupt Enable Bit\nThe RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation. If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set.\n
2
1
read-write
0
RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled
#0
1
RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled
#1
TDUIEN
Transmit Descriptor Unavailable Interrupt Enable Bit\nThe TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation. If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TDUIF (EMAC_INTSTS[23]) is set.\n
23
1
read-write
0
TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled
#0
1
TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled
#1
TSALMIEN
Time Stamp Alarm Interrupt Enable Bit\nThe TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation. If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the EMAC generates the TX interrupt to CPU. If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the TXTSALMIF (EMAC_INTEN[28]) is set.\n
28
1
read-write
0
TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled
#0
1
TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled
#1
TXABTIEN
Transmit Abort Interrupt Enable Bit\nThe TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation. If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXABTIF (EMAC_INTSTS[21]) is set.\n
21
1
read-write
0
TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled
#0
1
TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled
#1
TXBEIEN
Transmit Bus Error Interrupt Enable Bit\nThe TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation. If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXBEIF (EMAC_INTSTS[24]) is set.\n
24
1
read-write
0
TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled
#0
1
TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled
#1
TXCPIEN
Transmit Completion Interrupt Enable Bit\nThe TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation. If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXCPIF (EMAC_INTSTS[18]) is set.\n
18
1
read-write
0
TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled
#0
1
TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled
#1
TXIEN
Transmit Interrupt Enable Bit\nThe TXIEN controls the TX interrupt generation.\nIf TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU. If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled. In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled. And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.\n
16
1
read-write
0
TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled
#0
1
TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled
#1
TXUDIEN
Transmit FIFO Underflow Interrupt Enable Bit\nThe TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation. If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXUDIF (EMAC_INTSTS[17]) is set.\n
17
1
read-write
0
TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled
#0
1
TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled
#1
WOLIEN
Wake On LAN Interrupt Enable\nThe WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation. If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the WOLIF (EMAC_INTSTS[15]) is set.\n
15
1
read-write
0
WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled
#0
1
WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled
#1
INTSTS
EMAC_INTSTS
MAC Interrupt Status Register
0xB0
read-write
n
0x0
0x0
ALIEIF
Alignment Error Interrupt\nThe ALIEIF high indicates the length of the incoming frame is not a multiple of byte. If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high. Write 1 to this bit clears the ALIEIF status.\n
5
1
read-write
0
The frame length is a multiple of byte
#0
1
The frame length is not a multiple of byte
#1
CFRIF
Control Frame Receive Interrupt\nThe CFRIF high indicates EMAC receives a flow control frame. The CFRIF only available while EMAC is operating on full duplex mode.\nIf the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high. Write 1 to this bit clears the CFRIF status.\n
14
1
read-write
0
The EMAC does not receive the flow control frame
#0
1
The EMAC receives a flow control frame
#1
CRCEIF
CRC Error Interrupt\nThe CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped. If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and CRCEIF will not be set.\nIf the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high. Write 1 to this bit clears the CRCEIF status.\n
1
1
read-write
0
The frame does not incur CRC error
#0
1
The frame incurred CRC error
#1
DENIF
DMA Early Notification Interrupt\nThe DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.\nIf the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high. Write 1 to this bit clears the DENIF status.\n
9
1
read-write
0
The LENGTH field of incoming packet has not received yet
#0
1
The LENGTH field of incoming packet has received
#1
EXDEFIF
Defer Exceed Interrupt\nThe EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC is operating on half-duplex mode.\nIf the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high. Write 1 to this bit clears the EXDEFIF status.\n
19
1
read-write
0
Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps)
#0
1
Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps)
#1
LCIF
Late Collision Interrupt\nThe LCIF high indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has been transmitted out to the network, the collision still occurred. The late collision check will only be done while EMAC is operating on half-duplex mode. If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. Write 1 to this bit clears the LCIF status.\n
22
1
read-write
0
No collision occurred in the outside of 64 bytes collision window
#0
1
Collision occurred in the outside of 64 bytes collision window
#1
LPIF
Long Packet Interrupt Flag\nThe LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.\nIf the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high. Write 1 to this bit clears the LPIF status.\n
3
1
read-write
0
The incoming frame is not a long frame or S/W wants to receive a long frame
#0
1
The incoming frame is a long frame and dropped
#1
MFLEIF
Maximum Frame Length Exceed Interrupt Flag\nThe MFLEIF high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped. If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high. Write 1 to this bit clears the MFLEIF status.\n
8
1
read-write
0
The length of the incoming packet does not exceed the length limitation configured in DMARFC
#0
1
The length of the incoming packet has exceeded the length limitation configured in DMARFC
#1
MPCOVIF
Missed Packet Counter Overrun Interrupt Flag\nThe MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow. If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high. Write 1 to this bit clears the MPCOVIF status.\n
7
1
read-write
0
The MPCNT has not rolled over yet
#0
1
The MPCNT has rolled over yet
#1
NCSIF
No Carrier Sense Interrupt\nThe NCSIF high indicates the MII I/F signal CRS does not active at the start of or during the packet transmission. The NCSIF is only available while EMAC is operating on half-duplex mode. If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. Write 1 to this bit clears the NCSIF status.\n
20
1
read-write
0
CRS signal actives correctly
#0
1
CRS signal does not active at the start of or during the packet transmission
#1
RDUIF
Receive Descriptor Unavailable Interrupt\nThe RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state. Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.\nIf the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high. Write 1 to this bit clears the RDUIF status.\n
10
1
read-write
0
RX descriptor is available
#0
1
RX descriptor is unavailable
#1
RPIF
Runt Packet Interrupt\nThe RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped. If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.\nIf the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high. Write 1 to this bit clears the RPIF status.\n
6
1
read-write
0
The incoming frame is not a short frame or S/W wants to receive a short frame
#0
1
The incoming frame is a short frame and dropped
#1
RXBEIF
Receive Bus Error Interrupt\nThe RXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through RXDMA during packet reception process. Reset EMAC is recommended while RXBEIF status is high.\nIf the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high. Write 1 to this bit clears the RXBEIF status.\n
11
1
read-write
0
No ERROR response is received
#0
1
ERROR response is received
#1
RXGDIF
Receive Good Interrupt\nThe RXGDIF high indicates the frame reception has completed.\nIf the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high. Write 1 to this bit clears the RXGDIF status.\n
4
1
read-write
0
The frame reception has not complete yet
#0
1
The frame reception has completed
#1
RXIF
Receive Interrupt\nThe RXIF indicates the RX interrupt status.\nIf RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates the EMAC generates RX interrupt to CPU. If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.\nThe RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]. In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in EMAC_INTEN[15:1] is also enabled, the RXIF will be high.\nBecause the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.\n
0
1
read-write
0
No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled
#0
1
At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in EMAC_INTEN[15:1] is enabled, too
#1
RXOVIF
Receive FIFO Overflow Interrupt\nThe RXOVIF high indicates the RXFIFO overflow occurred during packet reception. While the RXFIFO overflow occurred, the EMAC drops the current receiving packer. If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, the RXFIFOTH of FFTCR register, to higher level.\nIf the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high. Write 1 to this bit clears the RXOVIF status.\n
2
1
read-write
0
No RXFIFO overflow occurred during packet reception
#0
1
RXFIFO overflow occurred during packet reception
#1
TDUIF
Transmit Descriptor Unavailable Interrupt\nThe TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state. Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.\nIf the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. Write 1 to this bit clears the TDUIF status.\n
23
1
read-write
0
TX descriptor is available
#0
1
TX descriptor is unavailable
#1
TSALMIF
Time Stamp Alarm Interrupt\nThe TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and EMAC_TSSUBSEC register value equals to register EMAC_TSMLSR.\nIf TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. Write 1 to this bit clears the TSALMIF status.\n
28
1
read-write
0
EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC
#0
1
EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC
#1
TXABTIF
Transmit Abort Interrupt\nThe TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMAC is operating on half-duplex mode.\nIf the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXABTIF status.\n
21
1
read-write
0
Packet does not incur 16 consecutive collisions during transmission
#0
1
Packet incurred 16 consecutive collisions during transmission
#1
TXBEIF
Transmit Bus Error Interrupt\nThe TXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through TXDMA during packet transmission process. Reset EMAC is recommended while TXBEIF status is high.\nIf the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXBEIF status.\n
24
1
read-write
0
No ERROR response is received
#0
1
ERROR response is received
#1
TXCPIF
Transmit Completion Interrupt\nThe TXCPIF indicates the packet transmission has completed correctly.\nIf the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXCPIF status.\n
18
1
read-write
0
The packet transmission not completed
#0
1
The packet transmission has completed
#1
TXIF
Transmit Interrupt\nThe TXIF indicates the TX interrupt status.\nIf TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates the EMAC generates TX interrupt to CPU. If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.\nThe TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]. In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit in EMAC_INTEN[28:17] is also enabled, the TXIF will be high. Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.\n
16
1
read-write
0
No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled
#0
1
At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit in EMAC_INTEN[28:17] is enabled, too
#1
TXUDIF
Transmit FIFO Underflow Interrupt\nThe TXUDIF high indicates the TXFIFO underflow occurred during packet transmission. While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention. If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXFIFOTH of FFTCR register, to higher level.\nIf the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXUDIF status.\n
17
1
read-write
0
No TXFIFO underflow occurred during packet transmission
#0
1
TXFIFO underflow occurred during packet transmission
#1
WOLIF
Wake On LAN Interrupt Flag\nThe WOLIF high indicates EMAC receives a Magic Packet. The CFRIF only available while system is in power down mode and WOLEN is set high.\nIf the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high. Write 1 to this bit clears the WOLIF status.\n
15
1
read-write
0
The EMAC does not receive the Magic Packet
#0
1
The EMAC receives a Magic Packet
#1
MIIMCTL
EMAC_MIIMCTL
MII Management Control and Address Register
0x98
-1
read-write
n
0x0
0x0
BUSY
Busy Bit\nThe BUSY controls the enable of the MII management frame generation. If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates the MII management frame to external PHY through MII Management I/F. The BUSY is a self-clear bit. This means the BUSY will be cleared automatically after the MII management command finished.\n
17
1
read-write
0
MII management command generation finished
#0
1
MII management command generation Enabled
#1
MDCON
MDC Clock ON\nThe MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.\n
19
1
read-write
0
MDC clock off
#0
1
MDC clock on
#1
PHYADDR
PHY Address\nThe PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
8
5
read-write
PHYREG
PHY Register Address\nThe PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command.
0
5
read-write
PREAMSP
Preamble Suppress\nThe PREAMSP controls the preamble field generation of MII management frame. If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.\n
18
1
read-write
0
Preamble field generation of MII management frame not skipped
#0
1
Preamble field generation of MII management frame skipped
#1
WRITE
Write Command\nThe Write defines the MII management command is a read or write.\n
16
1
read-write
0
MII management command is a read command
#0
1
MII management command is a write command
#1
MIIMDAT
EMAC_MIIMDAT
MII Management Data Register
0x94
read-write
n
0x0
0x0
DATA
MII Management Data\nThe DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command.
0
16
read-write
MPCNT
EMAC_MPCNT
Missed Packet Count Register
0xB8
-1
read-write
n
0x0
0x0
MPCNT
Miss Packet Count\nThe MPCNT indicates the number of packets that were dropped due to various types of receive errors. The following type of receiving error makes missed packet counter increase:\nIncoming packet is incurred RXFIFO overflow.\nIncoming packet is dropped due to RXON is disabled.\nIncoming packet is incurred CRC error.
0
16
read-write
MRFL
EMAC_MRFL
Maximum Receive Frame Control Register
0xA8
-1
read-write
n
0x0
0x0
MRFL
Maximum Receive Frame Length\nThe MRFL defines the maximum frame length for received frame. If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.\nIt is recommended that only use MRFL to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes.
0
16
read-write
RPCNT
EMAC_RPCNT
MAC Receive Pause Count Register
0xBC
read-only
n
0x0
0x0
RPCNT
MAC Receive Pause Count\nThe RPCNT keeps the OPERAND field of the PAUSE control frame. It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
0
16
read-only
RXDSA
EMAC_RXDSA
Receive Descriptor Link List Start Address Register
0x8C
-1
read-write
n
0x0
0x0
RXDSA
Receive Descriptor Link-List Start Address\nThe RXDSA keeps the start address of receive descriptor link-list. If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current receive descriptor start address register (EMAC_CRXDSA). The RXDSA does not be updated by EMAC. During the operation, EMAC will ignore the bits [1:0] of RXDSA. This means that RX descriptors must locate at word boundary memory address.
0
32
read-write
RXST
EMAC_RXST
Receive Start Demand Register
0xA4
write-only
n
0x0
0x0
RXST
Receive Start Demand\nIf the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted. After the S/W has prepared the new RX descriptor for frame reception, it must issue a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.\nThe EMAC_RXST is a write only register and read from this register is undefined.\nThe write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
0
32
write-only
TSADDEND
EMAC_TSADDEND
Time Stamp Addend Register
0x11C
read-write
n
0x0
0x0
ADDEND
Time Stamp Counter Addend\nThis register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.\nIf TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator with this 32-bit value in each HCLK. Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit value kept in register EMAC_TSINC.
0
32
read-write
TSCTL
EMAC_TSCTL
Time Stamp Control Register
0x100
read-write
n
0x0
0x0
TSALMEN
Time Stamp Alarm Enable Bit\nSet this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.\n
5
1
read-write
0
Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC
#0
1
Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC
#1
TSEN
Time Stamp Function Enable Bit\nThis bit controls if the IEEE 1588 PTP time stamp function is enabled or not.\nSet this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function.\n
0
1
read-write
0
I EEE 1588 PTP time stamp function Disabled
#0
1
IEEE 1588 PTP time stamp function Enabled
#1
TSIEN
Time Stamp Counter Initialization Enable Bit\nSet this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter.\nAfter the load operation finished, Ethernet MAC controller clear this bit to low automatically.\n
1
1
read-write
0
Time stamp counter initialization done
#0
1
Time stamp counter initialization Enabled
#1
TSMODE
Time Stamp Fine Update Enable Bit\nThis bit chooses the time stamp counter update mode.\n
2
1
read-write
0
Time stamp counter is in coarse update mode
#0
1
Time stamp counter is in fine update mode
#1
TSUPDATE
Time Stamp Counter Time Update Enable Bit\nSet this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter.\nAfter the add operation finished, Ethernet MAC controller clear this bit to low automatically.\n
3
1
read-write
0
No action
#0
1
EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC
#1
TSINC
EMAC_TSINC
Time Stamp Increment Register
0x118
read-write
n
0x0
0x0
CNTINC
Time Stamp Counter Increment\nTime stamp counter increment value.\nIf TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value.
0
8
read-write
TSSEC
EMAC_TSSEC
Time Stamp Counter Second Register
0x110
read-only
n
0x0
0x0
SEC
Time Stamp Counter Second\nThis register reflects the bit [63:32] value of 64-bit reference timing counter. This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
0
32
read-only
TSSUBSEC
EMAC_TSSUBSEC
Time Stamp Counter Sub Second Register
0x114
read-only
n
0x0
0x0
SUBSEC
Time Stamp Counter Sub-Second\nThis register reflects the bit [31:0] value of 64-bit reference timing counter. This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
0
32
read-only
TXDSA
EMAC_TXDSA
Transmit Descriptor Link List Start Address Register
0x88
-1
read-write
n
0x0
0x0
TXDSA
Transmit Descriptor Link-List Start Address\nThe TXDSA keeps the start address of transmit descriptor link-list. If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the current transmit descriptor start address register (EMAC_CTXDSA). The TXDSA does not be updated by EMAC. During the operation, EMAC will ignore the bits [1:0] of TXDSA. This means that TX descriptors must locate at word boundary memory address.
0
32
read-write
TXST
EMAC_TXST
Transmit Start Demand Register
0xA0
write-only
n
0x0
0x0
TXST
Transmit Start Demand\nIf the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted. After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.\nThe EMAC_TXST is a write only register and read from this register is undefined.\nThe write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
0
32
write-only
UPDSEC
EMAC_UPDSEC
Time Stamp Update Second Register
0x120
read-write
n
0x0
0x0
SEC
Time Stamp Counter Second Update\nWhen TSIEN (EMAC_TSCTL[1]) is high. EMAC loads this 32-bit value to EMAC_TSSEC directly. When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
0
32
read-write
UPDSUBSEC
EMAC_UPDSUBSEC
Time Stamp Update Sub Second Register
0x124
read-write
n
0x0
0x0
SUBSEC
Time Stamp Counter Sub-Second Update\nWhen TSIEN (EMAC_TSCTL[1]) is high. EMAC loads this 32-bit value to EMAC_TSSUBSEC directly. When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
0
32
read-write
EPWM0
EPWM Register Map
EPWM
0x0
0x0
0x48
registers
n
EPWM_ASYMCMP0
EPWM_ASYMCMP0
Asymmetric EPWM_CMPDAT0 Duty Register
0x20
read-write
n
0x0
0x0
CMP
Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle.
0
16
read-write
EPWM_ASYMCMP2
EPWM_ASYMCMP2
Asymmetric EPWM_CMPDAT2 Duty Register
0x24
read-write
n
0x0
0x0
EPWM_ASYMCMP4
EPWM_ASYMCMP4
Asymmetric EPWM_CMPDAT4 Duty Register
0x28
read-write
n
0x0
0x0
EPWM_ASYMCTL
EPWM_ASYMCTL
Asymmetric PWM Control Register
0x38
read-write
n
0x0
0x0
ASYMEN
Asymmetric PWM Enable Bit\nNote: This control bit is only valid when PWM module is set in Centre-aligned mode.
0
1
read-write
0
Asymmetric PWM function Disabled
#0
1
Asymmetric PWM function Enabled
#1
ASYMMODE0
Asymmetric PWMx_CH0 Reload Mode Setting\n
8
2
read-write
0
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#00
1
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#01
2
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#10
3
Reserved
#11
ASYMMODE2
Asymmetric PWMx_CH2 Reload Mode Setting\n
16
2
read-write
0
1. PWM compare register 2 is reload CMP (EPWM_CMPDAT2[15:0]) at PWM cycle start
#00
1
1. PWM compare register 2 is reload CMP (EPWM_CMPDAT2[15:0]) at PWM cycle start
#01
2
1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start
#10
3
Reserved
#11
ASYMMODE4
Asymmetric PWMx_CH4 Reload Mode Setting\n
24
2
read-write
0
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#00
1
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#01
2
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#10
3
Reserved
#11
EPWM_BRKOUT
EPWM_BRKOUT
PWM Brake Output
0x30
read-write
n
0x0
0x0
BRKOUT
PWM Brake Output\nWhen PWM Brake is asserted, the PWM_CH0~5 output state before polarity control will follow bit0~5 setting, respectively.\n
0
6
read-write
0
The PWM_CHn output before polarity control is low when Brake is asserted
0
1
The PWM_CHn output before polarity control is high when Brake is asserted
1
EPWM_CMPDAT0
EPWM_CMPDAT0
EPWM_CMPDAT0 Duty Register
0xC
read-write
n
0x0
0x0
CMP
PWM Duty Register\nEdge aligned:\n
0
16
read-write
EPWM_CMPDAT2
EPWM_CMPDAT2
EPWM_CMPDAT2 Duty Register
0x10
read-write
n
0x0
0x0
EPWM_CMPDAT4
EPWM_CMPDAT4
EPWM_CMPDAT4 Duty Register
0x14
read-write
n
0x0
0x0
EPWM_CTL
EPWM_CTL
PWM Control Register
0x0
read-write
n
0x0
0x0
BRK0NFDIS
PWM Brake 0 Noise Filter Disable Bit\n
28
1
read-write
0
Noise filter of PWM Brake 0 Enabled
#0
1
Noise filter of PWM Brake 0 Disabled
#1
BRK0NFSEL
Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
20
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRK1NFDIS
PWM Brake 1 Noise Filter Disable Bit\n
29
1
read-write
0
Noise filter of PWM Brake 1 Enabled
#0
1
Noise filter of PWM Brake 1 Disabled
#1
BRK1NFSEL
Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
22
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRK1SEL
Brake Function 1 Source Selection\n
18
2
read-write
0
From external pin BKPx1 (x=0~1 for unit0~1)
#00
1
From analog comparator 0 output (CPO0)
#01
2
From analog comparator 1 output (CPO1)
#10
3
From analog comparator 2 output (CPO2)
#11
BRKIEN
Brake0 And Brak1 Interrupt Enable Bit\n
5
1
read-write
0
Disabling flags BRKIF0 and BRKIF1 to trigger PWM interrupt
#0
1
Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt
#1
BRKP0EN
BKPx0 Pin Trigger Brake Function0 Enable Bit\n
16
1
read-write
0
PWMx Brake Function 0 Disabled
#0
1
PWMx Brake Function 0 Enabled
#1
BRKP0INV
Inverse BKP0 State\n
14
1
read-write
0
The state of pin BKPx0 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx0 is passed to the negative edge detector
#1
BRKP1EN
BKPx1 Pin Trigger Brake Function Enable Bit\n
17
1
read-write
0
PWMx Brake Function 1 Disabled
#0
1
PWMx Brake Function 1 Enabled
#1
BRKP1INV
Inverse BKP1 State\n
15
1
read-write
0
The state of pin BKPx1 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx1 is passed to the negative edge detector
#1
CLKDIV
PWM Clock Pre-Divider Selection\n
2
2
read-write
0
PWM clock = EPWM_CLK
#00
1
PWM clock = EPWM_CLK/2
#01
2
PWM clock = EPWM_CLK/4
#10
3
PWM clock = EPWM_CLK/16
#11
CNTCLR
Clear PWM Counter Control\nNote: It is automatically cleared by hardware.
11
1
read-write
1
Clear 16-bit PWM counter to 000H
#1
CNTEN
Start CNTEN Control\n
7
1
read-write
0
The PWM stops running
#0
1
The PWM counter starts running
#1
CNTTYPE
PWM Aligned Type Selection\n
12
1
read-write
0
Edge-aligned type
#0
1
Centre-aligned type
#1
CPO0BKEN
CPO0 Digital Output As Brake0 Source Enable Bit\n
24
1
read-write
0
CPO0 as one brake source in Brake 0 Disabled
#0
1
CPO0 as one brake source in Brake 0 Enabled
#1
CPO1BKEN
CPO1 Digital Output As Brake 0 Source Enable Bit\n
25
1
read-write
0
CPO1 as one brake source in Brake 0 Disabled
#0
1
CPO1 as one brake source in Brake 0 Enabled
#1
CPO2BKEN
CPO2 Digital Output As Brake 0 Source Enable Bit\n
26
1
read-write
0
CPO2 as one brake source in Brake 0 Disabled
#0
1
CPO2 as one brake source in Brake 0 Enabled
#1
CTRLD
Center Reload Mode Enable Bit\nThis bit only work when EPWM operation at center aligned mode.
31
1
read-write
0
EPWM reload compare register at the period point of PWM counter
#0
1
EPWM reload compare register at the center point of PWM counter
#1
GROUPEN
Group Bit\n
13
1
read-write
0
The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent
#0
1
Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0
#1
INTTYPE
PWM Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only.
8
1
read-write
0
PIF will be set if PWM counter underflow
#0
1
PIF will be set if PWM counter matches EPWM_PERIOD register
#1
LOAD
Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Compare Registers (EPWM_CMPDAT0~4) Control \nNote: This bit is software write, hardware clear and always read zero.
6
1
read-write
0
No action if written with 0. The value of PWM period register (EPWM_PERIOD) and PWM compare registers (EPWM_CMPDAT0~EPWM_CMPDAT4) are not loaded to PWM counter and Comparator registers
#0
1
Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM compare registers (EPWM_CMPDAT0~EPWM_CMPDAT4) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode
#1
LVDBKEN
Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n
27
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
MODE
PWM Mode Selection\n
0
2
read-write
0
Independent mode
#00
1
Pair/Complementary mode
#01
2
Synchronized mode
#10
3
Reserved
#11
PINV
Inverse PWM Comparator Output\nWhen PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.\n
9
1
read-write
0
Not inverse PWM comparator output
#0
1
Inverse PWM comparator output
#1
PWMIEN
PWM Interrupt Enable Bit\n
4
1
read-write
0
Disabling flag PIF to trigger PWM interrupt
#0
1
Enabling flag PIF can trigger PWM interrupt
#1
EPWM_DTCTL
EPWM_DTCTL
PWM Dead-time Control Register
0x2C
read-write
n
0x0
0x0
DTCNT
Dead-Time Counter\nThe dead-time can be calculated from the following formula: \n
0
11
read-write
DTEN0
Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH0, PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
16
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM_CH0, PWM_CH1)
#0
1
Dead-time insertion Enabled on the pin pair (PWM_CH0, PWM_CH1)
#1
DTEN2
Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH2, PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
17
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM_CH2, PWM_CH3)
#0
1
Dead-time insertion Enabled on the pin pair (PWM_CH2, PWM_CH3)
#1
DTEN4
Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH4, PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
18
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM_CH4, PWM_CH5)
#0
1
Dead-time insertion Enabled on the pin pair (PWM_CH4, PWM_CH5)
#1
EPWM_EINTCTL
EPWM_EINTCTL
PWM Edge Interrupt Control Register
0x40
read-write
n
0x0
0x0
EDGEIEN0
PWMx0 Edge Interrupt Enable Bit\n
0
1
read-write
0
Disabling flag EIF0 to trigger PWM interrupt
#0
1
Enabling flag EIF0 can trigger PWM interrupt
#1
EDGEIEN2
PWMx2 Edge Interrupt Enable Bit\n
1
1
read-write
0
Disabling flag EIF2 can trigger PWM interrupt
#0
1
Enabling flag EIF2 can trigger PWM interrupt
#1
EDGEIEN4
PWMx4 Edge Interrupt Enable Bit\n
2
1
read-write
0
Disable flag EIF4 to trigger PWM interrupt
#0
1
Enabling flag EIF4 can trigger PWM interrupt
#1
EINTTYPE0
PWMx0 Edge Interrupt Type\n
8
1
read-write
0
EIF0 will be set if falling edge is detected at PWMx0
#0
1
EIF0 will be set if rising edge is detected at PWMx0
#1
EINTTYPE2
PWMx2 Edge Interrupt Type\n
9
1
read-write
0
EIF2 will be set if falling edge is detected at PWMx2
#0
1
EIF2 will be set if rising edge is detected at PWMx2
#1
EINTTYPE4
PWMx4 Edge Interrupt Type\n
10
1
read-write
0
EIF4 will be set if falling edge is detected at PWMx4
#0
1
EIF4 will be set if rising edge is detected at PWMx4
#1
EPWM_MSK
EPWM_MSK
PWM Mask Mode Data Register
0x1C
read-write
n
0x0
0x0
MSKDAT
PWM Mask Data Bit\n
0
6
read-write
0
Output logic low to EPWM_CHn
0
1
Output logic high to EPWM_CHn
1
EPWM_MSKEN
EPWM_MSKEN
PWM Mask Mode Enable Control Register
0x18
read-write
n
0x0
0x0
MSKEN
PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled. The corresponding EPWM_CHn channel will be output with EPWM_MSK[n] data. \n
0
6
read-write
0
PWM generator signal is output to next stage
0
1
PWM generator signal is masked and EPWM_MSK[n] is output to next stage
1
EPWM_NPCTL
EPWM_NPCTL
PWM Negative Polarity Control
0x34
read-write
n
0x0
0x0
NEGPOLAR
PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
0
6
read-write
0
PWM_CHn output is active high
0
1
PWM_CHn output is active low
1
EPWM_OUTEN0
EPWM_OUTEN0
PWM Output Enable Control Register
0x44
read-write
n
0x0
0x0
EVENOUTEN
PWM Even Ports Output Enable Bit\n
0
1
read-write
0
PWM even ports output Disabled (PWM even ports at tri-state)
#0
1
PWM even ports output Enabled
#1
ODDOUTEN
PWM Odd Ports Output Enable Bit\n
1
1
read-write
0
PWM odd ports output Disabled (PWM even ports at tri-state)
#0
1
PWM odd ports output Enabled
#1
EPWM_PERIOD
EPWM_PERIOD
PWM Period Register
0x8
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nEdge aligned:\n
0
16
read-write
EPWM_PERIODCNT
EPWM_PERIODCNT
PIF Compared Counter
0x3C
read-write
n
0x0
0x0
PERIODCNT
PIF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt. \nPIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred.
0
4
read-write
EPWM_STATUS
EPWM_STATUS
PWM Status Register
0x4
read-write
n
0x0
0x0
BRK0LOCK
PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it.
8
1
read-write
0
Brake 0 state is released
#0
1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
#1
BRK0STS
Brake 0 Status (Read Only)\n
24
1
read-only
0
PWM had been out of Brake 0 state
#0
1
PWM is in Brake 0 state
#1
BRK1STS
Brake 1 Status (Read Only)\n
25
1
read-only
0
PWM had been out of Brake 1 state
#0
1
PWM is in Brake 1 state
#1
BRKIF0
PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it.
0
1
read-write
0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#0
1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
#1
BRKIF1
PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it.
1
1
read-write
0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#0
1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
#1
EIF0
PWMx_CH0 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
4
1
read-write
0
The PWMx_CH0 doesn't toggle
#0
1
Hardware will set this flag to high at the time of PWMx_CH0 rising or falling. If EDGEIEN0(EPWM_EINTCTL[8]) = 0, this bit is set when PWMx_CH0 falling is detected. If EDGEIEN0(EPWM_EINTCTL[8]) = 1, this bit is set when PWMx_CH0 rising is detected.
#1
EIF2
PWMx_CH2 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
5
1
read-write
0
The PWMx_CH2 doesn't toggle
#0
1
Hardware will set this flag to high at the time of PWMx_CH2 rising or falling. If EDGEIEN2(EPWM_EINTCTL[9]) = 0, this bit is set when PWMx_CH2 falling is detected. If EDGEIEN2(EPWM_EINTCTL[9])= 1, this bit is set when PWMx_CH2 rising is detected.
#1
EIF4
PWMx_CH4 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
6
1
read-write
0
The PWMx_CH4 doesn't toggle.
#0
1
Hardware will set this flag to high at the time of PWMx_CH4 rising or falling. If EDGEIEN4(EPWM_EINTCTL[10]) = 0, this bit is set when PWMx_CH4 falling is detected. If EDGEIEN4(EPWM_EINTCTL[10]) = 1, this bit is set when PWMx_CH4 rising is detected.
#1
PIF
PWM Period Flag\nNote: This bit must be cleared by writing 1 to it.
2
1
read-write
0
PWM Counter has not up counted to the value of PERIOD or down counted with underflow.
#0
1
Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode
#1
EPWM1
EPWM Register Map
EPWM
0x0
0x0
0x48
registers
n
EPWM_ASYMCMP0
EPWM_ASYMCMP0
Asymmetric EPWM_CMPDAT0 Duty Register
0x20
read-write
n
0x0
0x0
CMP
Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle.
0
16
read-write
EPWM_ASYMCMP2
EPWM_ASYMCMP2
Asymmetric EPWM_CMPDAT2 Duty Register
0x24
read-write
n
0x0
0x0
EPWM_ASYMCMP4
EPWM_ASYMCMP4
Asymmetric EPWM_CMPDAT4 Duty Register
0x28
read-write
n
0x0
0x0
EPWM_ASYMCTL
EPWM_ASYMCTL
Asymmetric PWM Control Register
0x38
read-write
n
0x0
0x0
ASYMEN
Asymmetric PWM Enable Bit\nNote: This control bit is only valid when PWM module is set in Centre-aligned mode.
0
1
read-write
0
Asymmetric PWM function Disabled
#0
1
Asymmetric PWM function Enabled
#1
ASYMMODE0
Asymmetric PWMx_CH0 Reload Mode Setting\n
8
2
read-write
0
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#00
1
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#01
2
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#10
3
Reserved
#11
ASYMMODE2
Asymmetric PWMx_CH2 Reload Mode Setting\n
16
2
read-write
0
1. PWM compare register 2 is reload CMP (EPWM_CMPDAT2[15:0]) at PWM cycle start
#00
1
1. PWM compare register 2 is reload CMP (EPWM_CMPDAT2[15:0]) at PWM cycle start
#01
2
1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start
#10
3
Reserved
#11
ASYMMODE4
Asymmetric PWMx_CH4 Reload Mode Setting\n
24
2
read-write
0
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#00
1
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#01
2
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#10
3
Reserved
#11
EPWM_BRKOUT
EPWM_BRKOUT
PWM Brake Output
0x30
read-write
n
0x0
0x0
BRKOUT
PWM Brake Output\nWhen PWM Brake is asserted, the PWM_CH0~5 output state before polarity control will follow bit0~5 setting, respectively.\n
0
6
read-write
0
The PWM_CHn output before polarity control is low when Brake is asserted
0
1
The PWM_CHn output before polarity control is high when Brake is asserted
1
EPWM_CMPDAT0
EPWM_CMPDAT0
EPWM_CMPDAT0 Duty Register
0xC
read-write
n
0x0
0x0
CMP
PWM Duty Register\nEdge aligned:\n
0
16
read-write
EPWM_CMPDAT2
EPWM_CMPDAT2
EPWM_CMPDAT2 Duty Register
0x10
read-write
n
0x0
0x0
EPWM_CMPDAT4
EPWM_CMPDAT4
EPWM_CMPDAT4 Duty Register
0x14
read-write
n
0x0
0x0
EPWM_CTL
EPWM_CTL
PWM Control Register
0x0
read-write
n
0x0
0x0
BRK0NFDIS
PWM Brake 0 Noise Filter Disable Bit\n
28
1
read-write
0
Noise filter of PWM Brake 0 Enabled
#0
1
Noise filter of PWM Brake 0 Disabled
#1
BRK0NFSEL
Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
20
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRK1NFDIS
PWM Brake 1 Noise Filter Disable Bit\n
29
1
read-write
0
Noise filter of PWM Brake 1 Enabled
#0
1
Noise filter of PWM Brake 1 Disabled
#1
BRK1NFSEL
Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
22
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRK1SEL
Brake Function 1 Source Selection\n
18
2
read-write
0
From external pin BKPx1 (x=0~1 for unit0~1)
#00
1
From analog comparator 0 output (CPO0)
#01
2
From analog comparator 1 output (CPO1)
#10
3
From analog comparator 2 output (CPO2)
#11
BRKIEN
Brake0 And Brak1 Interrupt Enable Bit\n
5
1
read-write
0
Disabling flags BRKIF0 and BRKIF1 to trigger PWM interrupt
#0
1
Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt
#1
BRKP0EN
BKPx0 Pin Trigger Brake Function0 Enable Bit\n
16
1
read-write
0
PWMx Brake Function 0 Disabled
#0
1
PWMx Brake Function 0 Enabled
#1
BRKP0INV
Inverse BKP0 State\n
14
1
read-write
0
The state of pin BKPx0 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx0 is passed to the negative edge detector
#1
BRKP1EN
BKPx1 Pin Trigger Brake Function Enable Bit\n
17
1
read-write
0
PWMx Brake Function 1 Disabled
#0
1
PWMx Brake Function 1 Enabled
#1
BRKP1INV
Inverse BKP1 State\n
15
1
read-write
0
The state of pin BKPx1 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx1 is passed to the negative edge detector
#1
CLKDIV
PWM Clock Pre-Divider Selection\n
2
2
read-write
0
PWM clock = EPWM_CLK
#00
1
PWM clock = EPWM_CLK/2
#01
2
PWM clock = EPWM_CLK/4
#10
3
PWM clock = EPWM_CLK/16
#11
CNTCLR
Clear PWM Counter Control\nNote: It is automatically cleared by hardware.
11
1
read-write
1
Clear 16-bit PWM counter to 000H
#1
CNTEN
Start CNTEN Control\n
7
1
read-write
0
The PWM stops running
#0
1
The PWM counter starts running
#1
CNTTYPE
PWM Aligned Type Selection\n
12
1
read-write
0
Edge-aligned type
#0
1
Centre-aligned type
#1
CPO0BKEN
CPO0 Digital Output As Brake0 Source Enable Bit\n
24
1
read-write
0
CPO0 as one brake source in Brake 0 Disabled
#0
1
CPO0 as one brake source in Brake 0 Enabled
#1
CPO1BKEN
CPO1 Digital Output As Brake 0 Source Enable Bit\n
25
1
read-write
0
CPO1 as one brake source in Brake 0 Disabled
#0
1
CPO1 as one brake source in Brake 0 Enabled
#1
CPO2BKEN
CPO2 Digital Output As Brake 0 Source Enable Bit\n
26
1
read-write
0
CPO2 as one brake source in Brake 0 Disabled
#0
1
CPO2 as one brake source in Brake 0 Enabled
#1
CTRLD
Center Reload Mode Enable Bit\nThis bit only work when EPWM operation at center aligned mode.
31
1
read-write
0
EPWM reload compare register at the period point of PWM counter
#0
1
EPWM reload compare register at the center point of PWM counter
#1
GROUPEN
Group Bit\n
13
1
read-write
0
The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent
#0
1
Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0
#1
INTTYPE
PWM Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only.
8
1
read-write
0
PIF will be set if PWM counter underflow
#0
1
PIF will be set if PWM counter matches EPWM_PERIOD register
#1
LOAD
Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Compare Registers (EPWM_CMPDAT0~4) Control \nNote: This bit is software write, hardware clear and always read zero.
6
1
read-write
0
No action if written with 0. The value of PWM period register (EPWM_PERIOD) and PWM compare registers (EPWM_CMPDAT0~EPWM_CMPDAT4) are not loaded to PWM counter and Comparator registers
#0
1
Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM compare registers (EPWM_CMPDAT0~EPWM_CMPDAT4) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode
#1
LVDBKEN
Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n
27
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
MODE
PWM Mode Selection\n
0
2
read-write
0
Independent mode
#00
1
Pair/Complementary mode
#01
2
Synchronized mode
#10
3
Reserved
#11
PINV
Inverse PWM Comparator Output\nWhen PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.\n
9
1
read-write
0
Not inverse PWM comparator output
#0
1
Inverse PWM comparator output
#1
PWMIEN
PWM Interrupt Enable Bit\n
4
1
read-write
0
Disabling flag PIF to trigger PWM interrupt
#0
1
Enabling flag PIF can trigger PWM interrupt
#1
EPWM_DTCTL
EPWM_DTCTL
PWM Dead-time Control Register
0x2C
read-write
n
0x0
0x0
DTCNT
Dead-Time Counter\nThe dead-time can be calculated from the following formula: \n
0
11
read-write
DTEN0
Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH0, PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
16
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM_CH0, PWM_CH1)
#0
1
Dead-time insertion Enabled on the pin pair (PWM_CH0, PWM_CH1)
#1
DTEN2
Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH2, PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
17
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM_CH2, PWM_CH3)
#0
1
Dead-time insertion Enabled on the pin pair (PWM_CH2, PWM_CH3)
#1
DTEN4
Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH4, PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
18
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM_CH4, PWM_CH5)
#0
1
Dead-time insertion Enabled on the pin pair (PWM_CH4, PWM_CH5)
#1
EPWM_EINTCTL
EPWM_EINTCTL
PWM Edge Interrupt Control Register
0x40
read-write
n
0x0
0x0
EDGEIEN0
PWMx0 Edge Interrupt Enable Bit\n
0
1
read-write
0
Disabling flag EIF0 to trigger PWM interrupt
#0
1
Enabling flag EIF0 can trigger PWM interrupt
#1
EDGEIEN2
PWMx2 Edge Interrupt Enable Bit\n
1
1
read-write
0
Disabling flag EIF2 can trigger PWM interrupt
#0
1
Enabling flag EIF2 can trigger PWM interrupt
#1
EDGEIEN4
PWMx4 Edge Interrupt Enable Bit\n
2
1
read-write
0
Disable flag EIF4 to trigger PWM interrupt
#0
1
Enabling flag EIF4 can trigger PWM interrupt
#1
EINTTYPE0
PWMx0 Edge Interrupt Type\n
8
1
read-write
0
EIF0 will be set if falling edge is detected at PWMx0
#0
1
EIF0 will be set if rising edge is detected at PWMx0
#1
EINTTYPE2
PWMx2 Edge Interrupt Type\n
9
1
read-write
0
EIF2 will be set if falling edge is detected at PWMx2
#0
1
EIF2 will be set if rising edge is detected at PWMx2
#1
EINTTYPE4
PWMx4 Edge Interrupt Type\n
10
1
read-write
0
EIF4 will be set if falling edge is detected at PWMx4
#0
1
EIF4 will be set if rising edge is detected at PWMx4
#1
EPWM_MSK
EPWM_MSK
PWM Mask Mode Data Register
0x1C
read-write
n
0x0
0x0
MSKDAT
PWM Mask Data Bit\n
0
6
read-write
0
Output logic low to EPWM_CHn
0
1
Output logic high to EPWM_CHn
1
EPWM_MSKEN
EPWM_MSKEN
PWM Mask Mode Enable Control Register
0x18
read-write
n
0x0
0x0
MSKEN
PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled. The corresponding EPWM_CHn channel will be output with EPWM_MSK[n] data. \n
0
6
read-write
0
PWM generator signal is output to next stage
0
1
PWM generator signal is masked and EPWM_MSK[n] is output to next stage
1
EPWM_NPCTL
EPWM_NPCTL
PWM Negative Polarity Control
0x34
read-write
n
0x0
0x0
NEGPOLAR
PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
0
6
read-write
0
PWM_CHn output is active high
0
1
PWM_CHn output is active low
1
EPWM_OUTEN0
EPWM_OUTEN0
PWM Output Enable Control Register
0x44
read-write
n
0x0
0x0
EVENOUTEN
PWM Even Ports Output Enable Bit\n
0
1
read-write
0
PWM even ports output Disabled (PWM even ports at tri-state)
#0
1
PWM even ports output Enabled
#1
ODDOUTEN
PWM Odd Ports Output Enable Bit\n
1
1
read-write
0
PWM odd ports output Disabled (PWM even ports at tri-state)
#0
1
PWM odd ports output Enabled
#1
EPWM_PERIOD
EPWM_PERIOD
PWM Period Register
0x8
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nEdge aligned:\n
0
16
read-write
EPWM_PERIODCNT
EPWM_PERIODCNT
PIF Compared Counter
0x3C
read-write
n
0x0
0x0
PERIODCNT
PIF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt. \nPIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred.
0
4
read-write
EPWM_STATUS
EPWM_STATUS
PWM Status Register
0x4
read-write
n
0x0
0x0
BRK0LOCK
PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it.
8
1
read-write
0
Brake 0 state is released
#0
1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
#1
BRK0STS
Brake 0 Status (Read Only)\n
24
1
read-only
0
PWM had been out of Brake 0 state
#0
1
PWM is in Brake 0 state
#1
BRK1STS
Brake 1 Status (Read Only)\n
25
1
read-only
0
PWM had been out of Brake 1 state
#0
1
PWM is in Brake 1 state
#1
BRKIF0
PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it.
0
1
read-write
0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#0
1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
#1
BRKIF1
PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it.
1
1
read-write
0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#0
1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
#1
EIF0
PWMx_CH0 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
4
1
read-write
0
The PWMx_CH0 doesn't toggle
#0
1
Hardware will set this flag to high at the time of PWMx_CH0 rising or falling. If EDGEIEN0(EPWM_EINTCTL[8]) = 0, this bit is set when PWMx_CH0 falling is detected. If EDGEIEN0(EPWM_EINTCTL[8]) = 1, this bit is set when PWMx_CH0 rising is detected
#1
EIF2
PWMx_CH2 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
5
1
read-write
0
The PWMx_CH2 doesn't toggle
#0
1
Hardware will set this flag to high at the time of PWMx_CH2 rising or falling. If EDGEIEN2(EPWM_EINTCTL[9]) = 0, this bit is set when PWMx_CH2 falling is detected. If EDGEIEN2(EPWM_EINTCTL[9])= 1, this bit is set when PWMx_CH2 rising is detected
#1
EIF4
PWMx_CH4 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
6
1
read-write
0
The PWMx_CH4 doesn't toggle
#0
1
Hardware will set this flag to high at the time of PWMx_CH4 rising or falling. If EDGEIEN4(EPWM_EINTCTL[10]) = 0, this bit is set when PWMx_CH4 falling is detected. If EDGEIEN4(EPWM_EINTCTL[10]) = 1, this bit is set when PWMx_CH4 rising is detected
#1
PIF
PWM Period Flag\nNote: This bit must be cleared by writing 1 to it.
2
1
read-write
0
PWM Counter has not up counted to the value of PERIOD or down counted with underflow
#0
1
Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode
#1
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
0x80
0x10
registers
n
0xC0
0x8
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBA
Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash is shared with APROM and data flash size is defined by user configuration and the content of this register is loaded from Config1.
0
32
read-only
FTCTL
FMC_FTCTL
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
FOM
Frequency Optimization Mode (Write Protect)\n
4
3
read-write
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADDR
ISP Address\nThe NUC442/NUC472 series is equipped with an embedded flash and supports word program only. ISPADDR[1:0] must be kept 00b for ISP operation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
CMD
ISP Command\nPlease check the table below for ISP commands.
0
6
read-write
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)\n
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
Config-Bits Update By ISP Enable Bit (Write Protect)\n
4
1
read-write
0
ISP Disabled to update config-bits
#0
1
ISP Enabled to update config-bits
#1
ISPEN
ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nNote: This bit needs to be cleared by writing 1 to it.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
read-only
n
0x0
0x0
CBS
Chip Boot Selection Mode This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
1
2
read-only
CFGCRCF
User-Configuration CRC Check Flag (Read Only)\nThis bit is set by hardware when detecting CONFIG CRC checksum is error\n
26
1
read-only
0
CONFIG CRC checksum is OK
#0
1
CONFIG CRC checksum error and force chip into LOCK mode
#1
ISPBUSY
ISP Busy Flag\n
0
1
read-only
0
ISP operation is finished
#0
1
ISP is progressed
#1
ISPFF
ISP Fail Flag (Read Only)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.
6
1
read-only
VECMAP
Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_07FF is mapping to address {VECMAP[11:2], 11'h000} ~ {VECMAP[11:2], 11'h7FF}\nVECMAP[1:0] is needed to set 0.
9
12
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed
#1
MPADDR
FMC_MPADDR
ISP Multi-word Program Address Status Register
0xC4
read-only
n
0x0
0x0
MPADDR
ISP Multi-Word Program Address Status\nMPADDR is the address of ISP Multi-Word Program operation when MPBUSY flag is 1. MPADDR will keep the final address when Multi-Word Program is aborted or finished.
0
32
read-only
MPDAT0
FMC_MPDAT0
ISP Multi-word Program Data0 Register
0x80
read-write
n
0x0
0x0
ISPDAT0
ISP Data 0\nThis register is the first 32-bit data for 32b/64b/multi-word program, and it is also the mirror of FMC_ISPDAT register, both registers keep the same data.
0
32
read-write
MPDAT1
FMC_MPDAT1
ISP Multi-word Program Data1 Register
0x84
read-write
n
0x0
0x0
ISPDAT1
ISP Data 1\nThis register is the second 32-bit data for 32b/64b/multi-word program.
0
32
read-write
MPDAT2
FMC_MPDAT2
ISP Multi-word Program Data2 Register
0x88
read-write
n
0x0
0x0
ISPDAT2
ISP Data 2\nThis register is the third 32-bit data for 32b/64b/multi-word program.
0
32
read-write
MPDAT3
FMC_MPDAT3
ISP Multi-word Program Data3 Register
0x8C
read-write
n
0x0
0x0
ISPDAT3
ISP Data 3\nThis register is the fourth 32-bit data for 32b/64b/multi-word program.
0
32
read-write
MPSTS
FMC_MPSTS
ISP Multi-word Program Status Register
0xC0
read-only
n
0x0
0x0
D0
ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 is programmed to flash complete.\n
4
1
read-only
0
FMC_MPDAT0 register is empty, or program to flash complete
#0
1
FMC_ISPDAT0 register has been written, and not programmed to flash yet
#1
D1
ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 is programmed to flash complete.\n
5
1
read-only
0
FMC_MPDAT1 register is empty, or program to flash complete
#0
1
FMC_MPDAT1 register has been written, and not programmed to flash yet
#1
D2
ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 is programmed to flash complete.\n
6
1
read-only
0
FMC_MPDAT2 register is empty, or program to flash complete
#0
1
FMC_MPDAT2 register has been written, and not programmed to flash yet
#1
D3
ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 is programmed to flash complete.\n
7
1
read-only
0
FMC_MPDAT3 register is empty, or program to flash complete
#0
1
FMC_MPDAT3 register has been written, and not programmed to flash yet
#1
ISPFF
ISP Fail Flag (Read Only)\nThis bit is set when ISP Multi-Word Program operation failed.
2
1
read-only
MPBUSY
ISP Multi-Word Program Busy Flag (Read Only)\n
0
1
read-only
0
ISP Multi-Word Program operation is aborted or finished
#0
1
ISP Multi-Word Program operation is progressed
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x2C
registers
n
0x100
0x2C
registers
n
0x140
0x2C
registers
n
0x180
0x2C
registers
n
0x1C0
0x2C
registers
n
0x200
0x2C
registers
n
0x40
0x2C
registers
n
0x440
0x4
registers
n
0x80
0x2C
registers
n
0x800
0x240
registers
n
0xC0
0x2C
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control
0x440
-1
read-write
n
0x0
0x0
DBCLKSEL
De-Bounce Sampling Cycle Selection\n
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-Bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz clock
#1
ICLKON
Interrupt Clock On Mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.\n
5
1
read-write
0
Disable the clock if the all port interrupts are disabled
#0
1
Interrupt generated circuit clock always Enabled
#1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output
0x800
-1
read-write
n
0x0
0x0
PDIO
Port N Bit M (PDIO) Value\nWrite:\nFor example, a writing of PA0 reflects the value of bit PA_DOUT[0], a reading returns the value of PA_PIN[0].
0
1
read-write
0
Clear PDIO port latch to output low.\nPort pin of PDIO is a low level
#0
1
Set PDIO port latch to output high.\nPort pin of PDIO is a high level
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output
0x828
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output
0x82C
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output
0x830
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output
0x834
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output
0x838
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output
0x83C
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output
0x804
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output
0x808
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output
0x80C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output
0x810
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output
0x814
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output
0x818
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output
0x81C
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output
0x820
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output
0x824
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
read-write
n
0x0
0x0
DATMSK0
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
0
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK1
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
1
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK10
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
10
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK11
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
11
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK12
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
12
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK13
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
13
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK14
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
14
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK15
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
15
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK2
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
2
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK3
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
3
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK4
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
4
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK5
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
5
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK6
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
6
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK7
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
7
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK8
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
8
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
DATMSK9
Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
9
1
read-write
0
Pn_DOUT[m] bit writing is valid
#0
1
Pn_DOUT[m] bit writing is ignored
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control
0x14
read-write
n
0x0
0x0
DBEN0
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
0
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN1
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
1
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN10
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
10
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN11
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
11
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN12
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
12
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN13
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
13
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN14
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
14
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN15
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
15
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN2
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
2
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN3
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
3
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN4
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
4
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN5
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
5
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN6
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
6
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN7
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
7
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN8
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
8
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
DBEN9
Port N Bit M Input De-Bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
9
1
read-write
0
Port n bit m input de-bounce Disabled
#0
1
Port n bit m input de-bounce Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
DINOFF0
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
16
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF1
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
17
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF10
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
26
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF11
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
27
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF12
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
28
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF13
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
29
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF14
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
30
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF15
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
31
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF2
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
18
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF3
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
19
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF4
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
20
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF5
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
21
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF6
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
22
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF7
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
23
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF8
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
24
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
DINOFF9
Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
25
1
read-write
0
Digital input path Enabled
#0
1
Digital input path Disabled (Digital input is tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
0
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT1
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
1
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT10
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
10
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT11
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
11
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT12
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
12
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT13
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
13
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT14
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
14
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT15
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
15
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT2
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
2
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT3
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
3
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT4
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
4
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT5
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
5
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT6
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
6
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT7
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
7
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT8
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
8
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
DOUT9
Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
9
1
read-write
0
Drive port n bit m high low
#0
1
Drive port n bit m high level
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable
0x1C
read-write
n
0x0
0x0
FLIEN0
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN1
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN10
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
10
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN11
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
11
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN12
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
12
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN13
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
13
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN14
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
14
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN15
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
15
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN2
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN3
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN4
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN5
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN6
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN7
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN8
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
8
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
FLIEN9
Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
9
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
RHIEN0
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN1
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN10
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
26
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN11
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
27
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN12
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
28
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN13
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
29
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN14
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
30
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN15
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
31
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN2
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN3
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN4
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN5
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN6
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN7
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN8
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
24
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
RHIEN9
Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
25
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
read-write
n
0x0
0x0
INTSRC0
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
0
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC1
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
1
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC10
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
10
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC11
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
11
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC12
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
12
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC13
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
13
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC14
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
14
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC15
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
15
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC2
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
2
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC3
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
3
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC4
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
4
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC5
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
5
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC6
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
6
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC7
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
7
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC8
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
8
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
INTSRC9
Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
9
1
read-write
0
No interrupt at Port n.\nNo effect
#0
1
Port n bit m generate an interrupt.\nClear the correspond pending interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Register
0x18
read-write
n
0x0
0x0
TYPE0
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE1
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE10
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
10
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE11
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
11
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE12
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
12
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE13
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
13
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE14
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
14
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE15
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
15
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE2
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE3
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE4
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE5
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE6
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE7
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE8
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
8
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
TYPE9
Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
9
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
0
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE1
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
2
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE10
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
20
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE11
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
22
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE12
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
24
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE13
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
26
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE14
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
28
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE15
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
30
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE2
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
4
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE3
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
6
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE4
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
8
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE5
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
10
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE6
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
12
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE7
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
14
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE8
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
16
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
MODE9
Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n
18
2
read-write
0
INPUT only mode
#00
1
OUTPUT mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
0
1
read-only
PIN1
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
1
1
read-only
PIN10
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
10
1
read-only
PIN11
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
11
1
read-only
PIN12
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
12
1
read-only
PIN13
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
13
1
read-only
PIN14
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
14
1
read-only
PIN15
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
15
1
read-only
PIN2
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
2
1
read-only
PIN3
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
3
1
read-only
PIN4
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
4
1
read-only
PIN5
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
5
1
read-only
PIN6
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
6
1
read-only
PIN7
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
7
1
read-only
PIN8
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
8
1
read-only
PIN9
Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
9
1
read-only
PA_SLEWCTL
PA_SLEWCTL
PA High Slew Rate Control
0x28
read-write
n
0x0
0x0
HSREN0
Port N Bit M High Slew Rate Control\n
0
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN1
Port N Bit M High Slew Rate Control\n
1
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN10
Port N Bit M High Slew Rate Control\n
10
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN11
Port N Bit M High Slew Rate Control\n
11
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN12
Port N Bit M High Slew Rate Control\n
12
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN13
Port N Bit M High Slew Rate Control\n
13
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN14
Port N Bit M High Slew Rate Control\n
14
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN15
Port N Bit M High Slew Rate Control\n
15
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN2
Port N Bit M High Slew Rate Control\n
2
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN3
Port N Bit M High Slew Rate Control\n
3
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN4
Port N Bit M High Slew Rate Control\n
4
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN5
Port N Bit M High Slew Rate Control\n
5
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN6
Port N Bit M High Slew Rate Control\n
6
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN7
Port N Bit M High Slew Rate Control\n
7
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN8
Port N Bit M High Slew Rate Control\n
8
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
HSREN9
Port N Bit M High Slew Rate Control\n
9
1
read-write
0
P I/O output with basic slew rate
#0
1
P I/O output with higher slew rate
#1
PA_SMTEN
PA_SMTEN
PA Input Schmitt Trigger Enable
0x24
read-write
n
0x0
0x0
SMTEN0
Port N Bit M Input Schmitt Trigger Enable Bit\n
0
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN1
Port N Bit M Input Schmitt Trigger Enable Bit\n
1
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN10
Port N Bit M Input Schmitt Trigger Enable Bit\n
10
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN11
Port N Bit M Input Schmitt Trigger Enable Bit\n
11
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN12
Port N Bit M Input Schmitt Trigger Enable Bit\n
12
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN13
Port N Bit M Input Schmitt Trigger Enable Bit\n
13
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN14
Port N Bit M Input Schmitt Trigger Enable Bit\n
14
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN15
Port N Bit M Input Schmitt Trigger Enable Bit\n
15
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN2
Port N Bit M Input Schmitt Trigger Enable Bit\n
2
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN3
Port N Bit M Input Schmitt Trigger Enable Bit\n
3
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN4
Port N Bit M Input Schmitt Trigger Enable Bit\n
4
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN5
Port N Bit M Input Schmitt Trigger Enable Bit\n
5
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN6
Port N Bit M Input Schmitt Trigger Enable Bit\n
6
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN7
Port N Bit M Input Schmitt Trigger Enable Bit\n
7
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN8
Port N Bit M Input Schmitt Trigger Enable Bit\n
8
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
SMTEN9
Port N Bit M Input Schmitt Trigger Enable Bit\n
9
1
read-write
0
P I/O input Schmitt Trigger function Disabled
#0
1
P I/O input Schmitt Trigger function Enabled
#1
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output
0x840
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output
0x868
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output
0x86C
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output
0x870
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output
0x874
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output
0x878
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output
0x87C
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output
0x844
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output
0x848
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output
0x84C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output
0x850
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output
0x854
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output
0x858
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output
0x85C
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output
0x860
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output
0x864
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control
0x54
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable
0x5C
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Register
0x58
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
read-write
n
0x0
0x0
PB_SLEWCTL
PB_SLEWCTL
PB High Slew Rate Control
0x68
read-write
n
0x0
0x0
PB_SMTEN
PB_SMTEN
PB Input Schmitt Trigger Enable
0x64
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output
0x880
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output
0x8A8
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output
0x8AC
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output
0x8B0
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output
0x8B4
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output
0x8B8
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output
0x8BC
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output
0x884
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output
0x888
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output
0x88C
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output
0x890
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output
0x894
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output
0x898
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output
0x89C
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output
0x8A0
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output
0x8A4
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control
0x94
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable
0x9C
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Register
0x98
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
read-write
n
0x0
0x0
PC_SLEWCTL
PC_SLEWCTL
PC High Slew Rate Control
0xA8
read-write
n
0x0
0x0
PC_SMTEN
PC_SMTEN
PC Input Schmitt Trigger Enable
0xA4
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output
0x8C0
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output
0x8E8
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output
0x8EC
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output
0x8F0
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output
0x8F4
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output
0x8F8
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output
0x8FC
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output
0x8C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output
0x8C8
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output
0x8CC
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output
0x8D0
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output
0x8D4
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output
0x8D8
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output
0x8DC
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output
0x8E0
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output
0x8E4
read-write
n
0x0
0x0
PD_DATMSK
PD_DATMSK
PD Data Output Write Mask
0xCC
read-write
n
0x0
0x0
PD_DBEN
PD_DBEN
PD De-bounce Enable Control
0xD4
read-write
n
0x0
0x0
PD_DINOFF
PD_DINOFF
PD Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
PD Data Output Value
0xC8
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
PD Interrupt Enable
0xDC
read-write
n
0x0
0x0
PD_INTSRC
PD_INTSRC
PD Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
PD_INTTYPE
PD_INTTYPE
PD Interrupt Trigger Type Register
0xD8
read-write
n
0x0
0x0
PD_MODE
PD_MODE
PD I/O Mode Control
0xC0
read-write
n
0x0
0x0
PD_PIN
PD_PIN
PD Pin Value
0xD0
read-write
n
0x0
0x0
PD_SLEWCTL
PD_SLEWCTL
PD High Slew Rate Control
0xE8
read-write
n
0x0
0x0
PD_SMTEN
PD_SMTEN
PD Input Schmitt Trigger Enable
0xE4
read-write
n
0x0
0x0
PE0_PDIO
PE0_PDIO
GPIO PE.n Pin Data Input/Output
0x900
read-write
n
0x0
0x0
PE10_PDIO
PE10_PDIO
GPIO PE.n Pin Data Input/Output
0x928
read-write
n
0x0
0x0
PE11_PDIO
PE11_PDIO
GPIO PE.n Pin Data Input/Output
0x92C
read-write
n
0x0
0x0
PE12_PDIO
PE12_PDIO
GPIO PE.n Pin Data Input/Output
0x930
read-write
n
0x0
0x0
PE13_PDIO
PE13_PDIO
GPIO PE.n Pin Data Input/Output
0x934
read-write
n
0x0
0x0
PE14_PDIO
PE14_PDIO
GPIO PE.n Pin Data Input/Output
0x938
read-write
n
0x0
0x0
PE15_PDIO
PE15_PDIO
GPIO PE.n Pin Data Input/Output
0x93C
read-write
n
0x0
0x0
PE1_PDIO
PE1_PDIO
GPIO PE.n Pin Data Input/Output
0x904
read-write
n
0x0
0x0
PE2_PDIO
PE2_PDIO
GPIO PE.n Pin Data Input/Output
0x908
read-write
n
0x0
0x0
PE3_PDIO
PE3_PDIO
GPIO PE.n Pin Data Input/Output
0x90C
read-write
n
0x0
0x0
PE4_PDIO
PE4_PDIO
GPIO PE.n Pin Data Input/Output
0x910
read-write
n
0x0
0x0
PE5_PDIO
PE5_PDIO
GPIO PE.n Pin Data Input/Output
0x914
read-write
n
0x0
0x0
PE6_PDIO
PE6_PDIO
GPIO PE.n Pin Data Input/Output
0x918
read-write
n
0x0
0x0
PE7_PDIO
PE7_PDIO
GPIO PE.n Pin Data Input/Output
0x91C
read-write
n
0x0
0x0
PE8_PDIO
PE8_PDIO
GPIO PE.n Pin Data Input/Output
0x920
read-write
n
0x0
0x0
PE9_PDIO
PE9_PDIO
GPIO PE.n Pin Data Input/Output
0x924
read-write
n
0x0
0x0
PE_DATMSK
PE_DATMSK
PE Data Output Write Mask
0x10C
read-write
n
0x0
0x0
PE_DBEN
PE_DBEN
PE De-bounce Enable Control
0x114
read-write
n
0x0
0x0
PE_DINOFF
PE_DINOFF
PE Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
PE_DOUT
PE_DOUT
PE Data Output Value
0x108
read-write
n
0x0
0x0
PE_INTEN
PE_INTEN
PE Interrupt Enable
0x11C
read-write
n
0x0
0x0
PE_INTSRC
PE_INTSRC
PE Interrupt Source Flag
0x120
read-write
n
0x0
0x0
PE_INTTYPE
PE_INTTYPE
PE Interrupt Trigger Type Register
0x118
read-write
n
0x0
0x0
PE_MODE
PE_MODE
PE I/O Mode Control
0x100
read-write
n
0x0
0x0
PE_PIN
PE_PIN
PE Pin Value
0x110
read-write
n
0x0
0x0
PE_SLEWCTL
PE_SLEWCTL
PE High Slew Rate Control
0x128
read-write
n
0x0
0x0
PE_SMTEN
PE_SMTEN
PE Input Schmitt Trigger Enable
0x124
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output
0x940
read-write
n
0x0
0x0
PF10_PDIO
PF10_PDIO
GPIO PF.n Pin Data Input/Output
0x968
read-write
n
0x0
0x0
PF11_PDIO
PF11_PDIO
GPIO PF.n Pin Data Input/Output
0x96C
read-write
n
0x0
0x0
PF12_PDIO
PF12_PDIO
GPIO PF.n Pin Data Input/Output
0x970
read-write
n
0x0
0x0
PF13_PDIO
PF13_PDIO
GPIO PF.n Pin Data Input/Output
0x974
read-write
n
0x0
0x0
PF14_PDIO
PF14_PDIO
GPIO PF.n Pin Data Input/Output
0x978
read-write
n
0x0
0x0
PF15_PDIO
PF15_PDIO
GPIO PF.n Pin Data Input/Output
0x97C
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output
0x944
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output
0x948
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output
0x94C
read-write
n
0x0
0x0
PF4_PDIO
PF4_PDIO
GPIO PF.n Pin Data Input/Output
0x950
read-write
n
0x0
0x0
PF5_PDIO
PF5_PDIO
GPIO PF.n Pin Data Input/Output
0x954
read-write
n
0x0
0x0
PF6_PDIO
PF6_PDIO
GPIO PF.n Pin Data Input/Output
0x958
read-write
n
0x0
0x0
PF7_PDIO
PF7_PDIO
GPIO PF.n Pin Data Input/Output
0x95C
read-write
n
0x0
0x0
PF8_PDIO
PF8_PDIO
GPIO PF.n Pin Data Input/Output
0x960
read-write
n
0x0
0x0
PF9_PDIO
PF9_PDIO
GPIO PF.n Pin Data Input/Output
0x964
read-write
n
0x0
0x0
PF_DATMSK
PF_DATMSK
PF Data Output Write Mask
0x14C
read-write
n
0x0
0x0
PF_DBEN
PF_DBEN
PF De-bounce Enable Control
0x154
read-write
n
0x0
0x0
PF_DINOFF
PF_DINOFF
PF Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
PF_DOUT
PF_DOUT
PF Data Output Value
0x148
read-write
n
0x0
0x0
PF_INTEN
PF_INTEN
PF Interrupt Enable
0x15C
read-write
n
0x0
0x0
PF_INTSRC
PF_INTSRC
PF Interrupt Source Flag
0x160
read-write
n
0x0
0x0
PF_INTTYPE
PF_INTTYPE
PF Interrupt Trigger Type Register
0x158
read-write
n
0x0
0x0
PF_MODE
PF_MODE
PF I/O Mode Control
0x140
read-write
n
0x0
0x0
PF_PIN
PF_PIN
PF Pin Value
0x150
read-write
n
0x0
0x0
PF_SLEWCTL
PF_SLEWCTL
PF High Slew Rate Control
0x168
read-write
n
0x0
0x0
PF_SMTEN
PF_SMTEN
PF Input Schmitt Trigger Enable
0x164
read-write
n
0x0
0x0
PG0_PDIO
PG0_PDIO
GPIO PG.n Pin Data Input/Output
0x980
read-write
n
0x0
0x0
PG10_PDIO
PG10_PDIO
GPIO PG.n Pin Data Input/Output
0x9A8
read-write
n
0x0
0x0
PG11_PDIO
PG11_PDIO
GPIO PG.n Pin Data Input/Output
0x9AC
read-write
n
0x0
0x0
PG12_PDIO
PG12_PDIO
GPIO PG.n Pin Data Input/Output
0x9B0
read-write
n
0x0
0x0
PG13_PDIO
PG13_PDIO
GPIO PG.n Pin Data Input/Output
0x9B4
read-write
n
0x0
0x0
PG14_PDIO
PG14_PDIO
GPIO PG.n Pin Data Input/Output
0x9B8
read-write
n
0x0
0x0
PG15_PDIO
PG15_PDIO
GPIO PG.n Pin Data Input/Output
0x9BC
read-write
n
0x0
0x0
PG1_PDIO
PG1_PDIO
GPIO PG.n Pin Data Input/Output
0x984
read-write
n
0x0
0x0
PG2_PDIO
PG2_PDIO
GPIO PG.n Pin Data Input/Output
0x988
read-write
n
0x0
0x0
PG3_PDIO
PG3_PDIO
GPIO PG.n Pin Data Input/Output
0x98C
read-write
n
0x0
0x0
PG4_PDIO
PG4_PDIO
GPIO PG.n Pin Data Input/Output
0x990
read-write
n
0x0
0x0
PG5_PDIO
PG5_PDIO
GPIO PG.n Pin Data Input/Output
0x994
read-write
n
0x0
0x0
PG6_PDIO
PG6_PDIO
GPIO PG.n Pin Data Input/Output
0x998
read-write
n
0x0
0x0
PG7_PDIO
PG7_PDIO
GPIO PG.n Pin Data Input/Output
0x99C
read-write
n
0x0
0x0
PG8_PDIO
PG8_PDIO
GPIO PG.n Pin Data Input/Output
0x9A0
read-write
n
0x0
0x0
PG9_PDIO
PG9_PDIO
GPIO PG.n Pin Data Input/Output
0x9A4
read-write
n
0x0
0x0
PG_DATMSK
PG_DATMSK
PG Data Output Write Mask
0x18C
read-write
n
0x0
0x0
PG_DBEN
PG_DBEN
PG De-bounce Enable Control
0x194
read-write
n
0x0
0x0
PG_DINOFF
PG_DINOFF
PG Digital Input Path Disable Control
0x184
read-write
n
0x0
0x0
PG_DOUT
PG_DOUT
PG Data Output Value
0x188
read-write
n
0x0
0x0
PG_INTEN
PG_INTEN
PG Interrupt Enable
0x19C
read-write
n
0x0
0x0
PG_INTSRC
PG_INTSRC
PG Interrupt Source Flag
0x1A0
read-write
n
0x0
0x0
PG_INTTYPE
PG_INTTYPE
PG Interrupt Trigger Type Register
0x198
read-write
n
0x0
0x0
PG_MODE
PG_MODE
PG I/O Mode Control
0x180
read-write
n
0x0
0x0
PG_PIN
PG_PIN
PG Pin Value
0x190
read-write
n
0x0
0x0
PG_SLEWCTL
PG_SLEWCTL
PG High Slew Rate Control
0x1A8
read-write
n
0x0
0x0
PG_SMTEN
PG_SMTEN
PG Input Schmitt Trigger Enable
0x1A4
read-write
n
0x0
0x0
PH0_PDIO
PH0_PDIO
GPIO PH.n Pin Data Input/Output
0x9C0
read-write
n
0x0
0x0
PH10_PDIO
PH10_PDIO
GPIO PH.n Pin Data Input/Output
0x9E8
read-write
n
0x0
0x0
PH11_PDIO
PH11_PDIO
GPIO PH.n Pin Data Input/Output
0x9EC
read-write
n
0x0
0x0
PH12_PDIO
PH12_PDIO
GPIO PH.n Pin Data Input/Output
0x9F0
read-write
n
0x0
0x0
PH13_PDIO
PH13_PDIO
GPIO PH.n Pin Data Input/Output
0x9F4
read-write
n
0x0
0x0
PH14_PDIO
PH14_PDIO
GPIO PH.n Pin Data Input/Output
0x9F8
read-write
n
0x0
0x0
PH15_PDIO
PH15_PDIO
GPIO PH.n Pin Data Input/Output
0x9FC
read-write
n
0x0
0x0
PH1_PDIO
PH1_PDIO
GPIO PH.n Pin Data Input/Output
0x9C4
read-write
n
0x0
0x0
PH2_PDIO
PH2_PDIO
GPIO PH.n Pin Data Input/Output
0x9C8
read-write
n
0x0
0x0
PH3_PDIO
PH3_PDIO
GPIO PH.n Pin Data Input/Output
0x9CC
read-write
n
0x0
0x0
PH4_PDIO
PH4_PDIO
GPIO PH.n Pin Data Input/Output
0x9D0
read-write
n
0x0
0x0
PH5_PDIO
PH5_PDIO
GPIO PH.n Pin Data Input/Output
0x9D4
read-write
n
0x0
0x0
PH6_PDIO
PH6_PDIO
GPIO PH.n Pin Data Input/Output
0x9D8
read-write
n
0x0
0x0
PH7_PDIO
PH7_PDIO
GPIO PH.n Pin Data Input/Output
0x9DC
read-write
n
0x0
0x0
PH8_PDIO
PH8_PDIO
GPIO PH.n Pin Data Input/Output
0x9E0
read-write
n
0x0
0x0
PH9_PDIO
PH9_PDIO
GPIO PH.n Pin Data Input/Output
0x9E4
read-write
n
0x0
0x0
PH_DATMSK
PH_DATMSK
PH Data Output Write Mask
0x1CC
read-write
n
0x0
0x0
PH_DBEN
PH_DBEN
PH De-bounce Enable Control
0x1D4
read-write
n
0x0
0x0
PH_DINOFF
PH_DINOFF
PH Digital Input Path Disable Control
0x1C4
read-write
n
0x0
0x0
PH_DOUT
PH_DOUT
PH Data Output Value
0x1C8
read-write
n
0x0
0x0
PH_INTEN
PH_INTEN
PH Interrupt Enable
0x1DC
read-write
n
0x0
0x0
PH_INTSRC
PH_INTSRC
PH Interrupt Source Flag
0x1E0
read-write
n
0x0
0x0
PH_INTTYPE
PH_INTTYPE
PH Interrupt Trigger Type Register
0x1D8
read-write
n
0x0
0x0
PH_MODE
PH_MODE
PH I/O Mode Control
0x1C0
read-write
n
0x0
0x0
PH_PIN
PH_PIN
PH Pin Value
0x1D0
read-write
n
0x0
0x0
PH_SLEWCTL
PH_SLEWCTL
PH High Slew Rate Control
0x1E8
read-write
n
0x0
0x0
PH_SMTEN
PH_SMTEN
PH Input Schmitt Trigger Enable
0x1E4
read-write
n
0x0
0x0
PI0_PDIO
PI0_PDIO
GPIO PI.n Pin Data Input/Output
0xA00
read-write
n
0x0
0x0
PI10_PDIO
PI10_PDIO
GPIO PI.n Pin Data Input/Output
0xA28
read-write
n
0x0
0x0
PI11_PDIO
PI11_PDIO
GPIO PI.n Pin Data Input/Output
0xA2C
read-write
n
0x0
0x0
PI12_PDIO
PI12_PDIO
GPIO PI.n Pin Data Input/Output
0xA30
read-write
n
0x0
0x0
PI13_PDIO
PI13_PDIO
GPIO PI.n Pin Data Input/Output
0xA34
read-write
n
0x0
0x0
PI14_PDIO
PI14_PDIO
GPIO PI.n Pin Data Input/Output
0xA38
read-write
n
0x0
0x0
PI15_PDIO
PI15_PDIO
GPIO PI.n Pin Data Input/Output
0xA3C
read-write
n
0x0
0x0
PI1_PDIO
PI1_PDIO
GPIO PI.n Pin Data Input/Output
0xA04
read-write
n
0x0
0x0
PI2_PDIO
PI2_PDIO
GPIO PI.n Pin Data Input/Output
0xA08
read-write
n
0x0
0x0
PI3_PDIO
PI3_PDIO
GPIO PI.n Pin Data Input/Output
0xA0C
read-write
n
0x0
0x0
PI4_PDIO
PI4_PDIO
GPIO PI.n Pin Data Input/Output
0xA10
read-write
n
0x0
0x0
PI5_PDIO
PI5_PDIO
GPIO PI.n Pin Data Input/Output
0xA14
read-write
n
0x0
0x0
PI6_PDIO
PI6_PDIO
GPIO PI.n Pin Data Input/Output
0xA18
read-write
n
0x0
0x0
PI7_PDIO
PI7_PDIO
GPIO PI.n Pin Data Input/Output
0xA1C
read-write
n
0x0
0x0
PI8_PDIO
PI8_PDIO
GPIO PI.n Pin Data Input/Output
0xA20
read-write
n
0x0
0x0
PI9_PDIO
PI9_PDIO
GPIO PI.n Pin Data Input/Output
0xA24
read-write
n
0x0
0x0
PI_DATMSK
PI_DATMSK
PI Data Output Write Mask
0x20C
read-write
n
0x0
0x0
PI_DBEN
PI_DBEN
PI De-bounce Enable Control
0x214
read-write
n
0x0
0x0
PI_DINOFF
PI_DINOFF
PI Digital Input Path Disable Control
0x204
read-write
n
0x0
0x0
PI_DOUT
PI_DOUT
PI Data Output Value
0x208
read-write
n
0x0
0x0
PI_INTEN
PI_INTEN
PI Interrupt Enable
0x21C
read-write
n
0x0
0x0
PI_INTSRC
PI_INTSRC
PI Interrupt Source Flag
0x220
read-write
n
0x0
0x0
PI_INTTYPE
PI_INTTYPE
PI Interrupt Trigger Type Register
0x218
read-write
n
0x0
0x0
PI_MODE
PI_MODE
PI I/O Mode Control
0x200
read-write
n
0x0
0x0
PI_PIN
PI_PIN
PI Pin Value
0x210
read-write
n
0x0
0x0
PI_SLEWCTL
PI_SLEWCTL
PI High Slew Rate Control
0x228
read-write
n
0x0
0x0
PI_SMTEN
PI_SMTEN
PI Input Schmitt Trigger Enable
0x224
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.19.5.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-Out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.19.5.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-Out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2C2
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.19.5.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-Out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2C3
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.19.5.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-Out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2C4
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Bit\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.19.5.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-Out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-Up Enable Bit\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2S
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
CLKDIV
I2S_CLKDIV
I2S Clock Divider Register
0x4
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by the NuMicro( NUC442/NUC472 series. Software can program these bits to generate sampling rate clock frequency.\nNote: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
8
9
read-write
MCLKDIV
Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input.\nNote: F_MCLK is the frequency of MCLK, and F_i2SCLK is the frequency of the I2S_CLK
0
6
read-write
CTL
I2S_CTL
I2S Control Register
0x0
read-write
n
0x0
0x0
FORMAT
Data Format Selection\n
7
1
read-write
0
I2S data format.\nPCM mode A
#0
1
MSB justified data format.\nPCM mode B
#1
I2SEN
I2S Controller Enable Bit\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
LZCEN
Left Channel Zero-Cross Detect Enable Bit
Note1: If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCIF(I2S_STATUS[23]) flag is set to 1.
Note2: If LZCIF Flag is set to 1, the left channel will be mute.
17
1
read-write
0
Left channel zero-cross detect Disabled
#0
1
Left channel zero-cross detect Enabled
#1
MCLKEN
Master Clock Enable Bit
Note: If the external crystal clock in NuMicro( NUC442/NUC472 series is frequency 2*N*256fs, software can program MCLKDIV(I2S_CLKDIV[5:0]) to get 256fs clock to audio codec chip.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data Control\nNote: when chip records data, only right channel data will be saved if monaural format is select.
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit\n
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit zero data
#1
PCMEN
PCM Interface Enable Bit\n
24
1
read-write
0
I2S Interface
#0
1
PCM Interface
#1
RXCLR
Clear Receive FIFO\nNote1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty.\nNote2: This bit is cleared by hardware automatically, read it return zero.
19
1
read-write
0
No Effect
#0
1
Clear RX FIFO
#1
RXEN
Receive Enable Bit\n
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXLCH
Receive Left Channel Enable Bit\n
23
1
read-write
0
Receives right channel data when monaural format is selected
#0
1
Receives left channel data when monaural format is selected
#1
RXPDMAEN
Receive DMA Enable Bit\nNote: When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
21
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTH
Receive FIFO Threshold Level\nNote: When received data word(s) in buffer is equal to or higher than threshold level then RXTHIF flag is set.
12
3
read-write
0
1 word data in receive FIFO
#000
1
2 word data in receive FIFO
#001
2
3 word data in receive FIFO
#010
3
4 word data in receive FIFO
#011
4
5 word data in receive FIFO
#100
5
6 word data in receive FIFO
#101
6
7 word data in receive FIFO
#110
7
8 word data in receive FIFO
#111
RZCEN
Right Channel Zero-Cross Detection Enable Bit\nNote1: If this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCIF(I2S_STATUS[22]) flag is set to 1.\nNote2: If RZCIF Flag is set to 1, the right channel will be mute.
16
1
read-write
0
Right channel zero-cross detect Disabled
#0
1
Right channel zero-cross detect Enabled
#1
SLAVE
Slave Mode Enable Bit\nNote: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC442/NUC472 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXCLR
Clear Transmit FIFO\nNote1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nNote2: This bit is clear by hardware automatically, read it return zero.
18
1
read-write
0
No Effect
#0
1
Clear TX FIFO
#1
TXEN
Transmit Enable Bit\n
1
1
read-write
0
Data transmission Disabled
#0
1
Data transmission Enabled
#1
TXPDMAEN
Transmit DMA Enable Bit\nNote: When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
20
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
TXTH
Transmit FIFO Threshold Level\nNote: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHIF flag is set.
9
3
read-write
0
0 word data in transmit FIFO
#000
1
1 word data in transmit FIFO
#001
2
2 words data in transmit FIFO
#010
3
3 words data in transmit FIFO
#011
4
4 words data in transmit FIFO
#100
5
5 words data in transmit FIFO
#101
6
6 words data in transmit FIFO
#110
7
7 words data in transmit FIFO
#111
WDWIDTH
Word Width\n
4
2
read-write
0
data is 8-bit
#00
1
data is 16-bit
#01
2
data is 24-bit
#10
3
data is 32-bit
#11
IEN
I2S_IEN
I2S Interrupt Enable Register
0x8
read-write
n
0x0
0x0
LZCIEN
Left Channel Zero-Cross Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and left channel zero-cross
12
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVIEN
Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF(I2S_STATUS[9]) flag is set to 1
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIEN
Receive FIFO Threshold Level Interrupt Enable Bit\nNote: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHIF bit is set to 1. If RXTHIEN bit is enabled, interrupt occur.
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDIEN
Receive FIFO Underflow Interrupt E Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1.
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RZCIEN
Right Channel Zero-Cross Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and right channel zero-cross
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVIEN
Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF(I2S_STATUS[17]) flag is set to 1
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9]).
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDIEN
Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF(I2S_STATUS[16]) flag is set to 1.
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RX
I2S_RX
I2S Receive FIFO Register
0x14
read-only
n
0x0
0x0
RX
Receive FIFO Bits\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT(I2S_STATUS[27:24]).
0
32
read-only
STATUS
I2S_STATUS
I2S Status Register
0xC
-1
read-write
n
0x0
0x0
I2SIF
I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of TXIF and RXIF bits.
0
1
read-only
0
No I2S interrupt
#0
1
I2S interrupt
#1
LZCIF
Left Channel Zero-Cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
23
1
read-write
0
No zero-cross
#0
1
Left channel zero-cross is detected
#1
RIGHT
Right Channel (Read Only)\nNote: This bit indicate current transmit data is belong to right channel
3
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Level (Read Only)\nThese bits indicate word number in receive FIFO\n
24
4
read-only
0
No data
#0000
1
1 word in receive FIFO
#0001
8
8 words in receive FIFO
#1000
RXEMPTY
Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is zero
12
1
read-only
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 8.
11
1
read-only
0
Not full
#0
1
Full
#1
RXIF
I2S Receive Interrupt (Read Only)\n
1
1
read-only
0
No receive interrupt
#0
1
Receive interrupt
#1
RXOVIF
Receive FIFO Overflow Flag\nNote1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nNote2: Write 1 to clear this bit to 0.
9
1
read-write
0
No overflow occur
#0
1
Overflow occur
#1
RXTHIF
Receive FIFO Threshold Flag (Read Only)\nNote: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT less than RXTH after software read RXFIFO register.
10
1
read-only
0
Data word(s) in FIFO is lower than threshold level
#0
1
Data word(s) in FIFO is equal or higher than threshold level
#1
RXUDIF
Receive FIFO Underflow Flag\nNote1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs.\nNote2: Write 1 to clear this bit to zero
8
1
read-write
0
No underflow occur
#0
1
Underflow occur
#1
RZCIF
Right Channel Zero-Cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
22
1
read-write
0
No zero-cross
#0
1
Right channel zero-cross is detected
#1
TXBUSY
Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.
21
1
read-only
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is busy
#1
TXCNT
Transmit FIFO Level (Read Only)\nThese bits indicate word number in transmit FIFO\n
28
4
read-only
0
No data
#0000
1
1 word in transmit FIFO
#0001
8
8 words in transmit FIFO
#1000
TXEMPTY
Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is zero\n
20
1
read-only
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 8\n
19
1
read-only
0
Not full
#0
1
Full
#1
TXIF
I2S Transmit Interrupt (Read Only)\n
2
1
read-only
0
No transmit interrupt
#0
1
Transmit interrupt
#1
TXOVIF
Transmit FIFO Overflow Flag\nNote1: Write data to transmit FIFO when it is full and this bit set to 1\nNote2: Write 1 to clear this bit to 0.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHIF
Transmit FIFO Threshold Flag (Read Only)\nNote: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT is higher than TXTH after software write TXFIFO register.
18
1
read-only
0
Data word(s) in FIFO is higher than threshold level
#0
1
Data word(s) in FIFO is equal or lower than threshold level
#1
TXUDIF
Transmit FIFO Underflow Flag\nNote1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nNote2: Write 1 to clear this bit to 0.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX
I2S_TX
I2S Transmit FIFO Register
0x10
write-only
n
0x0
0x0
TX
Transmit FIFO Bits\nI2S contains 8 words (8x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT(I2S_STATUS[31:28]).
0
32
write-only
NMI
NMI Register Map
NMI
0x0
0x0
0x8
registers
n
NMIEN
NMIEN
NMI Source Interrupt Enable Control Register
0x0
read-write
n
0x0
0x0
BOD
BOD NMI Source Enable\n
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected NMI Source Enable\n
4
1
read-write
0
Clock fail detected interrupt NMI source Disabled
#0
1
Clock fail detected interrupt NMI source Enabled
#1
EINT0
External Interrupt 0 NMI Source Enable\n
8
1
read-write
0
External interrupt 0 NMI source Disabled
#0
1
External interrupt 0 NMI source Enabled
#1
EINT1
External Interrupt 1 NMI Source Enable\n
9
1
read-write
0
External interrupt 1 NMI source Disabled
#0
1
External interrupt 1 NMI source Enabled
#1
EINT2
External Interrupt 2 NMI Source Enable\n
10
1
read-write
0
External interrupt 2 NMI source Disabled
#0
1
External interrupt 2 NMI source Enabled
#1
EINT3
External Interrupt 3 NMI Source Enable\n
11
1
read-write
0
External interrupt 3 NMI source Disabled
#0
1
External interrupt 3 NMI source Enabled
#1
EINT4
External Interrupt 4 NMI Source Enable\n
12
1
read-write
0
External interrupt 4 NMI source Disabled
#0
1
External interrupt 4 NMI source Enabled
#1
EINT5
External Interrupt 5 NMI Source Enable\n
13
1
read-write
0
External interrupt 5 NMI source Disabled
#0
1
External interrupt 5 NMI source Enabled
#1
EINT6
External Interrupt 6 NMI Source Enable\n
14
1
read-write
0
External interrupt 6 NMI source Disabled
#0
1
External interrupt 6 NMI source Enabled
#1
EINT7
External Interrupt 7 NMI Source Enable\n
15
1
read-write
0
External interrupt 7 NMI source Disabled
#0
1
External interrupt 7 NMI source Enabled
#1
IRC
IRC TRIM NMI Source Enable\n
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWK
Power-down Mode Wake-up NMI Source Enable\n
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
RTC
RTC NMI Source Enable\n
6
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
SRAMFAIL
SRAM ParityCheck Error NMI Source Enable\n
3
1
read-write
0
SRAM parity check error NMI source Disabled
#0
1
SRAM parity check error NMI source Enabled
#1
TAMPER
TAMPER_INT NMI Source Enable\n
7
1
read-write
0
Backup register tamper detected interrupt.NMI source Disabled
#0
1
Backup register tamper detected interrupt.NMI source Enabled
#1
NMISTS
NMISTS
NMI Source Interrupt Status Register
0x4
-1
read-only
n
0x0
0x0
BOD
BOD Interrupt Flag (Read Only)\n
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected Interrupt Flag (Read Only)\n
4
1
read-only
0
Clock fail detected interrupt is deasserted
#0
1
Clock fail detected interrupt is asserted
#1
EINT0
External Interrupt 0 Interrupt Flag (Read Only)\n
8
1
read-only
0
External Interrupt 0 interrupt is deasserted
#0
1
External Interrupt 0 interrupt is asserted
#1
EINT1
External Interrupt 1 Interrupt Flag (Read Only)\n
9
1
read-only
0
External Interrupt 1 interrupt is deasserted
#0
1
External Interrupt 1 interrupt is asserted
#1
EINT2
External Interrupt 2 Interrupt Flag (Read Only)\n
10
1
read-only
0
External Interrupt 2 interrupt is deasserted
#0
1
External Interrupt 2 interrupt is asserted
#1
EINT3
External Interrupt 3 Interrupt Flag (Read Only)\n
11
1
read-only
0
External Interrupt 3 interrupt is deasserted
#0
1
External Interrupt 3 interrupt is asserted
#1
EINT4
External Interrupt 4 Interrupt Flag (Read Only)\n
12
1
read-only
0
External Interrupt 4 interrupt is deasserted
#0
1
External Interrupt 4 interrupt is asserted
#1
EINT5
External Interrupt 5 Interrupt Flag (Read Only)\n
13
1
read-only
0
External Interrupt 5 interrupt is deasserted
#0
1
External Interrupt 5 interrupt is asserted
#1
EINT6
External Interrupt 6 Interrupt Flag (Read Only)\n
14
1
read-only
0
External Interrupt 6 interrupt is deasserted
#0
1
External Interrupt 6 interrupt is asserted
#1
EINT7
External Interrupt 7 Interrupt Flag (Read Only)\n
15
1
read-only
0
External Interrupt 7 interrupt is deasserted
#0
1
External Interrupt 7 interrupt is asserted
#1
IRC
IRC TRIM Interrupt Flag (Read Only)\n
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWK
Power-down Mode Wake-up Interrupt Flag (Read Only)\n
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
RTC
RTC Interrupt Flag (Read Only)\n
6
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
SRAMFAIL
SRAM ParityCheck Error Interrupt Flag (Read Only)\n
3
1
read-only
0
SRAM parity check error interrupt is deasserted
#0
1
SRAM parity check error interrupt is asserted
#1
TAMPER
TAMPER_INT Interrupt Flag (Read Only)\n
7
1
read-only
0
Backup register tamper detected interrupt is deasserted
#0
1
Backup register tamper detected interrupt is asserted
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x14
registers
n
0x100
0x14
registers
n
0x180
0x14
registers
n
0x200
0x14
registers
n
0x300
0x80
registers
n
0x80
0x14
registers
n
0xE00
0x4
registers
n
IABR0
NVIC_IABR0
IRQ0 ~ IRQ159 Active Bit Register
0x200
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. \n
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
IABR1
NVIC_IABR1
IRQ0 ~ IRQ159 Active Bit Register
0x204
read-write
n
0x0
0x0
IABR2
NVIC_IABR2
IRQ0 ~ IRQ159 Active Bit Register
0x208
read-write
n
0x0
0x0
IABR3
NVIC_IABR3
IRQ0 ~ IRQ159 Active Bit Register
0x20C
read-write
n
0x0
0x0
IABR4
NVIC_IABR4
IRQ0 ~ IRQ159 Active Bit Register
0x210
read-write
n
0x0
0x0
ICER0
NVIC_ICER0
IRQ0 ~ IRQ159 Clear-enable Control Register
0x80
read-write
n
0x0
0x0
CLRENA
Interrupt Clear Enable Control\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite:\n
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Disabled.\nInterrupt Enabled
1
ICER1
NVIC_ICER1
IRQ0 ~ IRQ159 Clear-enable Control Register
0x84
read-write
n
0x0
0x0
ICER2
NVIC_ICER2
IRQ0 ~ IRQ159 Clear-enable Control Register
0x88
read-write
n
0x0
0x0
ICER3
NVIC_ICER3
IRQ0 ~ IRQ159 Clear-enable Control Register
0x8C
read-write
n
0x0
0x0
ICER4
NVIC_ICER4
IRQ0 ~ IRQ159 Clear-enable Control Register
0x90
read-write
n
0x0
0x0
ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ159 Clear-pending Control Register
0x180
read-write
n
0x0
0x0
CLRPEND
Interrupt Clear-Pending\nThe NVIC_ICPR0-NCVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite:\n
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Removes pending state an interrupt.\nInterrupt is pending
1
ICPR1
NVIC_ICPR1
IRQ0 ~ IRQ159 Clear-pending Control Register
0x184
read-write
n
0x0
0x0
ICPR2
NVIC_ICPR2
IRQ0 ~ IRQ159 Clear-pending Control Register
0x188
read-write
n
0x0
0x0
ICPR3
NVIC_ICPR3
IRQ0 ~ IRQ159 Clear-pending Control Register
0x18C
read-write
n
0x0
0x0
ICPR4
NVIC_ICPR4
IRQ0 ~ IRQ159 Clear-pending Control Register
0x190
read-write
n
0x0
0x0
IPR0
NVIC_IPR0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x300
read-write
n
0x0
0x0
PRI_4n0
Priority Of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n1
Priority Of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n2
Priority Of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n3
Priority Of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
IPR1
NVIC_IPR1
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x304
read-write
n
0x0
0x0
IPR10
NVIC_IPR10
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x328
read-write
n
0x0
0x0
IPR11
NVIC_IPR11
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x32C
read-write
n
0x0
0x0
IPR12
NVIC_IPR12
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x330
read-write
n
0x0
0x0
IPR13
NVIC_IPR13
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x334
read-write
n
0x0
0x0
IPR14
NVIC_IPR14
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x338
read-write
n
0x0
0x0
IPR15
NVIC_IPR15
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x33C
read-write
n
0x0
0x0
IPR16
NVIC_IPR16
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x340
read-write
n
0x0
0x0
IPR17
NVIC_IPR17
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x344
read-write
n
0x0
0x0
IPR18
NVIC_IPR18
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x348
read-write
n
0x0
0x0
IPR19
NVIC_IPR19
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x34C
read-write
n
0x0
0x0
IPR2
NVIC_IPR2
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x308
read-write
n
0x0
0x0
IPR20
NVIC_IPR20
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x350
read-write
n
0x0
0x0
IPR21
NVIC_IPR21
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x354
read-write
n
0x0
0x0
IPR22
NVIC_IPR22
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x358
read-write
n
0x0
0x0
IPR23
NVIC_IPR23
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x35C
read-write
n
0x0
0x0
IPR24
NVIC_IPR24
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x360
read-write
n
0x0
0x0
IPR25
NVIC_IPR25
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x364
read-write
n
0x0
0x0
IPR26
NVIC_IPR26
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x368
read-write
n
0x0
0x0
IPR27
NVIC_IPR27
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x36C
read-write
n
0x0
0x0
IPR28
NVIC_IPR28
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x370
read-write
n
0x0
0x0
IPR29
NVIC_IPR29
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x374
read-write
n
0x0
0x0
IPR3
NVIC_IPR3
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x30C
read-write
n
0x0
0x0
IPR30
NVIC_IPR30
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x378
read-write
n
0x0
0x0
IPR31
NVIC_IPR31
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x37C
read-write
n
0x0
0x0
IPR4
NVIC_IPR4
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x310
read-write
n
0x0
0x0
IPR5
NVIC_IPR5
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x314
read-write
n
0x0
0x0
IPR6
NVIC_IPR6
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x318
read-write
n
0x0
0x0
IPR7
NVIC_IPR7
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x31C
read-write
n
0x0
0x0
IPR8
NVIC_IPR8
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x320
read-write
n
0x0
0x0
IPR9
NVIC_IPR9
IRQ0 ~ IRQ159 Interrupt Priority Control Register
0x324
read-write
n
0x0
0x0
ISER0
NVIC_ISER0
IRQ0 ~ IRQ159 Set-enable Control Register
0x0
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite:\n
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Enabled
1
ISER1
NVIC_ISER1
IRQ0 ~ IRQ159 Set-enable Control Register
0x4
read-write
n
0x0
0x0
ISER2
NVIC_ISER2
IRQ0 ~ IRQ159 Set-enable Control Register
0x8
read-write
n
0x0
0x0
ISER3
NVIC_ISER3
IRQ0 ~ IRQ159 Set-enable Control Register
0xC
read-write
n
0x0
0x0
ISER4
NVIC_ISER4
IRQ0 ~ IRQ159 Set-enable Control Register
0x10
read-write
n
0x0
0x0
ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ159 Set-pending Control Register
0x100
read-write
n
0x0
0x0
SETPEND
Interrupt Set-Pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite:\n
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Changes interrupt state to pending.\nInterrupt is pending
1
ISPR1
NVIC_ISPR1
IRQ0 ~ IRQ159 Set-pending Control Register
0x104
read-write
n
0x0
0x0
ISPR2
NVIC_ISPR2
IRQ0 ~ IRQ159 Set-pending Control Register
0x108
read-write
n
0x0
0x0
ISPR3
NVIC_ISPR3
IRQ0 ~ IRQ159 Set-pending Control Register
0x10C
read-write
n
0x0
0x0
ISPR4
NVIC_ISPR4
IRQ0 ~ IRQ159 Set-pending Control Register
0x110
read-write
n
0x0
0x0
STIR
NVIC_STIR
Software Trigger Interrupt Registers
0xE00
read-write
n
0x0
0x0
INTID
Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-63. For example, a value of 0x03 specifies interrupt IRQ3.
0
9
read-write
OPA
OPS Register Map
OPS
0x0
0x0
0x8
registers
n
CTL
OPA_CTL
OP Amplifier Control Register
0x0
read-write
n
0x0
0x0
OPAIE0
OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nThe OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE0 is set to 1, a comparator interrupt request is generated.
8
1
read-write
0
OP Amplifier 0 digital output interrupt function Disabled
#0
1
OP Amplifier 0 digital output interrupt function Enabled
#1
OPAIE1
OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE1 is set to 1, a comparator interrupt request is generated.
9
1
read-write
0
OP Amplifier 1 digital output interrupt function Disabled
#0
1
OP Amplifier 1 digital output interrupt function Enabled
#1
OPEN0
OP Amplifier 0 Enable Bit\nNote: OP Amplifier 0 output needs wait stable 20 s after OPEN0 is first set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
OPEN1
OP Amplifier 1 Enable Bit\nNote: OP Amplifier 1 output needs wait stable 20 s after OPEN1 is first set.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
OPSMTEN0
OP Amplifier 0 Schmitt Trigger Non-Inverting Buffer Enable Bit\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
OPSMTEN1
OP Amplifier 1 Schmitt Trigger Non-Inverting Buffer Enable Bit\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
STATUS
OPA_STATUS
OP Amplifier Status Register
0x4
read-write
n
0x0
0x0
OPDF0
OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
4
1
read-write
OPDF1
OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
5
1
read-write
OPDO0
OP Amplifier 0 Digital Output\n
0
1
read-write
OPDO1
OP Amplifier 1 Digital Output\n
1
1
read-write
OTG
OTG Register Map
OTG
0x0
0x0
0x14
registers
n
CTL
OTG_CTL
OTG Control Register
0x0
read-write
n
0x0
0x0
BUSREQ
OTG A-Device Bus Request\nIf user application of an OTG A-device wants to do data transfers via USB bus, set this bit to high Otherwise if user application won't use the bus any more, set this bit low. This bit will be automatically cleared if VBUSDROP bit is set to TRUE.
1
1
read-write
HNPREQEN
OTG B-Device HNP Enable/Request\nSet this bit to TRUE after the OTG A-device successfully sends a SetFeature(b_hnp_enable) command to the OTG B-device This bit will be cleared automatically when a bus reset or SESS_VLD goes from TRUE to FALSE.
2
1
read-write
OTGEN
OTG Function Enable Bit\nIf USB is configured as OTG device, this bit must set high.\n
4
1
read-write
0
OTG function Disabled
#0
1
OTG function Enabled
#1
PDEVCKON
Force OTG PHY Output Clock To USB Device\nIf software configures OTG controller as OTG device and OTG device as A-device, OTG controller will output OTG PHY clock (30 MHz) to USB device only when OTG device as A-peripheral. If software needs to configure USB device before role change (from A-Host to A-Peripheral), software can set this bit high to output OTG PHY clock to USB device.\n
7
1
read-write
0
USB device clock is available only when OTG device as a peripheral
#0
1
Force output OTG PHY clock to USB device
#1
VBUSDROP
Drop The VUSB Bus\nIf user application running on this OTG A-device wants to conserve power consumption, set this bit to high When set this bit to TRUE, BUSREQ shall be cleared as well.\n
0
1
read-write
0
Did Not drop the VBUS and keep going on USB data transfers
#0
1
Drop the VBUS to conserve power consumption
#1
WKEN
OTG Wake-Up Enable Bit\n
8
1
read-write
0
OTG ID pin status change wake-up Disabled
#0
1
OTG ID pin status change wake-up Enabled
#1
INTEN
OTG_INTEN
OTG Interrupt Enable Register
0x8
read-write
n
0x0
0x0
AVLDCHGIEN
A-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Bit\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
BVLDCHGIEN
B-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Bit\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
GOIDLEIEN
OTG Device Goes IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state. Please refer to A-device state diagram and B-device state diagram in OTG spec.
4
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
HNPFIEN
HNP Fail Interrupt Enable Bit\n
3
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
HOSTIEN
Act As Host Interrupt Enable Bit\n
7
1
read-write
0
This device as a host interrupt Disabled
#0
1
This device as a host interrupt Enabled
#1
IDCHGIEN
IDSTS Changed Interrupt Enable \n
5
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PDEVIEN
Act As Peripheral Interrupt Enable Bit\n
6
1
read-write
0
This device as a peripheral interrupt Disabled
#0
1
This device as a peripheral interrupt Enabled
#1
ROLECHGIEN
Role(Host Or Peripheral) Changed Interrupt Enable Bit\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SECHGIEN
SESSEND Status Changed Interrupt Enable Bit \n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SRPDETIEN
SRP Detected Interrupt Enable Bit\n
13
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SRPFIEN
SRP Fail Interrupt Enable Bit\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
VBCHGIEN
VBVALID Status Changed Interrupt Enable Bit\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
VBEIEN
VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
INTSTS
OTG_INTSTS
OTG Interrupt Status Register
0xC
read-write
n
0x0
0x0
AVLDCHGIF
A-Device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this flag.
9
1
read-write
0
AVLD not toggled
#0
1
AVLD from high to low or low to high
#1
BVLDCHGIF
B-Device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status.
8
1
read-write
0
BVLD not toggled
#0
1
BVLD from high to low or low to high
#1
GOIDLEIF
OTG Device Goes IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state. The OTG device will be neither a host nor a peripheral.\nNote: Write 1 to clear this flag.
4
1
read-write
0
OTG device does not go back to idle state(a_idle or b_idle)
#0
1
OTG device go back to idle state(a_idle or b_idle)
#1
HNPFIF
HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus in SE0 state, this bit will be set in specified interval (b_ase0_brst_tmr, defined in OTG spec. specification), A-device does not signal connect signal.\nNote: Write 1 to clear this flag.
3
1
read-write
HOSTIF
Act As Host Interrupt Status\nNote: Write 1 to clear this flag.
7
1
read-write
0
This device does not act as a host
#0
1
This device acts as a host
#1
IDCHGIF
ID State Change Interrupt Status\nNote1: BUSREQ (OTG_CTL[1]) will be cleared when IDDIG is high.\nNote2: Write 1 to clear this flag.
5
1
read-write
0
IDSTS not toggled
#0
1
IDSTS from high to low or from low to high
#1
PDEVIF
Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag.
6
1
read-write
0
This device does not act as a peripheral
#0
1
This device acts as a peripheral
#1
ROLECHGIF
OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host\nNote: Write 1 to clear this flag.
0
1
read-write
SECHGIF
SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag.
11
1
read-write
0
Session end not toggled
#0
1
SESSEND from high to low or from low to high
#1
SRPDETIF
SRP Detected Interrupt Status\nNote: Write 1 to clear this status.
13
1
read-write
0
SRP not detected
#0
1
SRP detected
#1
SRPFIF
SRP Fail Interrupt Status\nAfter initiating SRP, an OTG B-device will wait at least TB_SRP_FAIL min, defined in OTG specification, for the OTG A-device respond This flag is set when the OTG B-device didn't get the response from the remote A-device to turn VBUS on and generate a bus reset.\nNote: Write 1 to clear this flag.
2
1
read-write
VBCHGIF
VBVALID State Change Interrupt Status\nNote: Write 1 to clear this flag.
10
1
read-write
0
VBUS_VLD not toggled
#0
1
VBUS_VLD from high to low or from low to high
#1
VBEIF
VBUS Error Interrupt Status\nThis flag will be set in one of two conditions \nOne case is that voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A device starting to drive. \nThe other case is that the supplied VBUS drops below a minimum valid threshold due to the overcurrent condition.\nNote: Write 1 to clear this flag and recover from the VBUS error state.
1
1
read-write
PHYCTL
OTG_PHYCTL
OTG PHY Control Register
0x4
-1
read-write
n
0x0
0x0
DMPDEN
None
2
1
read-write
1
15 k resistor pull-down on D- pin Enabled
#1
DPPDEN
None
1
1
read-write
1
15 k resistor pull-down on D+ pin Enabled
#1
IDDETEN
ID Detection Enable\n
7
1
read-write
0
Sampling on ID pin Enabled
#0
1
Sampling on ID pin Disabled
#1
OTGPHYEN
OTG PHY Enable Control when Device Configured as OTG-Device\nWhen device is configured as OTG-device, hardware will not enable OTG PHY automatically. Software can set OTG_EN to enable OTG PHY.\n
9
1
read-write
0
OTG PHY Disabled
#0
1
OTG PHY Enabled
#1
PHYCLK
PHY Input Clock Selection\n
8
1
read-write
0
PHY input clock is12 MHz
#0
1
PHY input clock is 24 MHz
#1
SWPDEN
Software Control Pull-Down On Data Lines Enable Bit\nNote: Software must set this bit high before controlling DPPDEN and DMPDEN.
0
1
read-write
0
Pull-down resistors on data lines is controlled by OTG control logic
#0
1
Pull-down resistors on data lines is controlled by software
#1
VBENPOL
Off-Chip USB VBUS Power Enable Polarity\nThe OTG controller will enable off-chip USB VBUS LDO to provide VBUS power when need. The polarity of enabling off-chip BSU VBUS LDO (high active or low active) depends on the selected component. This bit provides the inverse option of off-chip USB VBUS LDO enable. \n
6
1
read-write
0
The polarity of enabling off-chip USB VBUS LDO from the OTG controller not inversed
#0
1
The polarity of enabling off-chip USB VBUS LDO from the OTG controller inversed
#1
VBSTSPOL
Off-Chip USB VBUS Power Status Polarity\nThe polarity of off-chip USB VBUS LDO valid depends on the selected component. This bit provides the inversed option of off-chip USB VBUS LDO valid.\n
5
1
read-write
0
The polarity of off-chip USB VBUS LDO valid not inversed
#0
1
The polarity of off-chip USB VBUS LDO valid inversed
#1
STATUS
OTG_STATUS
Functional Status Register
0x10
-1
read-only
n
0x0
0x0
AVLD
A-Device Session Valid Status\n
4
1
read-only
0
VBUS 0.8V
#0
1
VBUS 2V
#1
BVLD
B-Device Session Valid Status\n
3
1
read-only
0
VBUS 0.8V
#0
1
VBUS 4V
#1
IDSTS
ID Pin State Of Mini-B/Micro-Plug\n
1
1
read-only
0
Mini-A/Micro-A plug is attached
#0
1
Mini-B/Micro-B plug is attached
#1
OVERCUR
Overcurrent Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A device starting to drive\n
0
1
read-only
0
OTG A-device drives VBUS successfully
#0
1
Overcurrent condition occurred
#1
SESSEND
Session End Status \n
2
1
read-only
0
VBUS 0.8V
#0
1
VBUS 0.2V
#1
VBUSVLD
VBUS Valid Status\n
5
1
read-only
0
VBUS 4.4V
#0
1
VBUS 4.75V
#1
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x140
registers
n
0x400
0x30
registers
n
0x43C
0x4
registers
n
0x480
0x10
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Read/Write Target Abort Flag Register
0x420
read-write
n
0x0
0x0
CHCTL
PDMA_CHCTL
PDMA Channel Control Register
0x400
read-write
n
0x0
0x0
CHEN
PDMA Channel Enable Control Bit[X]\nSet this bit to 1 to enable PDMA[x] operation. \nNote1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFF to PDMA_STOP register) will clear this bit.\nNote3: If each channel is not set as enabled, each channel cannot be active.
0
16
read-write
0
PDMA channel [x] Disabled
0
1
PDMA channel [x] Enabled
1
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel 0
0x100
read-only
n
0x0
0x0
CURADDR
PDMA External Current Descriptor Address Bits\nThis field indicates a 32-bit current external descriptor address of PDMA.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external descriptor address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel 1
0x104
read-write
n
0x0
0x0
CURSCAT10
PDMA_CURSCAT10
Current Scatter-gather Descriptor Table Address of PDMA Channel 10
0x128
read-write
n
0x0
0x0
CURSCAT11
PDMA_CURSCAT11
Current Scatter-gather Descriptor Table Address of PDMA Channel 11
0x12C
read-write
n
0x0
0x0
CURSCAT12
PDMA_CURSCAT12
Current Scatter-gather Descriptor Table Address of PDMA Channel 12
0x130
read-write
n
0x0
0x0
CURSCAT13
PDMA_CURSCAT13
Current Scatter-gather Descriptor Table Address of PDMA Channel 13
0x134
read-write
n
0x0
0x0
CURSCAT14
PDMA_CURSCAT14
Current Scatter-gather Descriptor Table Address of PDMA Channel 14
0x138
read-write
n
0x0
0x0
CURSCAT15
PDMA_CURSCAT15
Current Scatter-gather Descriptor Table Address of PDMA Channel 15
0x13C
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel 2
0x108
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel 3
0x10C
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel 4
0x110
read-write
n
0x0
0x0
CURSCAT5
PDMA_CURSCAT5
Current Scatter-gather Descriptor Table Address of PDMA Channel 5
0x114
read-write
n
0x0
0x0
CURSCAT6
PDMA_CURSCAT6
Current Scatter-gather Descriptor Table Address of PDMA Channel 6
0x118
read-write
n
0x0
0x0
CURSCAT7
PDMA_CURSCAT7
Current Scatter-gather Descriptor Table Address of PDMA Channel 7
0x11C
read-write
n
0x0
0x0
CURSCAT8
PDMA_CURSCAT8
Current Scatter-gather Descriptor Table Address of PDMA Channel 8
0x120
read-write
n
0x0
0x0
CURSCAT9
PDMA_CURSCAT9
Current Scatter-gather Descriptor Table Address of PDMA Channel 9
0x124
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel 0
0x0
read-write
n
0x0
0x0
BURSIZE
Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size. But if in Single Request Type, this field is not useful and only 1 transfer item been transmitted for each transfer\n
4
3
read-write
0
128 transfers
#000
1
64 transfers
#001
2
32 transfers
#010
3
16 transfers
#011
4
8 transfers
#100
5
4 transfers
#101
6
2 transfers
#110
7
1 transfers
#111
DAINC
Destination Address Increment\nThis field is used to set the destination address increment size\n
10
2
read-write
3
No Increment (Fixed Address.)
#11
OPMODE
PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete.
0
2
read-write
0
Stop Mode. Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically
#00
1
Basic Mode. The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[x] will be asserted
#01
2
Scatter-Gather Mode. When operating in this mode, user must give the next descriptor table address in DSCTx_NEXT register PDMA will ignore this task, and then load the next task to execute
#10
SAINC
Source Address Increment\nThis field is used to set the source address increment size\n
8
2
read-write
3
No Increment (Fixed Address.)
#11
TBINTDIS
Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. When with transfer done flag, this bit is only used for scatter-gather mode. If the TBINTDIS bit is enabled when PDMA finishes this task, there will no interrupt generated. However, with the table empty flag, this bit is also useful. If it is set to '1 , the TEMPTYF will not be set when this situation has happened.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finish each transfer item, this field will be decrease imminently
16
14
read-write
TXTYPE
Request Type\n
2
1
read-write
0
Burst request type
#0
1
Single request type
#1
TXWIDTH
Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection
12
2
read-write
0
8 bits for every transfer item
#00
1
16 bits for every transfer item
#01
2
32 bits for every transfer item
#10
3
Reserved
#11
DSCT0_ENDDA
PDMA_DSCT0_ENDDA
End Destination Address Register of PDMA Channel 0
0x8
read-write
n
0x0
0x0
ENDDA
PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the destination address increment is word, this field must be filled 0x2000_0400.\n
0
32
read-write
DSCT0_ENDSA
PDMA_DSCT0_ENDSA
End Source Address Register of PDMA Channel 0
0x4
read-write
n
0x0
0x0
ENDSA
PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400.\n
0
32
read-write
DSCT0_NEXT
PDMA_DSCT0_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 0
0xC
read-write
n
0x0
0x0
NEXT
PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, that this field must fill 0x0100.\nNote3: Before filled transfer task in the description table, user must check if the descriptor table is complete.
2
14
read-write
DSCT10_CTL
PDMA_DSCT10_CTL
Descriptor Table Control Register of PDMA Channel 10
0xA0
read-write
n
0x0
0x0
DSCT10_ENDDA
PDMA_DSCT10_ENDDA
End Destination Address Register of PDMA Channel 10
0xA8
read-write
n
0x0
0x0
DSCT10_ENDSA
PDMA_DSCT10_ENDSA
End Source Address Register of PDMA Channel 10
0xA4
read-write
n
0x0
0x0
DSCT10_NEXT
PDMA_DSCT10_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 10
0xAC
read-write
n
0x0
0x0
DSCT11_CTL
PDMA_DSCT11_CTL
Descriptor Table Control Register of PDMA Channel 11
0xB0
read-write
n
0x0
0x0
DSCT11_ENDDA
PDMA_DSCT11_ENDDA
End Destination Address Register of PDMA Channel 11
0xB8
read-write
n
0x0
0x0
DSCT11_ENDSA
PDMA_DSCT11_ENDSA
End Source Address Register of PDMA Channel 11
0xB4
read-write
n
0x0
0x0
DSCT11_NEXT
PDMA_DSCT11_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 11
0xBC
read-write
n
0x0
0x0
DSCT12_CTL
PDMA_DSCT12_CTL
Descriptor Table Control Register of PDMA Channel 12
0xC0
read-write
n
0x0
0x0
DSCT12_ENDDA
PDMA_DSCT12_ENDDA
End Destination Address Register of PDMA Channel 12
0xC8
read-write
n
0x0
0x0
DSCT12_ENDSA
PDMA_DSCT12_ENDSA
End Source Address Register of PDMA Channel 12
0xC4
read-write
n
0x0
0x0
DSCT12_NEXT
PDMA_DSCT12_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 12
0xCC
read-write
n
0x0
0x0
DSCT13_CTL
PDMA_DSCT13_CTL
Descriptor Table Control Register of PDMA Channel 13
0xD0
read-write
n
0x0
0x0
DSCT13_ENDDA
PDMA_DSCT13_ENDDA
End Destination Address Register of PDMA Channel 13
0xD8
read-write
n
0x0
0x0
DSCT13_ENDSA
PDMA_DSCT13_ENDSA
End Source Address Register of PDMA Channel 13
0xD4
read-write
n
0x0
0x0
DSCT13_NEXT
PDMA_DSCT13_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 13
0xDC
read-write
n
0x0
0x0
DSCT14_CTL
PDMA_DSCT14_CTL
Descriptor Table Control Register of PDMA Channel 14
0xE0
read-write
n
0x0
0x0
DSCT14_ENDDA
PDMA_DSCT14_ENDDA
End Destination Address Register of PDMA Channel 14
0xE8
read-write
n
0x0
0x0
DSCT14_ENDSA
PDMA_DSCT14_ENDSA
End Source Address Register of PDMA Channel 14
0xE4
read-write
n
0x0
0x0
DSCT14_NEXT
PDMA_DSCT14_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 14
0xEC
read-write
n
0x0
0x0
DSCT15_CTL
PDMA_DSCT15_CTL
Descriptor Table Control Register of PDMA Channel 15
0xF0
read-write
n
0x0
0x0
DSCT15_ENDDA
PDMA_DSCT15_ENDDA
End Destination Address Register of PDMA Channel 15
0xF8
read-write
n
0x0
0x0
DSCT15_ENDSA
PDMA_DSCT15_ENDSA
End Source Address Register of PDMA Channel 15
0xF4
read-write
n
0x0
0x0
DSCT15_NEXT
PDMA_DSCT15_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 15
0xFC
read-write
n
0x0
0x0
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel 1
0x10
read-write
n
0x0
0x0
DSCT1_ENDDA
PDMA_DSCT1_ENDDA
End Destination Address Register of PDMA Channel 1
0x18
read-write
n
0x0
0x0
DSCT1_ENDSA
PDMA_DSCT1_ENDSA
End Source Address Register of PDMA Channel 1
0x14
read-write
n
0x0
0x0
DSCT1_NEXT
PDMA_DSCT1_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 1
0x1C
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel 2
0x20
read-write
n
0x0
0x0
DSCT2_ENDDA
PDMA_DSCT2_ENDDA
End Destination Address Register of PDMA Channel 2
0x28
read-write
n
0x0
0x0
DSCT2_ENDSA
PDMA_DSCT2_ENDSA
End Source Address Register of PDMA Channel 2
0x24
read-write
n
0x0
0x0
DSCT2_NEXT
PDMA_DSCT2_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 2
0x2C
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel 3
0x30
read-write
n
0x0
0x0
DSCT3_ENDDA
PDMA_DSCT3_ENDDA
End Destination Address Register of PDMA Channel 3
0x38
read-write
n
0x0
0x0
DSCT3_ENDSA
PDMA_DSCT3_ENDSA
End Source Address Register of PDMA Channel 3
0x34
read-write
n
0x0
0x0
DSCT3_NEXT
PDMA_DSCT3_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 3
0x3C
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel 4
0x40
read-write
n
0x0
0x0
DSCT4_ENDDA
PDMA_DSCT4_ENDDA
End Destination Address Register of PDMA Channel 4
0x48
read-write
n
0x0
0x0
DSCT4_ENDSA
PDMA_DSCT4_ENDSA
End Source Address Register of PDMA Channel 4
0x44
read-write
n
0x0
0x0
DSCT4_NEXT
PDMA_DSCT4_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 4
0x4C
read-write
n
0x0
0x0
DSCT5_CTL
PDMA_DSCT5_CTL
Descriptor Table Control Register of PDMA Channel 5
0x50
read-write
n
0x0
0x0
DSCT5_ENDDA
PDMA_DSCT5_ENDDA
End Destination Address Register of PDMA Channel 5
0x58
read-write
n
0x0
0x0
DSCT5_ENDSA
PDMA_DSCT5_ENDSA
End Source Address Register of PDMA Channel 5
0x54
read-write
n
0x0
0x0
DSCT5_NEXT
PDMA_DSCT5_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 5
0x5C
read-write
n
0x0
0x0
DSCT6_CTL
PDMA_DSCT6_CTL
Descriptor Table Control Register of PDMA Channel 6
0x60
read-write
n
0x0
0x0
DSCT6_ENDDA
PDMA_DSCT6_ENDDA
End Destination Address Register of PDMA Channel 6
0x68
read-write
n
0x0
0x0
DSCT6_ENDSA
PDMA_DSCT6_ENDSA
End Source Address Register of PDMA Channel 6
0x64
read-write
n
0x0
0x0
DSCT6_NEXT
PDMA_DSCT6_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 6
0x6C
read-write
n
0x0
0x0
DSCT7_CTL
PDMA_DSCT7_CTL
Descriptor Table Control Register of PDMA Channel 7
0x70
read-write
n
0x0
0x0
DSCT7_ENDDA
PDMA_DSCT7_ENDDA
End Destination Address Register of PDMA Channel 7
0x78
read-write
n
0x0
0x0
DSCT7_ENDSA
PDMA_DSCT7_ENDSA
End Source Address Register of PDMA Channel 7
0x74
read-write
n
0x0
0x0
DSCT7_NEXT
PDMA_DSCT7_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 7
0x7C
read-write
n
0x0
0x0
DSCT8_CTL
PDMA_DSCT8_CTL
Descriptor Table Control Register of PDMA Channel 8
0x80
read-write
n
0x0
0x0
DSCT8_ENDDA
PDMA_DSCT8_ENDDA
End Destination Address Register of PDMA Channel 8
0x88
read-write
n
0x0
0x0
DSCT8_ENDSA
PDMA_DSCT8_ENDSA
End Source Address Register of PDMA Channel 8
0x84
read-write
n
0x0
0x0
DSCT8_NEXT
PDMA_DSCT8_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 8
0x8C
read-write
n
0x0
0x0
DSCT9_CTL
PDMA_DSCT9_CTL
Descriptor Table Control Register of PDMA Channel 9
0x90
read-write
n
0x0
0x0
DSCT9_ENDDA
PDMA_DSCT9_ENDDA
End Destination Address Register of PDMA Channel 9
0x98
read-write
n
0x0
0x0
DSCT9_ENDSA
PDMA_DSCT9_ENDSA
End Source Address Register of PDMA Channel 9
0x94
read-write
n
0x0
0x0
DSCT9_NEXT
PDMA_DSCT9_NEXT
Scatter-gather Descriptor Table Offset Address of PDMA Channel 9
0x9C
read-write
n
0x0
0x0
INTEN
PDMA_INTEN
PDMA Interrupt Enable Control Register
0x418
read-write
n
0x0
0x0
INTEN
PDMA Interrupt Enable\nThis field is used for enabling PDMA channel[x] interrupt.\n
0
16
read-write
0
PDMA channel [x] interrupt Disabled
0
1
PDMA channel [x] interrupt Enabled
1
INTSTS
PDMA_INTSTS
PDMA Interrupt Status Register
0x41C
read-write
n
0x0
0x0
ABTIF
PDMA Target Abort Status Flag
This bit indicates which PDMA has target abort error
Note: This field is read only, but software can write 1 to clear it.
0
16
read-write
0
No bus ERROR response received
0
1
Bus ERROR response received
1
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
write-only
n
0x0
0x0
FPRICLR
PDMA Fix Priority Clear Bit\nSet this bit to 1 to clear fixed priority level.\nNote: This field is Write-Only, and software can indicate the channel priority by reading PDMA_PRISET register.
0
16
write-only
0
No effect
0
1
Set PDMA channel [x] to be round-robin priority channel
1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
read-write
n
0x0
0x0
FPRISET
PDMA Fixed Priority Setting Bit[X]\nSet this bit to 1 to enable fix priority level.\nThe PDMA channel priority is shown in the following table.
0
16
read-write
0
No effect
0
1
Set PDMA channel [x] be fixed priority channel
1
REQSEL0_3
PDMA_REQSEL0_3
PDMA Source Module Select Register 0
0x480
-1
read-write
n
0x0
0x0
REQSRC0
Channel 0 Selection \nThis filed defines which peripheral is connected to PDMA channel 0. Software can configure the peripheral by setting REQSRC0.\n
0
5
read-write
0
Connect to SPI0_TX
#00000
1
Connect to SPI1_TX
#00001
2
Connect to SPI2_TX
#00010
3
Connect to SPI3_TX
#00011
4
Connect to UART0_TX
#00100
5
Connect to UART1_TX
#00101
6
Connect to UART2_TX
#00110
7
Connect to UART3_TX
#00111
8
Connect to UART4_TX
#01000
9
Connect to UART5_TX
#01001
10
Reserved
#01010
11
Connect to I2S_TX
#01011
12
Connect to I2S1_TX
#01100
13
Connect to SPI0_RX
#01101
14
Connect to SPI1_RX
#01110
15
Connect to SPI2_RX
#01111
16
Connect to SPI3_RX
#10000
17
Connect to UART0_RX
#10001
18
Connect to UART1_RX
#10010
19
Connect to UART2_RX
#10011
20
Connect to UART3_RX
#10100
21
Connect to UART4_RX
#10101
22
Connect to UART5_RX
#10110
23
Reserved
#10111
24
Connect to ADC
#11000
25
Connect to I2S_RX
#11001
26
Connect to I2S1_RX
#11010
REQSRC1
Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 1. Software can configure the peripheral setting by REQSRC1. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
5
read-write
REQSRC2
Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. Software can configure the peripheral setting by REQSRC2. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
5
read-write
REQSRC3
Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. Software can configure the peripheral setting by REQSRC3. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
5
read-write
REQSEL12_15
PDMA_REQSEL12_15
PDMA Source Module Select Register 3
0x48C
-1
read-write
n
0x0
0x0
REQSRC12
Channel 12 Selection \nThis filed defines which peripheral is connected to PDMA channel 12. Software can configure the peripheral setting by REQSRC12. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
5
read-write
REQSRC13
Channel 13 Selection \nThis filed defines which peripheral is connected to PDMA channel 13. Software can configure the peripheral setting by REQSRC13. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
5
read-write
REQSRC14
Channel 14 Selection \nThis filed defines which peripheral is connected to PDMA channel 14. Software can configure the peripheral setting by REQSRC14. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
5
read-write
REQSRC15
Channel 15 Selection \nThis filed defines which peripheral is connected to PDMA channel 15. Software can configure the peripheral setting by REQSRC15. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
5
read-write
REQSEL4_7
PDMA_REQSEL4_7
PDMA Source Module Select Register 1
0x484
-1
read-write
n
0x0
0x0
REQSRC4
Channel 0 Selection \nThis filed defines which peripheral is connected to PDMA channel 4. Software can configure the peripheral setting by REQSRC4. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
5
read-write
REQSRC5
Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 5. Software can configure the peripheral setting by REQSRC5. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
5
read-write
REQSRC6
Channel 6 Selection \nThis filed defines which peripheral is connected to PDMA channel 6. Software can configure the peripheral setting by REQSRC6. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
5
read-write
REQSRC7
Channel 7 Selection \nThis filed defines which peripheral is connected to PDMA channel 7. Software can configure the peripheral setting by REQSRC7. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
5
read-write
REQSEL8_11
PDMA_REQSEL8_11
PDMA Source Module Select Register 2
0x488
-1
read-write
n
0x0
0x0
REQSRC10
Channel 10 Selection \nThis filed defines which peripheral is connected to PDMA channel 10. Software can configure the peripheral setting by REQSRC10. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
5
read-write
REQSRC11
Channel 11 Selection \nThis filed defines which peripheral is connected to PDMA channel 11. Software can configure the peripheral setting by REQSRC11. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
5
read-write
REQSRC8
Channel 8 Selection \nThis filed defines which peripheral is connected to PDMA channel 8. Software can configure the peripheral setting by REQSRC8. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
5
read-write
REQSRC9
Channel 9 Selection \nThis filed defines which peripheral is connected to PDMA channel 9. Software can configure the peripheral setting by REQSRC9. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
5
read-write
SCATBA
PDMA_SCATBA
PDMA Scatter-gather Descriptor Table Base Address Register
0x43C
-1
read-write
n
0x0
0x0
SCATBA
PDMA Scatter-Gather Descriptor Table Base Address
In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is
Note: Only useful in Scatter-Gather mode.
16
16
read-write
SCATSTS
PDMA_SCATSTS
PDMA Scatter-gather Transfer Done Flag Register
0x428
read-write
n
0x0
0x0
TEMPTYF
Table Empty Flag
This bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode
Note: This field is read only, but software can write 1 to clear.
0
16
read-write
0
Not finished or not in Stop mode
0
1
PDMA channel has finished transmission and the operation is Stop mode
1
STOP
PDMA_STOP
PDMA Stop Transfer Register
0x404
write-only
n
0x0
0x0
STOP
PDMA Stop Transfer Bit [X]
User can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register.
The difference between software reset and PDMA_STOP register is when software set software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit and request active flag will be cleared to '0'. When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit and request active flag. Software can poll channel enable bit to know if the on-going transfer is finished.
Note1: This field is Write-Only
Note2: Setting all PDMA_STOP bit to 1 will generate software reset to reset internal state machine (the embedded table will not be reset).
0
16
write-only
0
No effect
0
1
Stop PDMA transfer[x]
1
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
write-only
n
0x0
0x0
SWREQ
PDMA Software Request Bit [X]\nSet this bit to 1 to generate a software request to PDMA [x].\nNote1: This field is Write-Only. Software can indicate which channel is on active by reading PDMA_TRGSTS register. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable each PDMA channel, the software request will be ignored.
0
12
write-only
0
No effect
0
1
Generate a software request
1
TACTSTS
PDMA_TACTSTS
PDMA Transfer on Active Flag Register
0x42C
read-only
n
0x0
0x0
TXACTF
Transfer On Active Flag\nThis bit indicates which PDMA channel is on active.\n
0
16
read-only
0
PDMA channel is not finished
0
1
PDMA channel is on active
1
TDSTS
PDMA_TDSTS
PDMA Transfer Done Flag Register
0x424
read-write
n
0x0
0x0
TDIF
Transfer Done Flag\nThis bit indicates which PDMA channel has finished transmission.\nNote: This field is read only, but software can write 1 to clear.
0
16
read-write
0
Not finished yet
0
1
PDMA channel has finished transmission
1
TRGSTS
PDMA_TRGSTS
PDMA Request Active Flag Register
0x40C
read-only
n
0x0
0x0
REQSTS
PDMA Request Active Flag [X]\nThis flag indicates whether channel[x] have a request or not.\nNote1: The request may come from software request (SWREQ) or peripheral request.\nNote2: When PDMA finishes channel transfer, this bit will be cleared automatically\nNote3: Software reset (setting PDMA_STOP to 0xFFFF_FFFF) will clear this bit.
0
16
read-only
0
Have no requests
0
1
Have a request
1
PS2
PS2 Register Map
PS2
0x0
0x0
0x20
registers
n
CTL
PS2_CTL
PS/2 Control Register
0x0
read-write
n
0x0
0x0
ACK
Acknowledge Enable Bit\n
7
1
read-write
0
Always sends acknowledge to host at 12th clock for host to device communication
#0
1
If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock
#1
CLRFIFO
Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY(PS2_STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2_STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
8
1
read-write
0
Not active
#0
1
Clear FIFO
#1
FPS2CLK
Force CLKSTAT Line\nIt forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
10
1
read-write
0
Force CLKSTAT line low
#0
1
Force CLKSTAT line high
#1
FPS2DAT
Force DATSTAT Line\nIt forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
11
1
read-write
0
Force DATSTAT low
#0
1
Force DATSTAT high
#1
OVERRIDE
Software Override PS/2 CLK/DATA Pin State\n
9
1
read-write
0
CLKSTAT and DATSTAT pins are controlled by internal state machine
#0
1
CLKSTAT and DATSTAT pins are controlled by software
#1
PS2EN
PS/2 Device Enable Bit\nEnable PS/2 device controller.\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
RXIEN
Receive Interrupt Enable Bit\n
2
1
read-write
0
Data receive complete interrupt Disabled
#0
1
Data receive complete interrupt Enabled
#1
TXFDEPTH
Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application.\n
3
4
read-write
0
1 byte
0
1
2 bytes
1
14
15 bytes
14
15
16 bytes
15
TXIEN
Transmit Interrupt Enable Bit\n
1
1
read-write
0
Data transmit complete interrupt Disabled
#0
1
Data transmit complete interrupt Enabled
#1
INTSTS
PS2_INTSTS
PS/2 Interrupt Status Register
0x1C
read-write
n
0x0
0x0
RXIF
Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXIEN(PS2_CTL[2]) bit is set to 1.\nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
No interrupt
#0
1
Receive interrupt occurred
#1
TXIF
Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXIEN(PS2_CTL[1]) bit is set to 1.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
No interrupt
#0
1
Transmit interrupt occurred
#1
RXDAT
PS2_RXDAT
PS/2 Receive DATA Register
0x14
read-only
n
0x0
0x0
DAT
Received Data
For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2_RXDAT register. CPU must read this register before next byte reception complete otherwise, the data will be overwritten and RXOV(PS2_STATUS[6]) bit will be set to 1.
0
8
read-only
STATUS
PS2_STATUS
PS/2 Status Register
0x18
-1
read-write
n
0x0
0x0
BYTEIDX
Byte Index\n
8
4
read-write
CLKSTAT
CLK Pin State\nThis bit reflects the status of the CLKSTAT line after synchronizing.
0
1
read-write
DATSTAT
DATA Pin State\nThis bit reflects the status of the DATSTAT line after synchronizing and sampling.
1
1
read-write
FRAMEERR
Frame Error
For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides CLKSTAT to send clock till DATSTAT release to high state. After that, device sends a Resend command to host.
Note: Write 1 to clear this bit.
2
1
read-write
0
No frame error
#0
1
Frame error occurred
#1
RXBUSY
Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nNote: This bit is read only.
4
1
read-write
0
Idle
#0
1
Currently receiving data
#1
RXOV
RX Buffer Overwrite\nNote: Write 1 to clear this bit.
6
1
read-write
0
No overwrite
#0
1
Data in PS2_RXDAT register is overwritten by new received data
#1
RXPARITY
Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nNote: This bit is read only.
3
1
read-write
TXBUSY
Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nNote: This bit is read only.
5
1
read-write
0
Idle
#0
1
Currently sending data
#1
TXEMPTY
TX FIFO Empty\nWhen software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nNote: This bit is read only.
7
1
read-write
0
There is data to be transmitted
#0
1
FIFO is empty
#1
TXDAT0
PS2_TXDAT0
PS/2 Transmit DATA Register 0
0x4
read-write
n
0x0
0x0
DAT
Transmit Data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
0
32
read-write
TXDAT1
PS2_TXDAT1
PS/2 Transmit DATA Register 1
0x8
read-write
n
0x0
0x0
TXDAT2
PS2_TXDAT2
PS/2 Transmit DATA Register 2
0xC
read-write
n
0x0
0x0
TXDAT3
PS2_TXDAT3
PS/2 Transmit DATA Register 3
0x10
read-write
n
0x0
0x0
PWM0
PWM Register Map
PWM
0x0
0x0
0x8C
registers
n
0x90
0x30
registers
n
0xE0
0x18
registers
n
PWM_BRKCTL
PWM_BRKCTL
PWM Brake Control Register
0x6C
read-write
n
0x0
0x0
BK1SEL
Brake Function 1 Source Selection\n
12
2
read-write
0
From external pin BKP1
#00
1
From analog comparator 0 output (CPO0)
#01
2
From analog comparator 1 output (CPO1)
#10
3
Reserved
#11
BKOD
PWM Brake Output Data Register\nNote: Each bit controls the corresponding PWM channel.
24
6
read-write
0
PWM output low when fault brake conditions asserted
0
1
PWM output high when fault brake conditions asserted
1
BRK0INV
Inverse BKP0 State\n
2
1
read-write
0
The state of pin BKPx0 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx0 is passed to the negative edge detector
#1
BRK0NFDIS
PWM Brake 0 Noise Filter Disable Bit\n
1
1
read-write
0
Noise filter of PWM Brake 0 Enabled
#0
1
Noise filter of PWM Brake 0 Disabled
#1
BRK0NFSEL
Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
6
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRK1INV
Inverse BKP1 State\n
10
1
read-write
0
The state of pin BKPx1 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx1 is passed to the negative edge detector
#1
BRK1NFDIS
PWM Brake 1 Noise Filter Disable Bit\n
9
1
read-write
0
Noise filter of PWM Brake 1 Enabled
#0
1
Noise filter of PWM Brake 1 Disabled
#1
BRK1NFSEL
Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
14
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRKP0EN
Brake0 Function Enable Bit\n
0
1
read-write
0
Brake0 detect function Disabled
#0
1
Brake0 detect function Enabled
#1
BRKP1EN
Brake1 Function Enable Bit\n
8
1
read-write
0
Brake1 function Disabled
#0
1
Brake1 function Enabled
#1
CPO0BKEN
CPO0 Digital Output As Brake0 Source Enable Bit\n
16
1
read-write
0
CPO0 as one brake source in Brake 0 Disabled
#0
1
CPO0 as one brake source in Brake 0 Enabled
#1
CPO1BKEN
CPO1 Digital Output As Brake 0 Source Enable Bit\n
17
1
read-write
0
CPO1 as one brake source in Brake 0 Disabled
#0
1
CPO1 as one brake source in Brake 0 Enabled
#1
CPO2BKEN
CPO2 Digital Output As Brake 0 Source Enable Bit\n
18
1
read-write
0
CPO2 as one brake source in Brake 0 Disabled
#0
1
CPO2 as one brake source in Brake 0 Enabled
#1
LVDBKEN
Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n
19
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x80
read-write
n
0x0
0x0
CAPEN
Capture Function Enable Bits\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
Capture function Disabled. RCAPDAT and FCAPDAT will not be updated
0
1
Capture function Enabled. Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
1
CAPINV
Capture Inverter Enable Bits\nNote: Each bit controls the corresponding PWM channel.
8
6
read-write
0
Capture source inverter Disabled
0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
1
FCRLDEN
Falling Latch Reload Enable Bits\n
24
6
read-write
0
Falling latch reload counter Disabled
0
1
Falling latch reload counter Enabled
1
RCRLDEN
Rising Latch Reload Enable Bits\n
16
6
read-write
0
Rising latch reload counter Enabled
0
1
Rising latch reload counter Enabled
1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Control Register
0x84
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Bits\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x88
read-only
n
0x0
0x0
CRIFOV
Rising Latch Interrupt Flag Overrun Status
This flag indicates if rising latch happened when the corresponding CRLIF is 1
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
0
6
read-only
FLIFOV
Falling Latch Interrupt Flag Overrun Status
This flag indicates if falling latch happened when the corresponding CFLIF is 1
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
8
6
read-only
PWM_CLKDIV
PWM_CLKDIV
PWM Clock Divide Register
0x4
read-write
n
0x0
0x0
CLKDIV0
PWM Counter Base-Clock Divide For PWMx_CH0\n (Table is the same as CLKDIV5)
0
3
read-write
CLKDIV1
PWM Counter Base-Clock Divide For PWMx_CH1\n (Table is the same as CLKDIV5)
4
3
read-write
CLKDIV2
PWM Counter Base-Clock Divide For PWMx_CH2\n (Table is the same as CLKDIV5)
8
3
read-write
CLKDIV3
PWM Counter Base-Clock Divide For PWMx_CH3\n (Table is the same as CLKDIV5)
12
3
read-write
CLKDIV4
PWM Counter Base-Clock Divide For PWMx_CH4\n (Table is the same as CLKDIV5)
16
3
read-write
CLKDIV5
PWM Counter Base-Clock Divide For PWMx_CH5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM counter has independent clock divider control register and the divided value is listed in the table below:\n
20
3
read-write
0
2
#000
1
4
#001
2
8
#010
3
16
#011
4
1
#100
PWM_CLKPSC
PWM_CLKPSC
PWM Clock Prescale Register
0x0
read-write
n
0x0
0x0
CLKPSC01
PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC01 + 1). If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
0
8
read-write
CLKPSC23
PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC23 + 1). If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
8
8
read-write
CLKPSC45
PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC45 + 1). If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
16
8
read-write
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x28
read-write
n
0x0
0x0
CMP
PWM Compare Register\nCMP determines the PWM duty.\nNote: Any write to CMP will take effect in next PWM cycle.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x2C
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x30
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x38
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x3C
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Data Register 0
0x40
read-only
n
0x0
0x0
CNT
PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter.\nNote: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read.
0
16
read-only
PWM_CNT1
PWM_CNT1
PWM Data Register 1
0x44
read-write
n
0x0
0x0
PWM_CNT2
PWM_CNT2
PWM Data Register 2
0x48
read-write
n
0x0
0x0
PWM_CNT3
PWM_CNT3
PWM Data Register 3
0x4C
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Data Register 4
0x50
read-write
n
0x0
0x0
PWM_CNT5
PWM_CNT5
PWM Data Register 5
0x54
read-write
n
0x0
0x0
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Control Register
0xC
read-write
n
0x0
0x0
CNTEN
PWM Counter Enable Bit\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM Counter Stop Running
0
1
PWM Counter Start Running
1
PWM_CTL
PWM_CTL
PWM Control Register
0x8
read-write
n
0x0
0x0
CMPINV
PWM Comparator Output Inverter Enable Bit\nWhen CMPINV is set to high, the PWM comparator output signals will be inversed, \nNote: Each bit control corresponding PWM channel
0
6
read-write
0
Comparator output inverter Disabled
0
1
Comparator output inverter Enabled
1
CNTMODE
PWM Counter Operation Mode\nNote: Each bit control corresponding PWM channel\nNote: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared.
16
6
read-write
0
PWM counter working as One-shot mode
0
1
PWM counter working as Auto-reload mode
1
CNTTYPE
PWM Counter Operation Aligned Type\nNote: Each bit control corresponding PWM channel
24
6
read-write
0
PWM counter operating as Edge-aligned type
0
1
PWM counter operating as Center-aligned type
1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nNote: The PWM pin will keep output no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
GROUPEN
Group Mode Enable Bit\n
7
1
read-write
0
The signals timing of each PWM channel are independent
#0
1
Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0 and unify the signals timing of PWM_CH1, PWM_CH3 and PWM_CH5 in the same phase which is controlled by PWM_CH1
#1
OUTMODE
PWM Output Mode\nThe register controls the output mode of PWM\n
6
1
read-write
0
PWM output at independent mode
#0
1
PWM output at complementary mode
#1
PINV
PWM Output Polar Inverse Enable Bit\nThe register controls polarity state of PWM output\nNote: Each bit controls the corresponding PWM channel.
8
6
read-write
0
PWM output polar inverse Disabled
0
1
PWM output polar inverse Enabled
1
SYNCEN
Synchronous Mode Enable Bit\nNote: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive.
15
1
read-write
0
The signals timing of each PWM channel are independent
#0
1
Unify the signals timing of PWM_CH0 and PWM_CH1 in the same phase which is controlled by PWM0 and so as another two PWM pair
#1
PWM_DTCTL
PWM_DTCTL
PWM Dead-zone Control Register
0x60
read-write
n
0x0
0x0
DTCNT01
Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
0
8
read-write
DTCNT23
Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
8
8
read-write
DTCNT45
Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
16
8
read-write
DTDIV
Dead-Zone Generator Divider\n
24
2
read-write
0
Dead-zone clock equal to PWM base clock divide 1
#00
1
Dead-zone clock equal to PWM base clock divide 2
#01
2
Dead-zone clock equal to PWM base clock divide 4
#10
3
Dead-zone clock equal to PWM base clock divide 8
#11
DTEN01
Dead-Zone Enable Control for PWM Pair Of Channel 0 and Channel 1\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
28
1
read-write
0
Dead-zone insertion Disabled
#0
1
Dead-zone insertion Enabled
#1
DTEN23
Dead-Zone Enable Control for PWM Pair Of Channel 2 and Channel 3\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
29
1
read-write
0
Dead-zone insertion Disabled
#0
1
Dead-zone insertion Enabled
#1
DTEN45
Dead-Zone Enable Control for PWM Pair Of Channel 4 and Channel 5\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
30
1
read-write
0
Dead-zone insertion Disabled
#0
1
Dead-zone insertion Enabled
#1
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Capture Falling Latch Register 0
0x94
read-only
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Capture Falling Latch Register 1
0x9C
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Capture Falling Latch Register 2
0xA4
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Capture Falling Latch Register 3
0xAC
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Capture Falling Latch Register 4
0xB4
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Capture Falling Latch Register 5
0xBC
read-write
n
0x0
0x0
PWM_INTCTL
PWM_INTCTL
PWM Interrupt Control Register
0x70
read-write
n
0x0
0x0
DINTTYPE
PWM Duty Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
8
6
read-write
0
DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting
0
1
DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting
1
PINTTYPE
PWM Period Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PIF[n] will be set if PWM counter underflow
0
1
PIF[n] will be set if PWM counter matches PWM_PERIODn register
1
PWM_INTEN
PWM_INTEN
PWM Interrupt Enable Control Register
0x74
read-write
n
0x0
0x0
BRKIEN
Brake0 and Brak1 Interrupt Enable Bit\n
6
1
read-write
0
Disabling flags BFK0 and BFK1 to trigger PWM interrupt
#0
1
Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt
#1
DIEN
PWM Duty Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
8
6
read-write
0
Duty interrupt Disabled
0
1
Duty interrupt Enabled
1
FLIEN
Falling Latch Interrupt Enable Bit\nNote: Each bit controls the corresponding PWM channel.
24
6
read-write
0
Falling latch interrupt Disabled
0
1
Falling latch interrupt Enabled
1
PIEN
PWM Period Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
Period interrupt Disabled
0
1
Period interrupt Enabled
1
RLIEN
Rising Latch Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
16
6
read-write
0
Rising latch interrupt Disabled
0
1
Rising latch interrupt Enabled
1
PWM_INTSTS
PWM_INTSTS
PWM Interrupt Flag Register
0x78
read-write
n
0x0
0x0
BRKIF0
PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it.
6
1
read-write
0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#0
1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
#1
BRKIF1
PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it.
7
1
read-write
0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#0
1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
#1
BRKLK0
PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it.
14
1
read-write
0
Brake 0 state is released
#0
1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
#1
BRKSTS0
Brake 0 Status (Read Only)\n
22
1
read-only
0
PWM had been out of Brake 0 state
#0
1
PWM is in Brake 0 state
#1
BRKSTS1
Brake 1 Status (Read Only)\n
23
1
read-only
0
PWM had been out of Brake 1 state
#0
1
PWM is in Brake 1 state
#1
CFLIF
Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
24
6
read-write
0
No capture falling latch condition happened
0
1
Capture falling latch condition happened, this flag will be set to high
1
CRLIF
Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
16
6
read-write
0
No capture rising latch condition happened
0
1
Capture rising latch condition happened, this flag will be set to high
1
DIF
PWM Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMP0. Software can clear this bit by writing 1 to it.\nNote: If CMP is equal to PERIOD, this flag is not working in edge-aligned type selection.
8
6
read-write
PIF
PWM Period Interrupt Flag\nThis bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) ). Software can write 1 to clear this bit to 0.
0
6
read-write
PWM_MSK
PWM_MSK
PWM Mask Data Register
0x5C
read-write
n
0x0
0x0
MSKDAT
PWM Mask Data Bit:\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled.\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
Output logic low to PWMn
0
1
Output logic high to PWMn
1
PWM_MSKEN
PWM_MSKEN
PWM Mask Control Register
0x58
read-write
n
0x0
0x0
MSKEN
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with MSKDAT data. \nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM output signal is non-masked
0
1
PWM output signal is masked and output with MSKDAT data
1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x10
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nPERIOD determines the PWM period.\nNote1: Any write to PERIOD will take effect in next PWM cycle.\nNote2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable.\nNote3: When PERIOD value is set to 0, PWM output is always high.
0
16
read-write
PWM_PERIOD1
PWM_PERIOD1
PWM Period Register 1
0x14
read-write
n
0x0
0x0
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x18
read-write
n
0x0
0x0
PWM_PERIOD3
PWM_PERIOD3
PWM Period Register 3
0x1C
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x20
read-write
n
0x0
0x0
PWM_PERIOD5
PWM_PERIOD5
PWM Period Register 5
0x24
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Control Register
0x7C
read-write
n
0x0
0x0
POEN
PWM Pin Output Enable Bit\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM pin at tri-state
0
1
PWM pin in output mode
1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Capture Rising Latch Register 0
0x90
read-only
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Capture Rising Latch Register 1
0x98
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Capture Rising Latch Register 2
0xA0
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Capture Rising Latch Register 3
0xA8
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Capture Rising Latch Register 4
0xB0
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Capture Rising Latch Register 5
0xB8
read-write
n
0x0
0x0
PWM_SBS0
PWM_SBS0
PWM0 Synchronous Busy Status Register
0xE0
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (PWM_CTL[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (PWM_CTL[16]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS1
PWM_SBS1
PWM1 Synchronous Busy Status Register
0xE4
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 counter operation mode CNTMOD (PWM_CTL [17]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD1/PWM_CMPDAT1/ PWM_CLKPSC or switch PWM1 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 operation mode CNTMOD (PWM_CTL [17]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS2
PWM_SBS2
PWM2 Synchronous Busy Status Register
0xE8
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 counter operation mode CNTMOD (PWM_CTL [18]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD2/PWM_CMPDAT2/ PWM_CLKPSC or switch PWM2 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 operation mode CNTMOD (PWM_CTL [18]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS3
PWM_SBS3
PWM3 Synchronous Busy Status Register
0xEC
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 counter operation mode CNTMOD (PWM_CTL [19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD3/PWM_CMPDAT3/ PWM_CLKPSC or switch PWM3 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 operation mode CNTMOD (PWM_CTL [19]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS4
PWM_SBS4
PWM4 Synchronous Busy Status Register
0xF0
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 counter operation mode CNTMOD (PWM_CTL [20]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD4/PWM_CMPDAT4/ PWM_CLKPSC or switch PWM4 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 operation mode CNTMOD (PWM_CTL [20]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS5
PWM_SBS5
PWM5 Synchronous Busy Status Register
0xF4
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 counter operation mode CNTMOD (PWM_CTL [21]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD5/PWM_CMPDAT5/ PWM_CLKPSC or switch PWM5 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 operation mode CNTMOD (PWM_CTL [21]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_TRGADCSTS
PWM_TRGADCSTS
PWM Trigger ADC Status Register
0x68
read-write
n
0x0
0x0
CTRGF
PWM Center Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
8
6
read-write
FTRGF
PWM Falling Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
16
6
read-write
PTRGF
PWM Period Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
0
6
read-write
RTRGF
PWM Rising Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
24
6
read-write
PWM_TRGADCTL
PWM_TRGADCTL
PWM Trigger Control Register
0x64
read-write
n
0x0
0x0
CTRGEN
PWM Center Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
8
6
read-write
0
PWM center point trigger ADC function Disabled
0
1
PWM center point trigger ADC function Enabled
1
FTRGEN
PWM Falling Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
16
6
read-write
0
PWM falling edge point trigger ADC function Disabled
0
1
PWM falling edge point trigger ADC function Enabled
1
PTRGEN
PWM Period Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM period point trigger ADC function Disabled
0
1
PWM period point trigger ADC function Enabled
1
RTRGEN
PWM Rising Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
24
6
read-write
0
PWM rising edge point trigger ADC function Disabled
0
1
PWM rising edge point trigger ADC function Enabled
1
PWM1
PWM Register Map
PWM
0x0
0x0
0x8C
registers
n
0x90
0x30
registers
n
0xE0
0x18
registers
n
PWM_BRKCTL
PWM_BRKCTL
PWM Brake Control Register
0x6C
read-write
n
0x0
0x0
BK1SEL
Brake Function 1 Source Selection\n
12
2
read-write
0
From external pin BKP1
#00
1
From analog comparator 0 output (CPO0)
#01
2
From analog comparator 1 output (CPO1)
#10
3
Reserved
#11
BKOD
PWM Brake Output Data Register\nNote: Each bit controls the corresponding PWM channel.
24
6
read-write
0
PWM output low when fault brake conditions asserted
0
1
PWM output high when fault brake conditions asserted
1
BRK0INV
Inverse BKP0 State\n
2
1
read-write
0
The state of pin BKPx0 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx0 is passed to the negative edge detector
#1
BRK0NFDIS
PWM Brake 0 Noise Filter Disable Bit\n
1
1
read-write
0
Noise filter of PWM Brake 0 Enabled
#0
1
Noise filter of PWM Brake 0 Disabled
#1
BRK0NFSEL
Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
6
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRK1INV
Inverse BKP1 State\n
10
1
read-write
0
The state of pin BKPx1 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx1 is passed to the negative edge detector
#1
BRK1NFDIS
PWM Brake 1 Noise Filter Disable Bit\n
9
1
read-write
0
Noise filter of PWM Brake 1 Enabled
#0
1
Noise filter of PWM Brake 1 Disabled
#1
BRK1NFSEL
Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
14
2
read-write
0
Filter clock = HCLK
#00
1
Filter clock = HCLK/2
#01
2
Filter clock = HCLK/4
#10
3
Filter clock = HCLK/16
#11
BRKP0EN
Brake0 Function Enable Bit\n
0
1
read-write
0
Brake0 detect function Disabled
#0
1
Brake0 detect function Enabled
#1
BRKP1EN
Brake1 Function Enable Bit\n
8
1
read-write
0
Brake1 function Disabled
#0
1
Brake1 function Enabled
#1
CPO0BKEN
CPO0 Digital Output As Brake0 Source Enable Bit\n
16
1
read-write
0
CPO0 as one brake source in Brake 0 Disabled
#0
1
CPO0 as one brake source in Brake 0 Enabled
#1
CPO1BKEN
CPO1 Digital Output As Brake 0 Source Enable Bit\n
17
1
read-write
0
CPO1 as one brake source in Brake 0 Disabled
#0
1
CPO1 as one brake source in Brake 0 Enabled
#1
CPO2BKEN
CPO2 Digital Output As Brake 0 Source Enable Bit\n
18
1
read-write
0
CPO2 as one brake source in Brake 0 Disabled
#0
1
CPO2 as one brake source in Brake 0 Enabled
#1
LVDBKEN
Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n
19
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x80
read-write
n
0x0
0x0
CAPEN
Capture Function Enable Bits\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
Capture function Disabled. RCAPDAT and FCAPDAT will not be updated
0
1
Capture function Enabled. Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
1
CAPINV
Capture Inverter Enable Bits\nNote: Each bit controls the corresponding PWM channel.
8
6
read-write
0
Capture source inverter Disabled
0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
1
FCRLDEN
Falling Latch Reload Enable Bits\n
24
6
read-write
0
Falling latch reload counter Disabled
0
1
Falling latch reload counter Enabled
1
RCRLDEN
Rising Latch Reload Enable Bits\n
16
6
read-write
0
Rising latch reload counter Enabled
0
1
Rising latch reload counter Enabled
1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Control Register
0x84
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Bits\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x88
read-only
n
0x0
0x0
CRIFOV
Rising Latch Interrupt Flag Overrun Status
This flag indicates if rising latch happened when the corresponding CRLIF is 1
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
0
6
read-only
FLIFOV
Falling Latch Interrupt Flag Overrun Status
This flag indicates if falling latch happened when the corresponding CFLIF is 1
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
8
6
read-only
PWM_CLKDIV
PWM_CLKDIV
PWM Clock Divide Register
0x4
read-write
n
0x0
0x0
CLKDIV0
PWM Counter Base-Clock Divide For PWMx_CH0\n (Table is the same as CLKDIV5)
0
3
read-write
CLKDIV1
PWM Counter Base-Clock Divide For PWMx_CH1\n (Table is the same as CLKDIV5)
4
3
read-write
CLKDIV2
PWM Counter Base-Clock Divide For PWMx_CH2\n (Table is the same as CLKDIV5)
8
3
read-write
CLKDIV3
PWM Counter Base-Clock Divide For PWMx_CH3\n (Table is the same as CLKDIV5)
12
3
read-write
CLKDIV4
PWM Counter Base-Clock Divide For PWMx_CH4\n (Table is the same as CLKDIV5)
16
3
read-write
CLKDIV5
PWM Counter Base-Clock Divide For PWMx_CH5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM counter has independent clock divider control register and the divided value is listed in the table below:\n
20
3
read-write
0
2
#000
1
4
#001
2
8
#010
3
16
#011
4
1
#100
PWM_CLKPSC
PWM_CLKPSC
PWM Clock Prescale Register
0x0
read-write
n
0x0
0x0
CLKPSC01
PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC01 + 1). If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
0
8
read-write
CLKPSC23
PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC23 + 1). If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
8
8
read-write
CLKPSC45
PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC45 + 1). If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
16
8
read-write
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x28
read-write
n
0x0
0x0
CMP
PWM Compare Register\nCMP determines the PWM duty.\nNote: Any write to CMP will take effect in next PWM cycle.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x2C
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x30
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x38
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x3C
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Data Register 0
0x40
read-only
n
0x0
0x0
CNT
PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter.\nNote: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read.
0
16
read-only
PWM_CNT1
PWM_CNT1
PWM Data Register 1
0x44
read-write
n
0x0
0x0
PWM_CNT2
PWM_CNT2
PWM Data Register 2
0x48
read-write
n
0x0
0x0
PWM_CNT3
PWM_CNT3
PWM Data Register 3
0x4C
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Data Register 4
0x50
read-write
n
0x0
0x0
PWM_CNT5
PWM_CNT5
PWM Data Register 5
0x54
read-write
n
0x0
0x0
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Control Register
0xC
read-write
n
0x0
0x0
CNTEN
PWM Counter Enable Bit\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM Counter Stop Running
0
1
PWM Counter Start Running
1
PWM_CTL
PWM_CTL
PWM Control Register
0x8
read-write
n
0x0
0x0
CMPINV
PWM Comparator Output Inverter Enable Bit\nWhen CMPINV is set to high, the PWM comparator output signals will be inversed, \nNote: Each bit control corresponding PWM channel
0
6
read-write
0
Comparator output inverter Disabled
0
1
Comparator output inverter Enabled
1
CNTMODE
PWM Counter Operation Mode\nNote: Each bit control corresponding PWM channel\nNote: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared.
16
6
read-write
0
PWM counter working as One-shot mode
0
1
PWM counter working as Auto-reload mode
1
CNTTYPE
PWM Counter Operation Aligned Type\nNote: Each bit control corresponding PWM channel
24
6
read-write
0
PWM counter operating as Edge-aligned type
0
1
PWM counter operating as Center-aligned type
1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nNote: The PWM pin will keep output no matter ICE debug mode acknowledged or not.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
GROUPEN
Group Mode Enable Bit\n
7
1
read-write
0
The signals timing of each PWM channel are independent
#0
1
Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0 and unify the signals timing of PWM_CH1, PWM_CH3 and PWM_CH5 in the same phase which is controlled by PWM_CH1
#1
OUTMODE
PWM Output Mode\nThe register controls the output mode of PWM\n
6
1
read-write
0
PWM output at independent mode
#0
1
PWM output at complementary mode
#1
PINV
PWM Output Polar Inverse Enable Bit\nThe register controls polarity state of PWM output\nNote: Each bit controls the corresponding PWM channel.
8
6
read-write
0
PWM output polar inverse Disabled
0
1
PWM output polar inverse Enabled
1
SYNCEN
Synchronous Mode Enable Bit\nNote: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive.
15
1
read-write
0
The signals timing of each PWM channel are independent
#0
1
Unify the signals timing of PWM_CH0 and PWM_CH1 in the same phase which is controlled by PWM0 and so as another two PWM pair
#1
PWM_DTCTL
PWM_DTCTL
PWM Dead-zone Control Register
0x60
read-write
n
0x0
0x0
DTCNT01
Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
0
8
read-write
DTCNT23
Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
8
8
read-write
DTCNT45
Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
16
8
read-write
DTDIV
Dead-Zone Generator Divider\n
24
2
read-write
0
Dead-zone clock equal to PWM base clock divide 1
#00
1
Dead-zone clock equal to PWM base clock divide 2
#01
2
Dead-zone clock equal to PWM base clock divide 4
#10
3
Dead-zone clock equal to PWM base clock divide 8
#11
DTEN01
Dead-Zone Enable Control for PWM Pair Of Channel 0 and Channel 1\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
28
1
read-write
0
Dead-zone insertion Disabled
#0
1
Dead-zone insertion Enabled
#1
DTEN23
Dead-Zone Enable Control for PWM Pair Of Channel 2 and Channel 3\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
29
1
read-write
0
Dead-zone insertion Disabled
#0
1
Dead-zone insertion Enabled
#1
DTEN45
Dead-Zone Enable Control for PWM Pair Of Channel 4 and Channel 5\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
30
1
read-write
0
Dead-zone insertion Disabled
#0
1
Dead-zone insertion Enabled
#1
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Capture Falling Latch Register 0
0x94
read-only
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Capture Falling Latch Register 1
0x9C
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Capture Falling Latch Register 2
0xA4
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Capture Falling Latch Register 3
0xAC
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Capture Falling Latch Register 4
0xB4
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Capture Falling Latch Register 5
0xBC
read-write
n
0x0
0x0
PWM_INTCTL
PWM_INTCTL
PWM Interrupt Control Register
0x70
read-write
n
0x0
0x0
DINTTYPE
PWM Duty Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
8
6
read-write
0
DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting
0
1
DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting
1
PINTTYPE
PWM Period Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PIF[n] will be set if PWM counter underflow
0
1
PIF[n] will be set if PWM counter matches PWM_PERIODn register
1
PWM_INTEN
PWM_INTEN
PWM Interrupt Enable Control Register
0x74
read-write
n
0x0
0x0
BRKIEN
Brake0 and Brak1 Interrupt Enable Bit\n
6
1
read-write
0
Disabling flags BFK0 and BFK1 to trigger PWM interrupt
#0
1
Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt
#1
DIEN
PWM Duty Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
8
6
read-write
0
Duty interrupt Disabled
0
1
Duty interrupt Enabled
1
FLIEN
Falling Latch Interrupt Enable Bit\nNote: Each bit controls the corresponding PWM channel.
24
6
read-write
0
Falling latch interrupt Disabled
0
1
Falling latch interrupt Enabled
1
PIEN
PWM Period Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
Period interrupt Disabled
0
1
Period interrupt Enabled
1
RLIEN
Rising Latch Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
16
6
read-write
0
Rising latch interrupt Disabled
0
1
Rising latch interrupt Enabled
1
PWM_INTSTS
PWM_INTSTS
PWM Interrupt Flag Register
0x78
read-write
n
0x0
0x0
BRKIF0
PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it.
6
1
read-write
0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#0
1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
#1
BRKIF1
PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it.
7
1
read-write
0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#0
1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
#1
BRKLK0
PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it.
14
1
read-write
0
Brake 0 state is released
#0
1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
#1
BRKSTS0
Brake 0 Status (Read Only)\n
22
1
read-only
0
PWM had been out of Brake 0 state
#0
1
PWM is in Brake 0 state
#1
BRKSTS1
Brake 1 Status (Read Only)\n
23
1
read-only
0
PWM had been out of Brake 1 state
#0
1
PWM is in Brake 1 state
#1
CFLIF
Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
24
6
read-write
0
No capture falling latch condition happened
0
1
Capture falling latch condition happened, this flag will be set to high
1
CRLIF
Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
16
6
read-write
0
No capture rising latch condition happened
0
1
Capture rising latch condition happened, this flag will be set to high
1
DIF
PWM Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMP0. Software can clear this bit by writing 1 to it.\nNote: If CMP is equal to PERIOD, this flag is not working in edge-aligned type selection.
8
6
read-write
PIF
PWM Period Interrupt Flag\nThis bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) ). Software can write 1 to clear this bit to 0.
0
6
read-write
PWM_MSK
PWM_MSK
PWM Mask Data Register
0x5C
read-write
n
0x0
0x0
MSKDAT
PWM Mask Data Bit:\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled.\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
Output logic low to PWMn
0
1
Output logic high to PWMn
1
PWM_MSKEN
PWM_MSKEN
PWM Mask Control Register
0x58
read-write
n
0x0
0x0
MSKEN
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with MSKDAT data. \nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM output signal is non-masked
0
1
PWM output signal is masked and output with MSKDAT data
1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x10
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nPERIOD determines the PWM period.\nNote1: Any write to PERIOD will take effect in next PWM cycle.\nNote2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable.\nNote3: When PERIOD value is set to 0, PWM output is always high.
0
16
read-write
PWM_PERIOD1
PWM_PERIOD1
PWM Period Register 1
0x14
read-write
n
0x0
0x0
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x18
read-write
n
0x0
0x0
PWM_PERIOD3
PWM_PERIOD3
PWM Period Register 3
0x1C
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x20
read-write
n
0x0
0x0
PWM_PERIOD5
PWM_PERIOD5
PWM Period Register 5
0x24
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Control Register
0x7C
read-write
n
0x0
0x0
POEN
PWM Pin Output Enable Bit\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM pin at tri-state
0
1
PWM pin in output mode
1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Capture Rising Latch Register 0
0x90
read-only
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Capture Rising Latch Register 1
0x98
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Capture Rising Latch Register 2
0xA0
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Capture Rising Latch Register 3
0xA8
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Capture Rising Latch Register 4
0xB0
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Capture Rising Latch Register 5
0xB8
read-write
n
0x0
0x0
PWM_SBS0
PWM_SBS0
PWM0 Synchronous Busy Status Register
0xE0
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (PWM_CTL[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (PWM_CTL[16]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS1
PWM_SBS1
PWM1 Synchronous Busy Status Register
0xE4
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 counter operation mode CNTMOD (PWM_CTL [17]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD1/PWM_CMPDAT1/ PWM_CLKPSC or switch PWM1 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 operation mode CNTMOD (PWM_CTL [17]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS2
PWM_SBS2
PWM2 Synchronous Busy Status Register
0xE8
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 counter operation mode CNTMOD (PWM_CTL [18]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD2/PWM_CMPDAT2/ PWM_CLKPSC or switch PWM2 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 operation mode CNTMOD (PWM_CTL [18]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS3
PWM_SBS3
PWM3 Synchronous Busy Status Register
0xEC
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 counter operation mode CNTMOD (PWM_CTL [19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD3/PWM_CMPDAT3/ PWM_CLKPSC or switch PWM3 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 operation mode CNTMOD (PWM_CTL [19]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS4
PWM_SBS4
PWM4 Synchronous Busy Status Register
0xF0
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 counter operation mode CNTMOD (PWM_CTL [20]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD4/PWM_CMPDAT4/ PWM_CLKPSC or switch PWM4 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 operation mode CNTMOD (PWM_CTL [20]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_SBS5
PWM_SBS5
PWM5 Synchronous Busy Status Register
0xF4
read-only
n
0x0
0x0
SYNCBUSY
PWM Synchronous Busy\nWhen software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 counter operation mode CNTMOD (PWM_CTL [21]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD5/PWM_CMPDAT5/ PWM_CLKPSC or switch PWM5 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 operation mode CNTMOD (PWM_CTL [21]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
PWM_TRGADCSTS
PWM_TRGADCSTS
PWM Trigger ADC Status Register
0x68
read-write
n
0x0
0x0
CTRGF
PWM Center Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
8
6
read-write
FTRGF
PWM Falling Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
16
6
read-write
PTRGF
PWM Period Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
0
6
read-write
RTRGF
PWM Rising Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
24
6
read-write
PWM_TRGADCTL
PWM_TRGADCTL
PWM Trigger Control Register
0x64
read-write
n
0x0
0x0
CTRGEN
PWM Center Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
8
6
read-write
0
PWM center point trigger ADC function Disabled
0
1
PWM center point trigger ADC function Enabled
1
FTRGEN
PWM Falling Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
16
6
read-write
0
PWM falling edge point trigger ADC function Disabled
0
1
PWM falling edge point trigger ADC function Enabled
1
PTRGEN
PWM Period Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
0
6
read-write
0
PWM period point trigger ADC function Disabled
0
1
PWM period point trigger ADC function Enabled
1
RTRGEN
PWM Rising Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
24
6
read-write
0
PWM rising edge point trigger ADC function Disabled
0
1
PWM rising edge point trigger ADC function Enabled
1
QEI0
QEI Register Map
QEI
0x0
0x0
0x10
registers
n
0x14
0x8
registers
n
0x2C
0x4
registers
n
QEI_CNT
QEI_CNT
QEI Pulse Counter
0x0
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter\nA 32-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:\n
0
32
read-write
QEI_CNTCMP
QEI_CNTCMP
QEI Pulse Counter Compare Register
0xC
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter Compare\n
0
32
read-write
QEI_CNTHOLD
QEI_CNTHOLD
QEI Pulse Counter Hold Register
0x4
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIx_CTL[24]) goes from low to high, the QEI_CNT value is copied into QEI_CNTHOLD register.
0
32
read-write
QEI_CNTLATCH
QEI_CNTLATCH
QEI Pulse Counter Index Latch Register
0x8
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set, the QEI_CNT value is copied into QEI_CNTLATCH register.
0
32
read-write
QEI_CNTMAX
QEI_CNTMAX
QEI Pre-set Maximum Count Register
0x14
read-write
n
0x0
0x0
VAL
Quadrature Encoder Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode.
0
32
read-write
QEI_CTL
QEI_CTL
QEI Controller Control Register
0x18
read-write
n
0x0
0x0
CHAEN
QEA Input To QEI Controller Enable Bit\n
4
1
read-write
0
QEA input to QEI Controller Disabled
#0
1
QEA input to QEI Controller Enabled
#1
CHAINV
Inverse QEA Input Polarity\n
12
1
read-write
0
Not inverse QEA input polarity
#0
1
QEA input polarity is inversed to QEI controller
#1
CHBEN
QEB Input To QEI Controller Enable Bit\n
5
1
read-write
0
QEB input to QEI Controller Disabled
#0
1
QEB input to QEI Controller Enabled
#1
CHBINV
Inverse QEB Input Polarity\n
13
1
read-write
0
Not inverse QEB input polarity
#0
1
QEB input polarity is inversed to QEI controller
#1
CMPEN
The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set. \n
28
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIEN
CMPF Trigger QEI Interrupt Enable Bit\n
18
1
read-write
0
CMPF can trigger QEI controller interrupt Disabled
#0
1
CMPF can trigger QEI controller interrupt Enabled
#1
DIRIEN
DIRCHGF Trigger QEI Interrupt Enable Bit\n
17
1
read-write
0
DIRCHGF can trigger QEI controller interrupt Disabled
#0
1
DIRCHGF can trigger QEI controller interrupt Enabled
#1
HOLDCNT
Hold QEI_CNT Control
When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHOLD. This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
24
1
read-write
0
No operation
#0
1
QEI_CNT content is captured and stored in QEI_CNTHOLD
#1
HOLDTMR0
Hold QEI_CNT By Timer 0 \n
20
1
read-write
0
TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1
#1
HOLDTMR1
Hold QEI_CNT By Timer 1 \n
21
1
read-write
0
TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1
#1
HOLDTMR2
Hold QEI_CNT By Timer 2\n
22
1
read-write
0
TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1
#1
HOLDTMR3
Hold QEI_CNT By Timer 3 \n
23
1
read-write
0
TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1
#1
IDXEN
IDX Input To QEI Controller Enable Bit\n
6
1
read-write
0
IDX input to QEI Controller Disabled
#0
1
IDX input to QEI Controller Enabled
#1
IDXIEN
IDXF Trigger QEI Interrupt Enable Bit\n
19
1
read-write
0
The IDXF can trigger QEI interrupt Disabled
#0
1
The IDXF can trigger QEI interrupt Enabled
#1
IDXINV
Inverse IDX Input Polarity\n
14
1
read-write
0
Not inverse IDX input polarity
#0
1
IDX input polarity is inversed to QEI controller
#1
IDXLATEN
Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.\n
25
1
read-write
0
The index signal latch QEI counter function Disabled
#0
1
The index signal latch QEI counter function Enabled
#1
IDXRLDEN
Index Trigger QEI_CNT Reload Enable Bit\n
27
1
read-write
0
Reload function Disabled
#0
1
QEI_CNT re-initialized by Index signal Enabled
#1
MODE
QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes.\n
8
2
read-write
0
X4 Free-counting Mode
#00
1
X2 Free-counting Mode
#01
2
X4 Compare-counting Mode
#10
3
X2 Compare-counting Mode
#11
NFCLKSEL
Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock .\n
0
2
read-write
0
QEI_CLK
#00
1
QEI_CLK/2
#01
2
QEI_CLK/4
#10
3
QEI_CLK/16
#11
NFDIS
QEI Controller Input Noise Filter Disable Bit\n
3
1
read-write
0
The noise filter of QEI controller Enabled
#0
1
The noise filter of QEI controller Disabled
#1
OVUNIEN
OVUNF Trigger QEI Interrupt Enable Bit\n
16
1
read-write
0
OVUNF can trigger QEI controller interrupt Disabled
#0
1
OVUNF can trigger QEI controller interrupt Enabled
#1
QEIEN
Quadrature Encoder Interface Controller Enable Bit\n
29
1
read-write
0
QEI controller function Disabled
#0
1
QEI controller function Enabled
#1
QEI_STATUS
QEI_STATUS
QEI Controller Status Register
0x2C
read-write
n
0x0
0x0
CMPF
Compare-Match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it.
1
1
read-write
0
QEI counter does not match with QEI_CNTCMP value
#0
1
QEI counter counts to the same as QEI_CNTCMP value
#1
DIRCHGF
Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it.
3
1
read-write
0
No change in QEI counter counting direction
#0
1
QEI counter counting direction is changed
#1
DIRF
QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
8
1
read-write
0
QEI Counter is in down-counting
#0
1
QEI Counter is in up-counting
#1
IDXF
IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it.
0
1
read-write
0
No rising edge detected on signal CHX
#0
1
A rising edge occurs on signal CHX
#1
OVUNF
QEI Counter Overflow Or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_CNTMAX value to zero in compare-counting mode. Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_CNTMAX.\nNote: This bit is only cleared by writing 1 to it.
2
1
read-write
0
No overflow or underflow occurs in QEI counter
#0
1
QEI counter occurs counting overflow or underflow
#1
QEI1
QEI Register Map
QEI
0x0
0x0
0x10
registers
n
0x14
0x8
registers
n
0x2C
0x4
registers
n
QEI_CNT
QEI_CNT
QEI Pulse Counter
0x0
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter\nA 32-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:\n
0
32
read-write
QEI_CNTCMP
QEI_CNTCMP
QEI Pulse Counter Compare Register
0xC
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter Compare\n
0
32
read-write
QEI_CNTHOLD
QEI_CNTHOLD
QEI Pulse Counter Hold Register
0x4
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIx_CTL[24]) goes from low to high, the QEI_CNT value is copied into QEI_CNTHOLD register.
0
32
read-write
QEI_CNTLATCH
QEI_CNTLATCH
QEI Pulse Counter Index Latch Register
0x8
read-write
n
0x0
0x0
VAL
Quadrature Encoder Pulse Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set, the QEI_CNT value is copied into QEI_CNTLATCH register.
0
32
read-write
QEI_CNTMAX
QEI_CNTMAX
QEI Pre-set Maximum Count Register
0x14
read-write
n
0x0
0x0
VAL
Quadrature Encoder Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode.
0
32
read-write
QEI_CTL
QEI_CTL
QEI Controller Control Register
0x18
read-write
n
0x0
0x0
CHAEN
QEA Input To QEI Controller Enable Bit\n
4
1
read-write
0
QEA input to QEI Controller Disabled
#0
1
QEA input to QEI Controller Enabled
#1
CHAINV
Inverse QEA Input Polarity\n
12
1
read-write
0
Not inverse QEA input polarity
#0
1
QEA input polarity is inversed to QEI controller
#1
CHBEN
QEB Input To QEI Controller Enable Bit\n
5
1
read-write
0
QEB input to QEI Controller Disabled
#0
1
QEB input to QEI Controller Enabled
#1
CHBINV
Inverse QEB Input Polarity\n
13
1
read-write
0
Not inverse QEB input polarity
#0
1
QEB input polarity is inversed to QEI controller
#1
CMPEN
The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set. \n
28
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIEN
CMPF Trigger QEI Interrupt Enable Bit\n
18
1
read-write
0
CMPF can trigger QEI controller interrupt Disabled
#0
1
CMPF can trigger QEI controller interrupt Enabled
#1
DIRIEN
DIRCHGF Trigger QEI Interrupt Enable Bit\n
17
1
read-write
0
DIRCHGF can trigger QEI controller interrupt Disabled
#0
1
DIRCHGF can trigger QEI controller interrupt Enabled
#1
HOLDCNT
Hold QEI_CNT Control
When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHOLD. This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
24
1
read-write
0
No operation
#0
1
QEI_CNT content is captured and stored in QEI_CNTHOLD
#1
HOLDTMR0
Hold QEI_CNT By Timer 0 \n
20
1
read-write
0
TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1
#1
HOLDTMR1
Hold QEI_CNT By Timer 1 \n
21
1
read-write
0
TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1
#1
HOLDTMR2
Hold QEI_CNT By Timer 2\n
22
1
read-write
0
TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1
#1
HOLDTMR3
Hold QEI_CNT By Timer 3 \n
23
1
read-write
0
TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT
#0
1
A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1
#1
IDXEN
IDX Input To QEI Controller Enable Bit\n
6
1
read-write
0
IDX input to QEI Controller Disabled
#0
1
IDX input to QEI Controller Enabled
#1
IDXIEN
IDXF Trigger QEI Interrupt Enable Bit\n
19
1
read-write
0
The IDXF can trigger QEI interrupt Disabled
#0
1
The IDXF can trigger QEI interrupt Enabled
#1
IDXINV
Inverse IDX Input Polarity\n
14
1
read-write
0
Not inverse IDX input polarity
#0
1
IDX input polarity is inversed to QEI controller
#1
IDXLATEN
Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.\n
25
1
read-write
0
The index signal latch QEI counter function Disabled
#0
1
The index signal latch QEI counter function Enabled
#1
IDXRLDEN
Index Trigger QEI_CNT Reload Enable Bit\n
27
1
read-write
0
Reload function Disabled
#0
1
QEI_CNT re-initialized by Index signal Enabled
#1
MODE
QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes.\n
8
2
read-write
0
X4 Free-counting Mode
#00
1
X2 Free-counting Mode
#01
2
X4 Compare-counting Mode
#10
3
X2 Compare-counting Mode
#11
NFCLKSEL
Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock .\n
0
2
read-write
0
QEI_CLK
#00
1
QEI_CLK/2
#01
2
QEI_CLK/4
#10
3
QEI_CLK/16
#11
NFDIS
QEI Controller Input Noise Filter Disable Bit\n
3
1
read-write
0
The noise filter of QEI controller Enabled
#0
1
The noise filter of QEI controller Disabled
#1
OVUNIEN
OVUNF Trigger QEI Interrupt Enable Bit\n
16
1
read-write
0
OVUNF can trigger QEI controller interrupt Disabled
#0
1
OVUNF can trigger QEI controller interrupt Enabled
#1
QEIEN
Quadrature Encoder Interface Controller Enable Bit\n
29
1
read-write
0
QEI controller function Disabled
#0
1
QEI controller function Enabled
#1
QEI_STATUS
QEI_STATUS
QEI Controller Status Register
0x2C
read-write
n
0x0
0x0
CMPF
Compare-Match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it.
1
1
read-write
0
QEI counter does not match with QEI_CNTCMP value
#0
1
QEI counter counts to the same as QEI_CNTCMP value
#1
DIRCHGF
Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it.
3
1
read-write
0
No change in QEI counter counting direction
#0
1
QEI counter counting direction is changed
#1
DIRF
QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
8
1
read-write
0
QEI Counter is in down-counting
#0
1
QEI Counter is in up-counting
#1
IDXF
IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it.
0
1
read-write
0
No rising edge detected on signal CHX
#0
1
A rising edge occurs on signal CHX
#1
OVUNF
QEI Counter Overflow Or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_CNTMAX value to zero in compare-counting mode. Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_CNTMAX.\nNote: This bit is only cleared by writing 1 to it.
2
1
read-write
0
No overflow or underflow occurs in QEI counter
#0
1
QEI counter occurs counting overflow or underflow
#1
RTC
RTC Register Map
RTC
0x0
0x0
0x30
registers
n
0x110
0x8
registers
n
0x124
0x10
registers
n
0x140
0x8
registers
n
0x3C
0x64
registers
n
CAL
RTC_CAL
Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
Calendar Alarm Register
0x20
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CAMSK
RTC_CAMSK
Calendar Alarm MASK Register
0x144
read-write
n
0x0
0x0
MDAY
Mask 1-Day Calendar Digit of Alarm Setting (0~9)
0
1
read-write
MMON
Mask 1-Month Calendar Digit of Alarm Setting (0~9)
2
1
read-write
MTENDAY
Mask 10-Day Calendar Digit of Alarm Setting (0~3)
1
1
read-write
MTENMON
Mask 10-Month Calendar Digit of Alarm Setting (0~1)
3
1
read-write
MTENYEAR
Mask 10-Year Calendar Digit of Alarm Setting (0~9)
5
1
read-write
MYEAR
Mask 1-Year Calendar Digit of Alarm Setting (0~9)
4
1
read-write
CLKFMT
RTC_CLKFMT
Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24HEN
24-Hour / 12-Hour Time Scale Selection\n
0
1
read-write
0
12-hour time scale with AM and PM indication selected
#0
1
24-hour time scale selected
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FRACTION
Fraction Part\nNote: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
0
6
read-write
INTEGER
Integer Part\n
8
4
read-write
INIT
RTC_INIT
RTC Initiation Register
0x0
read-write
n
0x0
0x0
INIT
RTC Initiation
When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIT is a write-only field and read value will be always 0 .
1
31
read-write
INIT_Active
RTC Active Status (Read Only)\n
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable Bit\n
0
1
read-write
0
RTC Alarm Interrupt Disabled
#0
1
RTC Alarm Interrupt Enabled
#1
TICKIEN
Time Tick Interrupt Enable Bit\n
1
1
read-write
0
RTC Time Tick Interrupt Disabled
#0
1
RTC Time Tick Interrupt Enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Indicator Register
0x2C
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag\nWhen RTC real time counters RTC_TIME and RTC_CAL reach the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled (ALMIEN (RTC_INTEN(0)) is set to 1. Chip will also be waken up if RTC Alarm Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: This bit can be cleared by writing 1 to it.
0
1
read-write
TICKIF
RTC Time Tick Interrupt Flag\nWhen RTC Time Tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled (TICKIEN (RTC_INTEN[1])) is set to 1. Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: This bit can be cleared by writing 1 to it.
1
1
read-write
LEAPYEAR
RTC_LEAPYEAR
Leap Year Indication Register
0x24
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indicator (Read Only)\n
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
LXTIPCTL
RTC_LXTIPCTL
32K Input Pin I/O Mode Control
0x12C
read-write
n
0x0
0x0
LXTOPCTL
RTC_LXTOPCTL
32K Output Pin I/O Mode Control
0x130
read-write
n
0x0
0x0
RWEN
RTC_RWEN
RTC Access Enable Register
0x4
read-write
n
0x0
0x0
RWEN
RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
0
16
write-only
RWENF
RTC Register Access Enable Flag (Read Only)\n
16
1
read-only
0
RTC register read/write Disabled
#0
1
RTC register read/write Enabled
#1
SPR0
RTC_SPR0
RTC Spare Register 0
0x40
read-write
n
0x0
0x0
SPARE
SPARE Bits\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to SPARE register, software should write 0xA965 to RTC_RWEN to make sure register read/write enabled.
0
32
read-write
SPR1
RTC_SPR1
RTC Spare Register 1
0x44
read-write
n
0x0
0x0
SPR10
RTC_SPR10
RTC Spare Register 10
0x68
read-write
n
0x0
0x0
SPR11
RTC_SPR11
RTC Spare Register 11
0x6C
read-write
n
0x0
0x0
SPR12
RTC_SPR12
RTC Spare Register 12
0x70
read-write
n
0x0
0x0
SPR13
RTC_SPR13
RTC Spare Register 13
0x74
read-write
n
0x0
0x0
SPR14
RTC_SPR14
RTC Spare Register 14
0x78
read-write
n
0x0
0x0
SPR15
RTC_SPR15
RTC Spare Register 15
0x7C
read-write
n
0x0
0x0
SPR16
RTC_SPR16
RTC Spare Register 16
0x80
read-write
n
0x0
0x0
SPR17
RTC_SPR17
RTC Spare Register 17
0x84
read-write
n
0x0
0x0
SPR18
RTC_SPR18
RTC Spare Register 18
0x88
read-write
n
0x0
0x0
SPR19
RTC_SPR19
RTC Spare Register 19
0x8C
read-write
n
0x0
0x0
SPR2
RTC_SPR2
RTC Spare Register 2
0x48
read-write
n
0x0
0x0
SPR20
RTC_SPR20
RTC Spare Register 20
0x90
read-write
n
0x0
0x0
SPR21
RTC_SPR21
RTC Spare Register 21
0x94
read-write
n
0x0
0x0
SPR22
RTC_SPR22
RTC Spare Register 22
0x98
read-write
n
0x0
0x0
SPR23
RTC_SPR23
RTC Spare Register 23
0x9C
read-write
n
0x0
0x0
SPR3
RTC_SPR3
RTC Spare Register 3
0x4C
read-write
n
0x0
0x0
SPR4
RTC_SPR4
RTC Spare Register 4
0x50
read-write
n
0x0
0x0
SPR5
RTC_SPR5
RTC Spare Register 5
0x54
read-write
n
0x0
0x0
SPR6
RTC_SPR6
RTC Spare Register 6
0x58
read-write
n
0x0
0x0
SPR7
RTC_SPR7
RTC Spare Register 7
0x5C
read-write
n
0x0
0x0
SPR8
RTC_SPR8
RTC Spare Register 8
0x60
read-write
n
0x0
0x0
SPR9
RTC_SPR9
RTC Spare Register 9
0x64
read-write
n
0x0
0x0
SPRCTL
RTC_SPRCTL
RTC Spare Functional Control Register
0x3C
-1
read-write
n
0x0
0x0
SPRRWEN
SPR Register Enable Bit\nThis bit controls the spare register to be enabled or not.\n
2
1
read-write
0
Spare register Disabled and RTC_SPR0 ~ RTC_SPR23 cannot be accessed
#0
1
Spare register Enabled and RTC_SPR0 ~ RTC_SPR23 can be accessed
#1
SPRRWRDY
SPR Register Ready\nThis bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are ready to be accessed.\nAfter CPU writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23, polling this bit to check if these registers are updated done is necessary.\nThis bit is read only and any write to it won't take any effect.\n
7
1
read-write
0
RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 updating is in progress
#0
1
RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are updated done and ready to be accessed
#1
TALM
RTC_TALM
Time Alarm Register
0x1C
read-write
n
0x0
0x0
HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10-Hour Time Digit of Alarm Setting (0~2)
20
2
read-write
TENMIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TAMP0PCTL
RTC_TAMP0PCTL
TAMPER0 Pin I/O Mode Control
0x124
-1
read-write
n
0x0
0x0
DINOFF
Off Digital\n
4
1
read-write
0
Off digital Disabled
#0
1
Off digital Enabled
#1
OUTEN
Output Enable Bit\n
1
1
read-write
0
Output Enabled
#0
1
Output Disabled
#1
OUTLV
Output Level\n
0
1
read-write
0
Low
#0
1
High
#1
TRIEN
Tri-State\n
2
1
read-write
0
Tri-state Disabled
#0
1
Tri-state Enabled
#1
TYPE
Type\n
3
1
read-write
0
Input Schmitt Trigger function Disabled
#0
1
Input Schmitt Trigger function Enabled
#1
TAMP1PCTL
RTC_TAMP1PCTL
TAMPER1 Pin I/O Mode Control
0x128
read-write
n
0x0
0x0
TAMPCTL
RTC_TAMPCTL
Tamper Control Register
0x110
read-write
n
0x0
0x0
DESTROYEN
Destroy Spare Register Enable Bit\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TAMPDBEN0
Tamper0 De-Bounce Enable Bit\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
TAMPDBEN1
Tamper1 De-Bounce Enable Bit\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
TAMPEN0
Tamper0 Detect Enable Bit\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TAMPEN1
Tamper1 Detect Enable Bit\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
TAMPLV0
Tamper0 Level \n
6
1
read-write
0
Low
#0
1
High
#1
TAMPLV1
Tamper1 Level \n
7
1
read-write
0
Low
#0
1
High
#1
TIEN
Tamper Interrupt Enable Bit\n
0
1
read-write
0
Tamper interrupt Disabled
#0
1
Tamper interrupt Enabled
#1
TAMPSTS
RTC_TAMPSTS
Tamper Status Register
0x114
read-write
n
0x0
0x0
TAMPSTS0
Tamper0 Sense Flag\nNote: Write 1 to clear it
0
1
read-write
0
No invasion
#0
1
Tamper0 detect invasion
#1
TAMPSTS1
Tamper1 Sense Flag \nNote: Write 1 to clear it
1
1
read-write
0
No invasion
#0
1
Tamper1 detect invasion
#1
TAMSK
RTC_TAMSK
Time Alarm MASK Register
0x140
read-write
n
0x0
0x0
MHR
Mask 1-Hour Time Digit of Alarm Setting (0~9)
4
1
read-write
MMIN
Mask 1-Min Time Digit of Alarm Setting (0~9)
2
1
read-write
MSEC
Mask 1-Sec Time Digit of Alarm Setting (0~9)
0
1
read-write
MTENHR
Mask 10-Hour Time Digit of Alarm Setting (0~2)
5
1
read-write
MTENMIN
Mask 10-Min Time Digit of Alarm Setting (0~5)
3
1
read-write
MTENSEC
Mask 10-Sec Time Digit of Alarm Setting (0~5)
1
1
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TICKSEL
Time Tick Bits\n
0
3
read-write
TIME
RTC_TIME
Time Loading Register
0xC
read-write
n
0x0
0x0
HR
1-Hour Time Digit (0~9)
16
4
read-write
MIN
1-Min Time Digit (0~9)
8
4
read-write
SEC
1-Sec Time Digit (0~9)
0
4
read-write
TENHR
10-Hour Time Digit (0~2)
20
2
read-write
TENMIN
10-Min Time Digit (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day Of The Week Bits\n
0
3
read-write
SC0
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
11
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
#11
CDLV
Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
26
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RXRTYEN
\n
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SCEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
#11
TXOFF
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive and Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
CMPEN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETURDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIF
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGTIF
\n
6
1
read-only
CDIF
Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INITIF
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RBTOIF
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
9
1
read-only
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
1
1
read-only
TERRIF
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0IF
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1IF
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2IF
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATSTS
\n
16
1
read-write
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
PWREN
SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
PWRINV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
11
1
read-write
PWRSTS
\n
17
1
read-write
0
SC_PWR pin to low
#0
1
SC_PWR pin to high
#1
RSTSTS
SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
18
1
read-write
0
SC_RST pin is low
#0
1
SC_RST pin is high
#1
SCDOOUT
SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SCDOSTS pin to low
#0
1
Drive SCDOSTS pin to high
#1
SCRST
SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SCRST pin to low.\nSCRST pin status is low
#0
1
Drive SCRST pin to high.\nSCRST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Status Register
0x20
-1
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
CDPINSTS
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
13
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CINSERT
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
12
1
read-only
0
No effect.1 = Card insert
#0
CREMOVE
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
11
1
read-only
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
PEF
Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RXACT
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RXEMPTY
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RXFULL
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RXOV
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RXOVERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
22
1
read-only
RXPOINT
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
16
2
read-only
RXRERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
21
1
read-only
TXACT
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
9
1
read-only
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TXOV
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TXOVERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TXPOINT
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
2
read-only
TXRERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
OPMODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
24
4
read-write
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
24
4
read-write
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
24
4
read-write
SC_TMRDAT0
SC_TMRDAT0
SC Timer 0 Current Data Register
0x38
-1
read-only
n
0x0
0x0
CNT0
Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TMRDAT1_2
SC_TMRDAT1_2
SC Timer 1 and 2 Current Data Register
0x3C
-1
read-only
n
0x0
0x0
CNT1
Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
CNT2
Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Data Length\nNote: In smart card mode, this WLS must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
SC1
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
11
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
#11
CDLV
Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
26
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RXRTYEN
\n
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SCEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
#11
TXOFF
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive and Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
CMPEN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETURDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIF
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGTIF
\n
6
1
read-only
CDIF
Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INITIF
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RBTOIF
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
9
1
read-only
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
1
1
read-only
TERRIF
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0IF
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1IF
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2IF
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATSTS
\n
16
1
read-write
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
PWREN
SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
PWRINV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
11
1
read-write
PWRSTS
\n
17
1
read-write
0
SC_PWR pin to low
#0
1
SC_PWR pin to high
#1
RSTSTS
SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
18
1
read-write
0
SC_RST pin is low
#0
1
SC_RST pin is high
#1
SCDOOUT
SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SCDOSTS pin to low
#0
1
Drive SCDOSTS pin to high
#1
SCRST
SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SCRST pin to low.\nSCRST pin status is low
#0
1
Drive SCRST pin to high.\nSCRST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Status Register
0x20
-1
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
CDPINSTS
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
13
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CINSERT
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
12
1
read-only
0
No effect.1 = Card insert
#0
CREMOVE
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
11
1
read-only
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
PEF
Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RXACT
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RXEMPTY
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RXFULL
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RXOV
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RXOVERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
22
1
read-only
RXPOINT
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
16
2
read-only
RXRERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
21
1
read-only
TXACT
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
9
1
read-only
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TXOV
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TXOVERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TXPOINT
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
2
read-only
TXRERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
OPMODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
24
4
read-write
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
24
4
read-write
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
24
4
read-write
SC_TMRDAT0
SC_TMRDAT0
SC Timer 0 Current Data Register
0x38
-1
read-only
n
0x0
0x0
CNT0
Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TMRDAT1_2
SC_TMRDAT1_2
SC Timer 1 and 2 Current Data Register
0x3C
-1
read-only
n
0x0
0x0
CNT1
Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
CNT2
Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Data Length\nNote: In smart card mode, this WLS must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
SC2
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
11
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
#11
CDLV
Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
26
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RXRTYEN
\n
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SCEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
#11
TXOFF
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive and Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
CMPEN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETURDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIF
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGTIF
\n
6
1
read-only
CDIF
Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INITIF
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RBTOIF
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
9
1
read-only
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
1
1
read-only
TERRIF
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0IF
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1IF
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2IF
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATSTS
\n
16
1
read-write
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
PWREN
SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
PWRINV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
11
1
read-write
PWRSTS
\n
17
1
read-write
0
SC_PWR pin to low
#0
1
SC_PWR pin to high
#1
RSTSTS
SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
18
1
read-write
0
SC_RST pin is low
#0
1
SC_RST pin is high
#1
SCDOOUT
SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SCDOSTS pin to low
#0
1
Drive SCDOSTS pin to high
#1
SCRST
SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SCRST pin to low.\nSCRST pin status is low
#0
1
Drive SCRST pin to high.\nSCRST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Status Register
0x20
-1
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
CDPINSTS
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
13
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CINSERT
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
12
1
read-only
0
No effect.1 = Card insert
#0
CREMOVE
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
11
1
read-only
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
PEF
Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RXACT
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RXEMPTY
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RXFULL
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RXOV
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RXOVERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
22
1
read-only
RXPOINT
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
16
2
read-only
RXRERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
21
1
read-only
TXACT
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
9
1
read-only
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TXOV
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TXOVERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TXPOINT
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
2
read-only
TXRERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
OPMODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
24
4
read-write
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
24
4
read-write
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
24
4
read-write
SC_TMRDAT0
SC_TMRDAT0
SC Timer 0 Current Data Register
0x38
-1
read-only
n
0x0
0x0
CNT0
Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TMRDAT1_2
SC_TMRDAT1_2
SC Timer 1 and 2 Current Data Register
0x3C
-1
read-only
n
0x0
0x0
CNT1
Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
CNT2
Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Data Length\nNote: In smart card mode, this WLS must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
SC3
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
11
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
#11
CDLV
Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
26
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RXRTYEN
\n
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SCEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
#11
TXOFF
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive and Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
CMPEN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETURDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIF
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGTIF
\n
6
1
read-only
CDIF
Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INITIF
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RBTOIF
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
9
1
read-only
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
1
1
read-only
TERRIF
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0IF
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1IF
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2IF
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATSTS
\n
16
1
read-write
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
PWREN
SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
PWRINV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
11
1
read-write
PWRSTS
\n
17
1
read-write
0
SC_PWR pin to low
#0
1
SC_PWR pin to high
#1
RSTSTS
SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
18
1
read-write
0
SC_RST pin is low
#0
1
SC_RST pin is high
#1
SCDOOUT
SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SCDOSTS pin to low
#0
1
Drive SCDOSTS pin to high
#1
SCRST
SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SCRST pin to low.\nSCRST pin status is low
#0
1
Drive SCRST pin to high.\nSCRST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Status Register
0x20
-1
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
CDPINSTS
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
13
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CINSERT
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
12
1
read-only
0
No effect.1 = Card insert
#0
CREMOVE
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
11
1
read-only
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
PEF
Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RXACT
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RXEMPTY
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RXFULL
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RXOV
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RXOVERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
22
1
read-only
RXPOINT
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
16
2
read-only
RXRERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
21
1
read-only
TXACT
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
9
1
read-only
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TXOV
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TXOVERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TXPOINT
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
2
read-only
TXRERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
OPMODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
24
4
read-write
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
24
4
read-write
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
24
4
read-write
SC_TMRDAT0
SC_TMRDAT0
SC Timer 0 Current Data Register
0x38
-1
read-only
n
0x0
0x0
CNT0
Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TMRDAT1_2
SC_TMRDAT1_2
SC Timer 1 and 2 Current Data Register
0x3C
-1
read-only
n
0x0
0x0
CNT1
Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
CNT2
Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Data Length\nNote: In smart card mode, this WLS must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
SC4
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
11
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
#11
CDLV
Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
26
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RXRTYEN
\n
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SCEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
#11
TXOFF
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive and Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
CMPEN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETURDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIF
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGTIF
\n
6
1
read-only
CDIF
Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INITIF
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RBTOIF
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
9
1
read-only
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
1
1
read-only
TERRIF
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0IF
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1IF
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2IF
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATSTS
\n
16
1
read-write
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
PWREN
SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
PWRINV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
11
1
read-write
PWRSTS
\n
17
1
read-write
0
SC_PWR pin to low
#0
1
SC_PWR pin to high
#1
RSTSTS
SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
18
1
read-write
0
SC_RST pin is low
#0
1
SC_RST pin is high
#1
SCDOOUT
SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SCDOSTS pin to low
#0
1
Drive SCDOSTS pin to high
#1
SCRST
SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SCRST pin to low.\nSCRST pin status is low
#0
1
Drive SCRST pin to high.\nSCRST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Status Register
0x20
-1
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
CDPINSTS
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
13
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CINSERT
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
12
1
read-only
0
No effect.1 = Card insert
#0
CREMOVE
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
11
1
read-only
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
PEF
Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RXACT
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RXEMPTY
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RXFULL
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RXOV
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RXOVERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
22
1
read-only
RXPOINT
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
16
2
read-only
RXRERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
21
1
read-only
TXACT
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
9
1
read-only
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TXOV
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TXOVERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TXPOINT
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
2
read-only
TXRERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
OPMODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
24
4
read-write
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
24
4
read-write
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
24
4
read-write
SC_TMRDAT0
SC_TMRDAT0
SC Timer 0 Current Data Register
0x38
-1
read-only
n
0x0
0x0
CNT0
Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TMRDAT1_2
SC_TMRDAT1_2
SC Timer 1 and 2 Current Data Register
0x3C
-1
read-only
n
0x0
0x0
CNT1
Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
CNT2
Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Data Length\nNote: In smart card mode, this WLS must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
SC5
SC Register Map
SC
0x0
0x0
0x40
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
11
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\n
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#00
1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#01
2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#10
3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
#11
CDLV
Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
26
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
16
3
read-write
RXRTYEN
\n
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
6
2
read-write
0
INTR_RDA Trigger Level with 01 Bytes
#00
1
INTR_RDA Trigger Level with 02 Bytes
#01
2
INTR_RDA Trigger Level with 03 Bytes
#10
3
Reserved
#11
SCEN
SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
30
1
read-write
0
synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Selection \n
13
2
read-write
0
All internal timer function Disabled
#00
1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#01
2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#10
3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
#11
TXOFF
TX Transition Disable Bit\n
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive and Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
CMPEN
Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETURDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIF
Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
10
1
read-only
BGTIF
\n
6
1
read-only
CDIF
Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
7
1
read-only
INITIF
Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RBTOIF
Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
9
1
read-only
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
0
1
read-only
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
1
1
read-only
TERRIF
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0IF
Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1IF
Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2IF
Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATSTS
\n
16
1
read-write
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
PWREN
SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
PWRINV
SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
11
1
read-write
PWRSTS
\n
17
1
read-write
0
SC_PWR pin to low
#0
1
SC_PWR pin to high
#1
RSTSTS
SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
18
1
read-write
0
SC_RST pin is low
#0
1
SC_RST pin is high
#1
SCDOOUT
SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SCDOSTS pin to low
#0
1
Drive SCDOSTS pin to high
#1
SCRST
SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SCRST pin to low.\nSCRST pin status is low
#0
1
Drive SCRST pin to high.\nSCRST pin status is high
#1
SYNC
SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
30
1
read-write
0
Synchronizing is completion, user can write new data to SC_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Status Register
0x20
-1
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
6
1
read-only
CDPINSTS
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
13
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CINSERT
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
12
1
read-only
0
No effect.1 = Card insert
#0
CREMOVE
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
11
1
read-only
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
5
1
read-only
PEF
Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
4
1
read-only
RXACT
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RXEMPTY
Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
1
1
read-only
RXFULL
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RXOV
RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RXOVERR
Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
22
1
read-only
RXPOINT
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
16
2
read-only
RXRERR
Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
21
1
read-only
TXACT
Transmit In Active Status Flag (Read Only)\n
31
1
read-only
0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#0
1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
9
1
read-only
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TXOV
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TXOVERR
Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TXPOINT
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
2
read-only
TXRERR
Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
24
read-write
OPMODE
Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
24
4
read-write
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
24
4
read-write
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
24
4
read-write
SC_TMRDAT0
SC_TMRDAT0
SC Timer 0 Current Data Register
0x38
-1
read-only
n
0x0
0x0
CNT0
Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TMRDAT1_2
SC_TMRDAT1_2
SC Timer 1 and 2 Current Data Register
0x3C
-1
read-only
n
0x0
0x0
CNT1
Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
CNT2
Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
7
1
read-write
0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
6
1
read-write
0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Data Length\nNote: In smart card mode, this WLS must be '00'
4
2
read-write
0
Character Data Length is 8 bits
#00
1
Character Data Length is 7 bits
#01
2
Character Data length is 6 bits
#10
3
Character Data Length is 5 bits
#11
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0xD04
0x4
registers
n
0xD0C
0x8
registers
n
0xD18
0xC
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness\n
15
1
read-write
0
Little-endian
#0
1
Big-endian
#1
PRIGROUP
Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority,
8
3
read-write
SYSRESETREQ
System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
VECTRESET
Reserved for Debug Use \nThis bit is read as 0. You must write 0 to this bit, otherwise the behavior is Unpredictable
0
1
read-write
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read only)\n
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
NMI Set-Pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception is not pending
#0
1
Changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-Pending Bit
Write:
Note: This is a write only bit. To clear the PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-Pending Bit\nWrite:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-Pending Bit
Write:
Note: This is a write only bit. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-Pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
RETTOBASE
Preempted Active Exceptions indicator\nIndicate whether There are Preempted Active Exceptions\n
11
1
read-write
0
there are preempted active exceptions to execute
#0
1
there are no active exceptions, or the currently-executing exception is the only active exception
#1
VECTACTIVE
Contains The Active Exception Number\n
0
6
read-write
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
12
6
read-write
0
no pending exceptions
0
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event On Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.\n
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enters sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR1
SHPR1
System Handler Priority Register 1
0xD18
read-write
n
0x0
0x0
PRI_4
Priority of system handler 4, MemManage
0
8
read-write
PRI_5
Priority of system handler 5, BusFault
8
8
read-write
PRI_6
Priority of system handler 6, UsageFault
16
8
read-write
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority Of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority Of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority Of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection\n
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled\n
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled\n
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0.
0
24
read-write
SDH
SDH Register Map
SDH
0x0
0x0
0x2C
registers
n
0x400
0x4
registers
n
0x408
0x10
registers
n
0x800
0xC
registers
n
0x820
0x20
registers
n
BLEN
SDH_BLEN
SD Block Length Register
0x838
-1
read-write
n
0x0
0x0
BLKLEN
SD BLOCK LENGTH In Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN+1.\nNote: The default SD block length is 512 bytes
0
11
read-write
CMDARG
SDH_CMDARG
SD Command Argument Register
0x824
read-write
n
0x0
0x0
ARGUMENT
SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
0
32
read-write
CTL
SDH_CTL
SD Control and Status Register
0x820
-1
read-write
n
0x0
0x0
BLKCNT
Block Counts To Be Transferred Or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. Don't fill 0x0 to this field.\nNote: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
16
8
read-write
CLK74OEN
Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
5
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will output 74 clock cycles to SD card
#1
CLK8OEN
Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
6
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will output 8 clock cycles
#1
CLKKEEP0
SD Clock Enable Control for Port 0\n
7
1
read-write
0
SD host decided when to output clock and when to disable clock output automatically
#0
1
SD clock always keeps free running
#1
CLKKEEP1
SD Clock Enable Control for Port 1\n
31
1
read-write
0
SD host decided when to output clock and when to disable clock output automatically
#0
1
SD clock always keeps free running
#1
CMDCODE
SD Command Code\nThis register contains the SD command code (0x00 - 0x3F).
8
6
read-write
COEN
Command Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
0
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will output a command to SD card
#1
CTLRST
Software Engine Reset\n
14
1
read-write
0
No effect
#0
1
Reset the internal state machine and counters. The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared). This bit will be auto cleared after few clock cycles
#1
DBW
SD Data Bus Width (For 1-Bit / 4-Bit Selection)\n
15
1
read-write
0
Data bus width is 1-bit
#0
1
Data bus width is 4-bit
#1
DIEN
Data Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
2
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will wait to receive block data and the CRC16 value from SD card
#1
DOEN
Data Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
3
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will transfer block data and the CRC16 value to SD card
#1
R2EN
Response R2 Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
4
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7)
#1
RIEN
Response Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
1
1
read-write
0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#0
1
Enabled, SD host will wait to receive a response from SD card
#1
SDNWR
NWR Parameter For Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1.
24
4
read-write
SDPORT
SD Port Selection\n
29
2
read-write
0
Port 0 selected
#00
1
Port 1 selected
#01
DMABCNT
SDH_DMABCNT
DMA Transfer Byte Count Register
0x40C
read-only
n
0x0
0x0
BCNT
DMA Transfer Byte Count (Read Only)
This field indicates the remained byte count of DMA transfer. The value of this field is valid only when DMA is busy otherwise, it is 0.
0
26
read-only
DMACTL
SDH_DMACTL
DMA Control and Status Register
0x400
read-write
n
0x0
0x0
DMABUSY
DMA Transfer Is In Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not.\n
9
1
read-write
0
DMA transfer is not in progress
#0
1
DMA transfer is in progress
#1
DMAEN
DMA Engine Enable Bit\nIf this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote: If target abort is occurred, DMAEN will be cleared.
0
1
read-write
0
DMA Disabled
#0
1
DMA Enabled
#1
DMARST
Software Engine Reset\nNote: The software reset DMA related registers.
1
1
read-write
0
No effect
#0
1
Reset internal state machine and pointers. The contents of control register will not be cleared. This bit will auto be cleared after few clock cycles
#1
SGEN
Scatter-Gather Function Enable Bit\n
3
1
read-write
0
Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory)
#0
1
Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table. The format of these Pads' will be described later)
#1
DMAINTEN
SDH_DMAINTEN
DMA Interrupt Enable Control Register
0x410
-1
read-write
n
0x0
0x0
ABORTIEN
DMA Read/Write Target Abort Interrupt Enable Bit\n
0
1
read-write
0
Target abort interrupt generation Disabled during DMA transfer
#0
1
Target abort interrupt generation Enabled during DMA transfer
#1
WEOTIEN
Wrong EOT Encountered Interrupt Enable Bit\n
1
1
read-write
0
Interrupt generation Disabled when wrong EOT is encountered
#0
1
Interrupt generation Enabled when wrong EOT is encountered
#1
DMAINTSTS
SDH_DMAINTSTS
DMA Interrupt Status Register
0x414
read-write
n
0x0
0x0
ABORTIF
DMA Read/Write Target Abort Interrupt Flag\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
WEOTIF
Wrong EOT Encountered Interrupt Flag\nWhen DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
1
1
read-write
0
No EOT encountered before DMA transfer finished
#0
1
EOT encountered before DMA transfer finished
#1
DMASA
SDH_DMASA
DMA Transfer Starting Address Register
0x408
read-write
n
0x0
0x0
DMASA
DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
1
31
read-write
ORDER
Determined To The PAD Table Fetching Is In Order Or Out Of Order\n
0
1
read-write
0
PAD table is fetched in order
#0
1
PAD table is fetched out of order
#1
FB_0
SDH_FB_0
Shared Buffer (FIFO)
0x0
read-write
n
0x0
0x0
FB_1
SDH_FB_1
Shared Buffer (FIFO)
0x4
read-write
n
0x0
0x0
FB_10
SDH_FB_10
Shared Buffer (FIFO)
0x28
read-write
n
0x0
0x0
FB_11
SDH_FB_11
Shared Buffer (FIFO)
0x2C
read-write
n
0x0
0x0
FB_12
SDH_FB_12
Shared Buffer (FIFO)
0x30
read-write
n
0x0
0x0
FB_13
SDH_FB_13
Shared Buffer (FIFO)
0x34
read-write
n
0x0
0x0
FB_14
SDH_FB_14
Shared Buffer (FIFO)
0x38
read-write
n
0x0
0x0
FB_15
SDH_FB_15
Shared Buffer (FIFO)
0x3C
read-write
n
0x0
0x0
FB_16
SDH_FB_16
Shared Buffer (FIFO)
0x40
read-write
n
0x0
0x0
FB_17
SDH_FB_17
Shared Buffer (FIFO)
0x44
read-write
n
0x0
0x0
FB_18
SDH_FB_18
Shared Buffer (FIFO)
0x48
read-write
n
0x0
0x0
FB_19
SDH_FB_19
Shared Buffer (FIFO)
0x4C
read-write
n
0x0
0x0
FB_2
SDH_FB_2
Shared Buffer (FIFO)
0x8
read-write
n
0x0
0x0
FB_20
SDH_FB_20
Shared Buffer (FIFO)
0x50
read-write
n
0x0
0x0
FB_21
SDH_FB_21
Shared Buffer (FIFO)
0x54
read-write
n
0x0
0x0
FB_22
SDH_FB_22
Shared Buffer (FIFO)
0x58
read-write
n
0x0
0x0
FB_23
SDH_FB_23
Shared Buffer (FIFO)
0x5C
read-write
n
0x0
0x0
FB_24
SDH_FB_24
Shared Buffer (FIFO)
0x60
read-write
n
0x0
0x0
FB_25
SDH_FB_25
Shared Buffer (FIFO)
0x64
read-write
n
0x0
0x0
FB_26
SDH_FB_26
Shared Buffer (FIFO)
0x68
read-write
n
0x0
0x0
FB_27
SDH_FB_27
Shared Buffer (FIFO)
0x6C
read-write
n
0x0
0x0
FB_28
SDH_FB_28
Shared Buffer (FIFO)
0x70
read-write
n
0x0
0x0
FB_29
SDH_FB_29
Shared Buffer (FIFO)
0x74
read-write
n
0x0
0x0
FB_3
SDH_FB_3
Shared Buffer (FIFO)
0xC
read-write
n
0x0
0x0
FB_30
SDH_FB_30
Shared Buffer (FIFO)
0x78
read-write
n
0x0
0x0
FB_31
SDH_FB_31
Shared Buffer (FIFO)
0x7C
read-write
n
0x0
0x0
FB_4
SDH_FB_4
Shared Buffer (FIFO)
0x10
read-write
n
0x0
0x0
FB_5
SDH_FB_5
Shared Buffer (FIFO)
0x14
read-write
n
0x0
0x0
FB_6
SDH_FB_6
Shared Buffer (FIFO)
0x18
read-write
n
0x0
0x0
FB_7
SDH_FB_7
Shared Buffer (FIFO)
0x1C
read-write
n
0x0
0x0
FB_8
SDH_FB_8
Shared Buffer (FIFO)
0x20
read-write
n
0x0
0x0
FB_9
SDH_FB_9
Shared Buffer (FIFO)
0x24
read-write
n
0x0
0x0
GCTL
SDH_GCTL
Global Control and Status Register
0x800
read-write
n
0x0
0x0
GCTLRST
Software Engine Reset\n
0
1
read-write
0
No effect
#0
1
Reset SD host. The contents of control register will not be cleared. This bit will auto cleared after reset complete
#1
SDEN
Secure Digital Functionality Enable Bit\n
1
1
read-write
0
SD functionality disabled
#0
1
SD functionality enabled
#1
GINTEN
SDH_GINTEN
Global Interrupt Control Register
0x804
-1
read-write
n
0x0
0x0
DTAIEN
DMA READ/WRITE Target Abort Interrupt Enable Bit\n
0
1
read-write
0
DMA READ/WRITE target abort interrupt generation disabled
#0
1
DMA READ/WRITE target abort interrupt generation enabled
#1
GINTSTS
SDH_GINTSTS
Global Interrupt Status Register
0x808
read-write
n
0x0
0x0
DTAIF
DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred, please reset all engine.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
INTEN
SDH_INTEN
SD Interrupt Control Register
0x828
-1
read-write
n
0x0
0x0
BLKDIEN
Block Transfer Done Interrupt Enable Bit\n
0
1
read-write
0
SD host will not generate interrupt when data-in (out) transfer done
#0
1
SD host will generate interrupt when data-in (out) transfer done
#1
CDIEN0
SD0 Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card 0 is inserted or removed.\n
8
1
read-write
0
Disable
#0
1
Enabled
#1
CDIEN1
SD1 Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card 1 is inserted or removed.\n
9
1
read-write
0
Disable
#0
1
Enabled
#1
CDSRC0
SD0 Card Detect Source Selection\n
30
1
read-write
0
From SD0 card's DAT3 pin
#0
1
From GPIO pin
#1
CDSRC1
SD1 Card Detect Source Selection\n
31
1
read-write
0
From SD1 card's DAT3 pin
#0
1
From GPIO pin
#1
CRCIEN
CRC7, CRC16 And CRC Status Error Interrupt Enable Bit\n
1
1
read-write
0
SD host will not generate interrupt when CRC7, CRC16 and CRC status is error
#0
1
SD host will generate interrupt when CRC7, CRC16 and CRC status is error
#1
DITOIEN
Data Input Time-Out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out. Time-out value is specified at TOUT register.\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
RTOIEN
Response Time-Out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT register.\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
WKIEN
Wake-Up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.\n
14
1
read-write
0
Disabled
#0
1
Enabled
#1
INTSTS
SDH_INTSTS
SD Interrupt Status Register
0x82C
-1
read-write
n
0x0
0x0
BLKDIF
Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
0
Not finished yet
#0
1
Done
#1
CDIF0
SD0 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 0 is inserted or removed. Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it.
8
1
read-only
0
No card is inserted or removed
#0
1
There is a card inserted in or removed from SD0
#1
CDIF1
SD1 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 1 is inserted or removed. Only when CDIEN1 (SDH_INTEN[9]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it.
9
1
read-only
0
No card is inserted or removed
#0
1
There is a card inserted in or removed from SD1
#1
CDSTS0
Card Detect Status Of SD0 (Read Only)\nThis bit indicates the card detect pin status of SD0, and is used for card detection. When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.\n
16
1
read-only
0
Card removed.\nCard inserted
#0
1
Card inserted.\nCard removed
#1
CDSTS1
Card Detect Status Of SD1 (Read Only)\nThis bit indicates the card detect pin status of SD1, and is used for card detection. When there is a card inserted in or removed from SD1, software should check this bit to confirm if there is really a card insertion or removal.\n
17
1
read-only
0
Card removed.\nCard inserted
#0
1
Card inserted.\nCard removed
#1
CRC16
CRC16 Check Status Of Data-In Transfer (Read Only)
SD host will check CRC16 correctness after data-in transfer.
3
1
read-only
0
Fault
#0
1
OK
#1
CRC7
CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in. If that response does not contain CRC7 information (ex. R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.\n
2
1
read-only
0
Fault
#0
1
OK
#1
CRCIF
CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. When CRC error is occurred, software should reset SD engine. Some response (ex. R3) doesn't have CRC7 information with it SD host will still calculate CRC7, get CRC error and set this flag. In this condition, software should ignore CRC error and clears this bit manually.
Note: This bit is read only, but can be cleared by writing '1' to it.
1
1
read-only
0
No CRC error is occurred
#0
1
CRC error is occurred
#1
CRCSTS
CRC Status Value Of Data-Out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer.\n
4
3
read-only
2
Positive CRC status
#010
5
Negative CRC status
#101
7
SD card programming error occurs
#111
DAT0STS
DAT0 Pin Status Of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port.
7
1
read-only
DAT1STS
DAT1 Pin Status Of SD Port (Read Only)\nThis bit indicates the DAT1 pin status of SD port.
18
1
read-only
DITOIF
Data Input Time-Out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
13
1
read-only
0
Not time-out
#0
1
Data input time-out
#1
RTOIF
Response Time-Out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
12
1
read-only
0
Not time-out
#0
1
Response time-out
#1
RESP0
SDH_RESP0
SD Receiving Response Token Register 0
0x830
read-only
n
0x0
0x0
RESPTK0
SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token.
0
32
read-only
RESP1
SDH_RESP1
SD Receiving Response Token Register 1
0x834
read-only
n
0x0
0x0
RESPTK1
SD Receiving Response Token 1\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token.
0
8
read-only
TOUT
SDH_TOUT
SD Response/Data-in Time-out Register
0x83C
read-write
n
0x0
0x0
TOUT
SD Response/Data-In Time-Out Value\nA 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached. The time period depends on SD engine clock frequency. Do not write a small number into this field, or you may never get response or data due to time-out.\nNote: Filling 0x0 into this field will disable hardware time-out function.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.
Note :
1. is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
2 .is the peripheral clock which is used to drive the SPI logic unit.
0
8
read-write
SPI_CTL
SPI_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DUALIOEN
Dual I/O Mode Enable Bit\n
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
8
5
read-write
LSB
Send LSB First\n
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
QDIODIR
Quad Or Dual I/O Mode Direction Control\n
20
1
read-write
0
Quad or Dual Input mode
#0
1
Quad or Dual Output mode
#1
QUADIOEN
Quad I/O Mode Enable Bit\n
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
4
4
read-write
TWOBIT
2-Bit Mode Enable Bit\nNote: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TXNEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SP bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPI_FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit\n
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-Out Interrupt Enable Bit (Slave Only)\n
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXRST
Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.\n
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPI_PDMACTL
SPI_PDMACTL
SPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit\n
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPI_RX
SPI_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SPI_SSCTL
SPI_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-Wire Mode Enable Bit\nIn Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO and SPIn_MOSI pins.\n
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\n
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-Out Period \nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-Out Interrupt Enable Bit\n
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-Out Reset Control\n
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit\n
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
0
1
read-write
0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#0
1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit \n
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS).\n
2
1
read-write
0
The slave selection signal SPIn_SS is active low
#0
1
The slave selection signal SPIn_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit \n
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)\n
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\n
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)\n
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
Receive FIFO does not over run
#0
1
Receive FIFO over run
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)\n
10
1
read-only
0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVTOIF
Slave Time-Out Interrupt Flag\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
The SPI controller is disabled
#0
1
The SPI controller is enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt be cleared or not occurrs
#0
1
Slave select active interrupt event occurrs
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt be cleared or not occurrs
#0
1
Slave select inactive interrupt event occurrs
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\n
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\n
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX Or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)\n
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SPI1
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.
Note :
1. is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
2 .is the peripheral clock which is used to drive the SPI logic unit.
0
8
read-write
SPI_CTL
SPI_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DUALIOEN
Dual I/O Mode Enable Bit\n
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
8
5
read-write
LSB
Send LSB First\n
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
QDIODIR
Quad Or Dual I/O Mode Direction Control\n
20
1
read-write
0
Quad or Dual Input mode
#0
1
Quad or Dual Output mode
#1
QUADIOEN
Quad I/O Mode Enable Bit\n
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
4
4
read-write
TWOBIT
2-Bit Mode Enable Bit\nNote: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TXNEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SP bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPI_FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit\n
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-Out Interrupt Enable Bit (Slave Only)\n
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXRST
Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.\n
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPI_PDMACTL
SPI_PDMACTL
SPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit\n
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPI_RX
SPI_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SPI_SSCTL
SPI_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-Wire Mode Enable Bit\nIn Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO and SPIn_MOSI pins.\n
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\n
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-Out Period \nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-Out Interrupt Enable Bit\n
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-Out Reset Control\n
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit\n
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
0
1
read-write
0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#0
1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit \n
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS).\n
2
1
read-write
0
The slave selection signal SPIn_SS is active low
#0
1
The slave selection signal SPIn_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit \n
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)\n
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\n
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)\n
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
Receive FIFO does not over run
#0
1
Receive FIFO over run
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)\n
10
1
read-only
0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVTOIF
Slave Time-Out Interrupt Flag\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
The SPI controller is disabled
#0
1
The SPI controller is enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt be cleared or not occurrs
#0
1
Slave select active interrupt event occurrs
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt be cleared or not occurrs
#0
1
Slave select inactive interrupt event occurrs
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\n
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\n
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX Or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)\n
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SPI2
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.
Note :
1. is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
2 .is the peripheral clock which is used to drive the SPI logic unit.
0
8
read-write
SPI_CTL
SPI_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DUALIOEN
Dual I/O Mode Enable Bit\n
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
8
5
read-write
LSB
Send LSB First\n
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
QDIODIR
Quad Or Dual I/O Mode Direction Control\n
20
1
read-write
0
Quad or Dual Input mode
#0
1
Quad or Dual Output mode
#1
QUADIOEN
Quad I/O Mode Enable Bit\n
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
4
4
read-write
TWOBIT
2-Bit Mode Enable Bit\nNote: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TXNEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SP bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPI_FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit\n
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-Out Interrupt Enable Bit (Slave Only)\n
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXRST
Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.\n
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPI_PDMACTL
SPI_PDMACTL
SPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit\n
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPI_RX
SPI_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SPI_SSCTL
SPI_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-Wire Mode Enable Bit\nIn Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO and SPIn_MOSI pins.\n
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\n
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-Out Period \nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-Out Interrupt Enable Bit\n
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-Out Reset Control\n
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit\n
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
0
1
read-write
0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#0
1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit \n
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS).\n
2
1
read-write
0
The slave selection signal SPIn_SS is active low
#0
1
The slave selection signal SPIn_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit \n
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)\n
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\n
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)\n
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
Receive FIFO does not over run
#0
1
Receive FIFO over run
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)\n
10
1
read-only
0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVTOIF
Slave Time-Out Interrupt Flag\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
The SPI controller is disabled
#0
1
The SPI controller is enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt be cleared or not occurrs
#0
1
Slave select active interrupt event occurrs
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt be cleared or not occurrs
#0
1
Slave select inactive interrupt event occurrs
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\n
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\n
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX Or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)\n
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SPI3
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.
Note :
1. is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
2 .is the peripheral clock which is used to drive the SPI logic unit.
0
8
read-write
SPI_CTL
SPI_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DUALIOEN
Dual I/O Mode Enable Bit\n
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
8
5
read-write
LSB
Send LSB First\n
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
QDIODIR
Quad Or Dual I/O Mode Direction Control\n
20
1
read-write
0
Quad or Dual Input mode
#0
1
Quad or Dual Output mode
#1
QUADIOEN
Quad I/O Mode Enable Bit\n
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive On Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
4
4
read-write
TWOBIT
2-Bit Mode Enable Bit\nNote: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TXNEG
Transmit On Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SP bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPI_FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit\n
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit\n
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-Out Interrupt Enable Bit (Slave Only)\n
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXRST
Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit\n
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.\n
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
SPI_PDMACTL
SPI_PDMACTL
SPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit\n
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
SPI_RX
SPI_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SPI_SSCTL
SPI_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-Wire Mode Enable Bit\nIn Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO and SPIn_MOSI pins.\n
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\n
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-Out Period \nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-Out Interrupt Enable Bit\n
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-Out Reset Control\n
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit\n
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
0
1
read-write
0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#0
1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit \n
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS).\n
2
1
read-write
0
The slave selection signal SPIn_SS is active low
#0
1
The slave selection signal SPIn_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit \n
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)\n
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\n
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)\n
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
Receive FIFO does not over run
#0
1
Receive FIFO over run
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)\n
10
1
read-only
0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVTOIF
Slave Time-Out Interrupt Flag\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
The SPI controller is disabled
#0
1
The SPI controller is enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt be cleared or not occurrs
#0
1
Slave select active interrupt event occurrs
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt be cleared or not occurrs
#0
1
Slave select inactive interrupt event occurrs
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\n
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\n
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX Or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)\n
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x18
0x60
registers
n
0xC0
0x10
registers
n
0xF0
0xC
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODEN
Brown-Out Detector Enable Bit (Write Protect)
The default value is set by flash controller user configuration register config0 bit[23]
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODINTF
Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-Out Detector Low Power Mode (Write Protect)
The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-Out Detector Output Status\n
6
1
read-write
0
Brown-out Detector output status is 0. It means the detected voltage is higher than BODVL setting or BODEN is 0
#0
1
Brown-out Detector output status is 1. It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000
#1
BODRSTEN
Brown-Out Reset Enable Bit (Write Protect)
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
The default value is set by flash controller user configuration register config0 bit[20].
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
3
1
read-write
0
Brown-out INTERRUPT function Enabled
#0
1
Brown-out RESET function Enabled
#1
BODVL
Brown-Out Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash controller user configuration register config0 bit[22:21]
Relationship between BODVL and Brown-out voltage listed below:
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
1
2
read-write
0
2.2V
#00
1
2.7V
#01
2
3.7V
#10
3
4.5V
#11
LVREN
Low Voltage Reset Enable Bit (Write Protect)
The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default)
#1
GPA_MFPH
SYS_GPA_MFPH
Port A High Byte Multi-function Control Register
0x34
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
4
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
4
read-write
PA12MFP
PA.12 Multi-function Pin Selection
16
4
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
4
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
4
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
4
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
4
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
4
read-write
GPA_MFPL
SYS_GPA_MFPL
Port A Low Byte Multi-function Control Register
0x30
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
4
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
4
read-write
GPB_MFPH
SYS_GPB_MFPH
Port B High Byte Multi-function Control Register
0x3C
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
4
read-write
GPB_MFPL
SYS_GPB_MFPL
Port B Low Byte Multi-function Control Register
0x38
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFPH
SYS_GPC_MFPH
Port C High Byte Multi-function Control Register
0x44
read-write
n
0x0
0x0
PC10MFP
PC.10 Multi-function Pin Selection
8
4
read-write
PC11MFP
PC.11 Multi-function Pin Selection
12
4
read-write
PC12MFP
PC.12 Multi-function Pin Selection
16
4
read-write
PC13MFP
PC.13 Multi-function Pin Selection
20
4
read-write
PC14MFP
PC.14 Multi-function Pin Selection
24
4
read-write
PC15MFP
PC.15 Multi-function Pin Selection
28
4
read-write
PC8MFP
PC.8 Multi-function Pin Selection
0
4
read-write
PC9MFP
PC.9 Multi-function Pin Selection
4
4
read-write
GPC_MFPL
SYS_GPC_MFPL
Port C Low Byte Multi-function Control Register
0x40
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
4
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
4
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
4
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
4
read-write
GPD_MFPH
SYS_GPD_MFPH
Port D High Byte Multi-function Control Register
0x4C
read-write
n
0x0
0x0
PD10MFP
PD.10 Multi-function Pin Selection
8
4
read-write
PD11MFP
PD.11 Multi-function Pin Selection
12
4
read-write
PD12MFP
PD.12 Multi-function Pin Selection
16
4
read-write
PD13MFP
PD.13 Multi-function Pin Selection
20
4
read-write
PD14MFP
PD.14 Multi-function Pin Selection
24
4
read-write
PD15MFP
PD.15 Multi-function Pin Selection
28
4
read-write
PD8MFP
PD.8 Multi-function Pin Selection
0
4
read-write
PD9MFP
PD.9 Multi-function Pin Selection
4
4
read-write
GPD_MFPL
SYS_GPD_MFPL
Port D Low Byte Multi-function Control Register
0x48
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
4
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
4
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
4
read-write
PD3MFP
PD.3 Multi-function Pin Selection
12
4
read-write
PD4MFP
PD.4 Multi-function Pin Selection
16
4
read-write
PD5MFP
PD.5 Multi-function Pin Selection
20
4
read-write
PD6MFP
PD.6 Multi-function Pin Selection
24
4
read-write
PD7MFP
PD.7 Multi-function Pin Selection
28
4
read-write
GPE_MFPH
SYS_GPE_MFPH
Port E High Byte Multi-function Control Register
0x54
read-write
n
0x0
0x0
PE10MFP
PE.10 Multi-function Pin Selection
8
4
read-write
PE11MFP
PE.11 Multi-function Pin Selection
12
4
read-write
PE12MFP
PE.12 Multi-function Pin Selection
16
4
read-write
PE13MFP
PE.13 Multi-function Pin Selection
20
4
read-write
PE14MFP
PE.14 Multi-function Pin Selection
24
4
read-write
PE15MFP
PE.15 Multi-function Pin Selection
28
4
read-write
PE8MFP
PE.8 Multi-function Pin Selection
0
4
read-write
PE9MFP
PE.9 Multi-function Pin Selection
4
4
read-write
GPE_MFPL
SYS_GPE_MFPL
Port E Low Byte Multi-function Control Register
0x50
read-write
n
0x0
0x0
PE0MFP
PE.0 Multi-function Pin Selection
0
4
read-write
PE1MFP
PE.1 Multi-function Pin Selection
4
4
read-write
PE2MFP
PE.2 Multi-function Pin Selection
8
4
read-write
PE3MFP
PE.3 Multi-function Pin Selection
12
4
read-write
PE4MFP
PE.4 Multi-function Pin Selection
16
4
read-write
PE5MFP
PE.5 Multi-function Pin Selection
20
4
read-write
PE6MFP
PE.6 Multi-function Pin Selection
24
4
read-write
PE7MFP
PE.7 Multi-function Pin Selection
28
4
read-write
GPF_MFPH
SYS_GPF_MFPH
Port F High Byte Multi-function Control Register
0x5C
read-write
n
0x0
0x0
PF10MFP
PF.10 Multi-function Pin Selection
8
4
read-write
PF11MFP
PF.11 Multi-function Pin Selection
12
4
read-write
PF12MFP
PF.12 Multi-function Pin Selection
16
4
read-write
PF13MFP
PF.13 Multi-function Pin Selection
20
4
read-write
PF14MFP
PF.14 Multi-function Pin Selection
24
4
read-write
PF15MFP
PF.15 Multi-function Pin Selection
28
4
read-write
PF8MFP
PF.8 Multi-function Pin Selection
0
4
read-write
PF9MFP
PF.9 Multi-function Pin Selection
4
4
read-write
GPF_MFPL
SYS_GPF_MFPL
Port F Low Byte Multi-function Control Register
0x58
read-write
n
0x0
0x0
PF0MFP
PF.0 Multi-function Pin Selection
0
4
read-write
PF1MFP
PF.1 Multi-function Pin Selection
4
4
read-write
PF2MFP
PF.2 Multi-function Pin Selection
8
4
read-write
PF3MFP
PF.3 Multi-function Pin Selection
12
4
read-write
PF4MFP
PF.4 Multi-function Pin Selection
16
4
read-write
PF5MFP
PF.5 Multi-function Pin Selection
20
4
read-write
PF6MFP
PF.6 Multi-function Pin Selection
24
4
read-write
PF7MFP
PF.7 Multi-function Pin Selection
28
4
read-write
GPG_MFPH
SYS_GPG_MFPH
Port G High Byte Multi-function Control Register
0x64
-1
read-write
n
0x0
0x0
PG10MFP
PG.10 Multi-function Pin Selection
8
4
read-write
PG11MFP
PG.11 Multi-function Pin Selection
12
4
read-write
PG12MFP
PG.12 Multi-function Pin Selection
16
4
read-write
PG13MFP
PG.13 Multi-function Pin Selection
20
4
read-write
PG14MFP
PG.14 Multi-function Pin Selection
24
4
read-write
PG15MFP
PG.15 Multi-function Pin Selection
28
4
read-write
PG8MFP
PG.8 Multi-function Pin Selection
0
4
read-write
PG9MFP
PG.9 Multi-function Pin Selection
4
4
read-write
GPG_MFPL
SYS_GPG_MFPL
Port G Low Byte Multi-function Control Register
0x60
read-write
n
0x0
0x0
PG0MFP
PG.0 Multi-function Pin Selection
0
4
read-write
PG1MFP
PG.1 Multi-function Pin Selection
4
4
read-write
PG2MFP
PG.2 Multi-function Pin Selection
8
4
read-write
PG3MFP
PG.3 Multi-function Pin Selection
12
4
read-write
PG4MFP
PG.4 Multi-function Pin Selection
16
4
read-write
PG5MFP
PG.5 Multi-function Pin Selection
20
4
read-write
PG6MFP
PG.6 Multi-function Pin Selection
24
4
read-write
PG7MFP
PG.7 Multi-function Pin Selection
28
4
read-write
GPH_MFPH
SYS_GPH_MFPH
Port H High Byte Multi-function Control Register
0x6C
read-write
n
0x0
0x0
PH10MFP
PH.10 Multi-function Pin Selection
8
4
read-write
PH11MFP
PH.11 Multi-function Pin Selection
12
4
read-write
PH12MFP
PH.12 Multi-function Pin Selection
16
4
read-write
PH13MFP
PH.13 Multi-function Pin Selection
20
4
read-write
PH14MFP
PH.14 Multi-function Pin Selection
24
4
read-write
PH15MFP
PH.15 Multi-function Pin Selection
28
4
read-write
PH8MFP
PH.8 Multi-function Pin Selection
0
4
read-write
PH9MFP
PH.9 Multi-function Pin Selection
4
4
read-write
GPH_MFPL
SYS_GPH_MFPL
Port H Low Byte Multi-function Control Register
0x68
read-write
n
0x0
0x0
PH0MFP
PH.0 Multi-function Pin Selection
0
4
read-write
PH1MFP
PH.1 Multi-function Pin Selection
4
4
read-write
PH2MFP
PH.2 Multi-function Pin Selection
8
4
read-write
PH3MFP
PH.3 Multi-function Pin Selection
12
4
read-write
PH4MFP
PH.4 Multi-function Pin Selection
16
4
read-write
PH5MFP
PH.5 Multi-function Pin Selection
20
4
read-write
PH6MFP
PH.6 Multi-function Pin Selection
24
4
read-write
PH7MFP
PH.7 Multi-function Pin Selection
28
4
read-write
GPI_MFPH
SYS_GPI_MFPH
Port I High Byte Multi-function Control Register
0x74
read-write
n
0x0
0x0
PI10MFP
PI.10 Multi-function Pin Selection
8
4
read-write
PI11MFP
PI.11 Multi-function Pin Selection
12
4
read-write
PI12MFP
PI.12 Multi-function Pin Selection
16
4
read-write
PI13MFP
PI.13 Multi-function Pin Selection
20
4
read-write
PI14MFP
PI.14 Multi-function Pin Selection
24
4
read-write
PI15MFP
PI.15 Multi-function Pin Selection
28
4
read-write
PI8MFP
PI.8 Multi-function Pin Selection
0
4
read-write
PI9MFP
PI.9 Multi-function Pin Selection
4
4
read-write
GPI_MFPL
SYS_GPI_MFPL
Port I Low Byte Multi-function Control Register
0x70
read-write
n
0x0
0x0
PI0MFP
PI.0 Multi-function Pin Selection
0
4
read-write
PI1MFP
PI.1 Multi-function Pin Selection
4
4
read-write
PI2MFP
PI.2 Multi-function Pin Selection
8
4
read-write
PI3MFP
PI.3 Multi-function Pin Selection
12
4
read-write
PI4MFP
PI.4 Multi-function Pin Selection
16
4
read-write
PI5MFP
PI.5 Multi-function Pin Selection
20
4
read-write
PI6MFP
PI.6 Multi-function Pin Selection
24
4
read-write
PI7MFP
PI.7 Multi-function Pin Selection
28
4
read-write
IPRST0
SYS_IPRST0
Peripheral Controller Reset Control Register 1
0x8
read-write
n
0x0
0x0
CAPRST
Image Capture Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CAP controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Reference the register SYS_REGLCTL at address GCR_BA+0x100
8
1
read-write
0
CAP controller normal operation
#0
1
CAP controller reset
#1
CHIPRST
Chip One-Shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
This bit is a write protected bit, which means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
0
1
read-write
0
Chip normal operation
#0
1
Chip one shot reset
#1
CPURST
Processor Core One-Shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CRC controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Reference the register SYS_REGLCTL at address GCR_BA+0x100
7
1
read-write
0
CRC controller normal operation
#0
1
CRC controller reset
#1
CRPTRST
CRYPTO Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
12
1
read-write
0
CRYPTO controller normal operation
#0
1
CRYPTO controller reset
#1
EBIRST
EBI Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
3
1
read-write
0
EBI controller normal operation
#0
1
EBI controller reset
#1
EMACRST
EMAC Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the EMAC controller. User needs to set this bit to 0 to release from the reset state.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
5
1
read-write
0
EMAC controller normal operation
#0
1
EMAC controller reset
#1
PDMARST
PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
SDHRST
SD HOST Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the SD HOST controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
6
1
read-write
0
SD HOST controller normal operation
#0
1
SD HOST controller reset
#1
USBHRST
USBH Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the HSB HOST controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
4
1
read-write
0
USBH controller normal operation
#0
1
USBH controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Controller Reset Control Register 2
0xC
read-write
n
0x0
0x0
ACMPRST
Analog Comparator Controller Reset\n
7
1
read-write
0
Analog Comparator controller normal operation
#0
1
Analog Comparator controller reset
#1
CAN0RST
CAN0 Controller Reset\n
24
1
read-write
0
CAN0 controller normal operation
#0
1
CAN0 controller reset
#1
CAN1RST
CAN1 Controller Reset\n
25
1
read-write
0
CAN1 controller normal operation
#0
1
CAN1 controller reset
#1
EADCRST
ADC Controller Reset\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIORST
GPIO Controller Reset\n
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset\n
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset\n
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2S1RST
I2S1 Controller Reset\n
30
1
read-write
0
I2S1 controller normal operation
#0
1
I2S1 controller reset
#1
I2SRST
I2S Controller Reset\n
29
1
read-write
0
I2S controller normal operation
#0
1
I2S controller reset
#1
PS2RST
PS/2 Controller Reset\n
31
1
read-write
0
PS/2 controller normal operation
#0
1
PS/2 controller reset
#1
SPI0RST
SPI0 Controller Reset\n
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1RST
SPI1 Controller Reset\n
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
SPI2RST
SPI2 Controller Reset \n
14
1
read-write
0
SPI2 controller normal operation
#0
1
SPI2 controller reset
#1
SPI3RST
SPI3 Controller Reset \n
15
1
read-write
0
SPI3 controller normal operation
#0
1
SPI3 controller reset
#1
TMR0RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset\n
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset\n
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset\n
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset\n
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2RST
UART2 Controller Reset \n
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
UART3RST
UART3 Controller Reset \n
19
1
read-write
0
UART3 controller normal operation
#0
1
UART3 controller reset
#1
UART4RST
UART4 Controller Reset \n
20
1
read-write
0
UART4 controller normal operation
#0
1
UART4 controller reset
#1
UART5RST
UART2 Controller Reset \n
21
1
read-write
0
UART5 controller normal operation
#0
1
UART5 controller reset
#1
USBDRST
USB Device Controller Reset\n
27
1
read-write
0
USB device controller normal operation
#0
1
USB device controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Controller Reset Control Register 3
0x10
read-write
n
0x0
0x0
I2C4RST
I2C4 Controller Reset\n
8
1
read-write
0
I2C4 controller normal operation
#0
1
I2C4 controller reset
#1
PWM0RST
PWM0 Controller Reset\n
16
1
read-write
0
PWM0 controller normal operation
#0
1
PWM0 controller reset
#1
PWM1RST
PWM1 Controller Reset\n
17
1
read-write
0
PWM1 controller normal operation
#0
1
PWM1 controller reset
#1
QEI0RST
QEI0 Controller Reset\n
22
1
read-write
0
QEI0 controller normal operation
#0
1
QEI0 controller reset
#1
QEI1RST
QEI1 Controller Reset\n
23
1
read-write
0
QEI1 controller normal operation
#0
1
QEI1 controller reset
#1
SC0RST
SC0 Controller Reset\n
0
1
read-write
0
SC0 controller normal operation
#0
1
SC0 controller reset
#1
SC1RST
SC1 Controller Reset\n
1
1
read-write
0
SC1 controller normal operation
#0
1
SC1 controller reset
#1
SC2RST
SC2 Controller Reset\n
2
1
read-write
0
SC2 controller normal operation
#0
1
SC2 controller reset
#1
SC3RST
SC3 Controller Reset\n
3
1
read-write
0
SC3 controller normal operation
#0
1
SC3 controller reset
#1
SC4RST
SC4 Controller Reset\n
4
1
read-write
0
SC4 controller normal operation
#0
1
SC4 controller reset
#1
SC5RST
SC5 Controller Reset\n
5
1
read-write
0
SC5 controller normal operation
#0
1
SC5 controller reset
#1
IRCTCTL
SYS_IRCTCTL
IRC Trim Control Register
0xF0
read-write
n
0x0
0x0
CESTOPEN
Clock Error Stop Enable Bit\n
8
1
read-write
0
The trim operation is keep going if clock is inaccuracy
#0
1
The trim operation is stopped if clock is inaccuracy
#1
FREQSEL
Trim Frequency Selection\nThis field indicates the target frequency of HIRC auto trim.\nIf no any target frequency is selected (FREQSEL is 00), the HIRC auto trim function is disabled.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\n
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Enable HIRC auto trim function and trim HIRC to 22.1184 MHz
#01
2
Enable HIRC auto trim function and trim HIRC to 24 MHz
#10
3
Reserved
#11
LOOPSEL
Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nFor example, if CALCLOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.\n
4
2
read-write
0
Trim value calculation is based on average difference in 4 32.768 kHz clock
#00
1
Trim value calculation is based on average difference in 8 32.768 kHz clock
#01
2
Trim value calculation is based on average difference in 16 32.768 kHz clock
#10
3
Trim value calculation is based on average difference in 32 32.768 kHz clock
#11
RETRYCNT
Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.\n
6
2
read-write
0
Trim retry count limitation is 64
#00
1
Trim retry count limitation is 128
#01
2
Trim retry count limitation is 256
#10
3
Trim retry count limitation is 512
#11
IRCTIEN
SYS_IRCTIEN
IRC Trim Interrupt Enable Control Register
0xF4
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\n
2
1
read-write
0
Disable CLKERRIF status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF status to trigger an interrupt to CPU
#1
TFAILIEN
Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL.\nIf this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
1
1
read-write
0
Disable TFAILIF status to trigger an interrupt to CPU
#0
1
Enable TFAILIF status to trigger an interrupt to CPU
#1
IRCTISTS
SYS_IRCTISTS
IRC Trim Interrupt Status Register
0xF8
read-write
n
0x0
0x0
CLKERRIF
Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically if CESTOPEN is set to 1.\nIf this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
2
1
read-write
0
Clock frequency is accuracy
#0
1
Clock frequency is inaccuracy
#1
FREQLOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
0
1
read-write
TFAILIF
Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
1
1
read-write
0
Trim value update limitation count does not reach
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
PDID
SYS_PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used.
0
32
read-only
PORCTL
SYS_PORCTL
Power-On-reset Controller Register
0x24
read-write
n
0x0
0x0
POROFF
Power-On-Reset Enable Bit (Write Protect)
When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
/RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Write-protection Control Register
0x100
read-write
n
0x0
0x0
REGLCTL
Register Write-Protection Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Write-Protection Disable Index (Read Only)
The Protected registers are:
SYS_IPRST0: address 0x4000_0008
SYS_BODCTL: address 0x4000_0018
SYS_PORCTL: address 0x4000_0024
PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
APBCLK bit[0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select)
NMI_SEL]: address 0x4000_0300 (for NMI source select)
ISPCON: address 0x4000_5000 (Flash ISP Control register)
ISPTRG: address 0x4000_5010 (ISP Trigger Control register)
WTCR: address 0x4004_0000
FATCON: address 0x4000_5018
TAMPER: address 0x400E_1000
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Source Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPURF
CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M4 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
nRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag
The system reset flag is set by the Reset Signal from the Cortex-M4 Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M4
#0
1
The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
SRAM0_ERRADDR
SYS_SRAM0_ERRADDR
SRAM Parity Check Error First Address1
0xC8
read-only
n
0x0
0x0
PERRADDR
First SRAM Parity Check Fail Address\nThis register shows the first system SRAM parity error byte address.
0
32
read-only
SRAM1_ERRADDR
SYS_SRAM1_ERRADDR
SRAM Parity Check Error First Address2
0xCC
read-only
n
0x0
0x0
PERRADDR
Second SRAM Parity Check Fail Address\nThis register shows the second system SRAM parity error byte address.
0
32
read-only
SRAM_INTCTL
SYS_SRAM_INTCTL
SRAM Failed Interrupt Enable Control Register
0xC0
read-write
n
0x0
0x0
PERRIEN
SRAM Parity Check Fail Interrupt Enable Bit\n
0
1
read-write
0
SRAMF INT Disabled
#0
1
SRAMF INT Enabled when SRAM fail flag
#1
SRAM_STATUS
SYS_SRAM_STATUS
SRAM Parity Check Error Flag
0xC4
read-write
n
0x0
0x0
PERRIF0
SRAM Parity Check Fail Flag\n
0
1
read-write
0
No first 1 SRAM fail
#0
1
First SRAM Fail
#1
PERRIF1
SRAM Parity Check Fail Flag\n
1
1
read-write
0
2nd SRAM fail
#0
1
2nd SRAM Fail
#1
TEMPCTL
SYS_TEMPCTL
Temperature Sensor Control Register
0x1C
read-write
n
0x0
0x0
VTEMPEN
Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
USBPHY
SYS_USBPHY
USB PHY Control Register
0x2C
read-write
n
0x0
0x0
LDO33EN
LDO33 Enable Bit (Write Protect) \n
8
1
read-write
0
USB LDO33 Disabled
#0
1
USB LDO33 Enabled
#1
USBROLE
USB Role Configuration (Write Protect)\nUSB role configuration can be from ROMMAP or software setting if software setting option, controlled by ROMMAP, is enabled.\n
0
2
read-write
0
Standard USB device
#00
1
Standard USB host
#01
2
ID dependent device
#10
3
On-The-Go device
#11
VCID
SYS_VCID
Hardware Version Control Register
0x20
read-only
n
0x0
0x0
VCID
Hardware Version Control (Ready Only)
These registers repress hardware version.
These bits are the read protected bits.
It means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
0
16
read-only
VREFCTL
SYS_VREFCTL
ADC VREF Control Register
0x28
read-write
n
0x0
0x0
ADCMODESEL
ADC IP Selection (Write Protect)\n
8
1
read-write
0
ADC mode
#0
1
E ADC mode
#1
PWMSYNCMODE
PWM SYNC MODE (Write Protect)\n
9
1
read-write
0
PWM SYNC MODE Disabled PWM engine clock can different with HCLK
#0
1
PWM SYNC MODE Enabled PWM engine clock is same as HCLK
#1
VREFCTL
VREF Control Bits (Write Protect)\n
0
5
read-write
3
VREF is internal 2.65V
#00011
7
VREF is internal 2.048V
#00111
11
VREF is internal 3.072V
#01011
15
VREF is internal 4.096V
#01111
16
VREF is from AVDD
#10000
TIMER01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value (TIMERx_CNT value) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] timer interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the timer will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nUser can read CNT for getting current 24- bit event counter value if TIMERx_CTL[24] is 1
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CNTDATEN
Data Load Enable\nWhen this bit is set, timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
CNTEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
OPMODE
Timer Operation Mode\n
27
2
read-write
0
The Timer controller is operated in One-shot mode
#00
1
The Timer controller is operated in Periodic mode
#01
2
The Timer controller is operated in Toggle-output mode
#10
3
The Timer controller is operated in Continuous Counting mode
#11
PSC
PSC Counter\n
0
8
read-write
RSTCNT
Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
#1
TOGDIS1
Toggle Output 1 Disable\nSetting this bit will disable the Toggle output pins group 1.\nNote: The group1 pins are PB4, PB1, PC6, and PC1.
21
1
read-write
0
Toggle output pins group 1 Enabled
#0
1
Toggle output pins group 1 Disabled
#1
TOGDIS2
Toggle Output 2 Disable\nSetting this bit will disable the Toggle output pins group 2.\nNote1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled, toggle output signal is generated only from TOUT1 pins.\nNote2: The group2 pins are PD1, PE8, PE1, and PD11.
22
1
read-write
0
Toggle output pins group 2 Enabled
#0
1
Toggle output pins group 2 Disabled
#1
WKEN
Wake-Up Enable\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled if timer interrupt signal generated
#0
1
Wake-up trigger event Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-Bounce Enable\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce Enabled
#1
CAPEDGE
Timer External Pin Edge Detect\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#10
3
Reserved
#11
CAPEN
Timer External Pin Enable \nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin. \n
3
1
read-write
0
CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored
#0
1
CAPFUNCS function of TMx_EXT (x= 0~3) pin is active
#1
CAPFUNCS
Timer External Reset Counter / Capture Mode Select\n
4
1
read-write
0
Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value
#0
1
Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value
#1
CAPIEN
Timer External Interrupt Enable\n
5
1
read-write
0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-Bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TIMERx_CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or power-down mode if timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TIMER23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value (TIMERx_CNT value) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] timer interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the timer will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nUser can read CNT for getting current 24- bit event counter value if TIMERx_CTL[24] is 1
0
24
read-only
TIMER2_CTL
TIMER2_CTL
Timer2 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CNTDATEN
Data Load Enable\nWhen this bit is set, timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
CNTEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
OPMODE
Timer Operation Mode\n
27
2
read-write
0
The Timer controller is operated in One-shot mode
#00
1
The Timer controller is operated in Periodic mode
#01
2
The Timer controller is operated in Toggle-output mode
#10
3
The Timer controller is operated in Continuous Counting mode
#11
PSC
PSC Counter\n
0
8
read-write
RSTCNT
Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
#1
TOGDIS1
Toggle Output 1 Disable\nSetting this bit will disable the Toggle output pins group 1.\nNote: The group1 pins are PB4, PB1, PC6, and PC1.
21
1
read-write
0
Toggle output pins group 1 Enabled
#0
1
Toggle output pins group 1 Disabled
#1
TOGDIS2
Toggle Output 2 Disable\nSetting this bit will disable the Toggle output pins group 2.\nNote1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled, toggle output signal is generated only from TOUT1 pins.\nNote2: The group2 pins are PD1, PE8, PE1, and PD11.
22
1
read-write
0
Toggle output pins group 2 Enabled
#0
1
Toggle output pins group 2 Disabled
#1
WKEN
Wake-Up Enable\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled if timer interrupt signal generated
#0
1
Wake-up trigger event Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-Bounce Enable\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce Enabled
#1
CAPEDGE
Timer External Pin Edge Detect\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#10
3
Reserved
#11
CAPEN
Timer External Pin Enable \nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin. \n
3
1
read-write
0
CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored
#0
1
CAPFUNCS function of TMx_EXT (x= 0~3) pin is active
#1
CAPFUNCS
Timer External Reset Counter / Capture Mode Select\n
4
1
read-write
0
Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value
#0
1
Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value
#1
CAPIEN
Timer External Interrupt Enable\n
5
1
read-write
0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-Bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TIMERx_CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or power-down mode if timer time-out interrupt signal generated
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Compare Register
0x24
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control and Status Register
0x20
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x34
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x48
registers
n
UART_ALTCTL
UART_ALTCTL
UARTx Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LINRXEN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
0
4
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection (AAD) Operation mode Disabled
#0
1
RS-485 Auto Address Detection (AAD) Operation mode Enabled
#1
RS485AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation (AUO) mode Disabled
#0
1
RS-485 Auto Direction Operation (AUO) mode Enabled
#1
RS485NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UARTx Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal To 1
Refer to the table below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must = 3)
#1
BAUDM1
Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#1
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UARTx Receive / Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
0
8
read-write
UART_FIFO
UART_FIFO
UARTx FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control Use\n
16
4
read-write
RXOFF
Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UARTx FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
3
1
read-only
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
4
1
read-only
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
15
1
read-only
RXOVIF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
0
1
read-only
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
8
6
read-only
SCERR
Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
2
1
read-write
0
No any transmitter re-transmits over or receiver transfer error retry over
#0
1
one of the transmitter re-transmits over active or receiver transfer error retry over active
#1
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
23
1
read-only
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
24
1
read-only
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UARTx Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select Enable Bit\n
0
3
read-write
0
UART function
#000
1
LIN function Enabled
#001
2
IrDA function Enabled
#010
3
RS-485 function Enabled
#011
4
Smart-Card function Enabled
#100
UART_INTEN
UART_INTEN
UARTx Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
INT_BUF_ERR Disabled
#0
1
INT_BUF_ERR Enabled
#1
LINIEN
LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus RX break filed interrupt Disabled
#0
1
Lin bus RX break filed interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
INT_MODEM Disabled
#0
1
INT_MODEM Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
INT_RDA Disabled
#0
1
INT_RDA Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit \n
2
1
read-write
0
INT_RLS Disabled
#0
1
INT_RLS Enabled
#1
RXPDMAEN
RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTOIEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
NT_TOUT Disabled
#0
1
INT_TOUT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
INT_THRE Disabled
#0
1
INT_THRE Enabled
#1
TOCNTEN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TXPDMAEN
TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
WKCTSIEN
UART Wake-Up Function Enable Bit\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UARTx Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
HWBUFEIF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
21
1
read-only
HWBUFEINT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
The buffer error interrupt is generated in DMA mode
#1
HWMODIF
In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
19
1
read-only
HWMODINT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN and HWMODIF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HWRLSIF
In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HWRLSINT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HWTOIF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
HWTOINT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LINIF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
7
1
read-only
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
LIN RX Break interrupt is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
MODENIF
MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
RXTOINT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
1
1
read-only
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UARTx IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
FIXPULSE
Pulse width of TX is fixed 1.6us.
7
1
read-write
RXINV
IrDA Inverse Receive Input Signal\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal\n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UARTx LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
20
2
read-write
0
LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
HSEL
LIN Header Selection\n
22
2
read-write
0
LIN header includes break field
#00
1
LIN header includes break field and sync field
#01
2
LIN header includes break field , sync field and frame ID field
#10
3
LIN header includes break field , sync field and frame ID field , but this mode only supports Receiver mode, not support transmitter mode. This mode difference with mode 10 in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set)
#11
IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
4
1
read-write
0
LIN mute mode. Disabled
#0
1
LIN mute mode Enabled
#1
PID
This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
None
11
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
SENDH
LIN TX Send Header Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINDEBUG
UART_LINDEBUG
UARTx LIN Debug Register
0x3C
read-write
n
0x0
0x0
DEVERRF
LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
0
1
read-only
FRAMEERRF
LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
2
1
read-only
SYNCERRF
LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
3
1
read-only
TOF
LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
1
1
read-only
UART_LINE
UART_LINE
UARTx Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UART_LINSTS
UART_LINSTS
UARTx LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UARTx Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
RTS (Request-To-Send) Signal \n
1
1
read-write
0
Drive RTS pin to logic 1 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 0 (If the RTSACTLV set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 1 (If the RTSACTLV set to high level triggered)
#1
RTSACTLV
RTS Trigger Level \nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSSTS
RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UARTx Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
CTS Trigger Level \nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
CTSDETF
Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
0
1
read-only
CTSSTS
CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
4
1
read-only
UART_SCCTL
UART_SCCTL
UARTx SC Control Register
0x40
read-write
n
0x0
0x0
UART_SCSTATUS
UART_SCSTATUS
UARTx SC Flag Status Register
0x44
read-write
n
0x0
0x0
UART_TOUT
UART_TOUT
UARTx Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x48
registers
n
UART_ALTCTL
UART_ALTCTL
UARTx Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LINRXEN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
0
4
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection (AAD) Operation mode Disabled
#0
1
RS-485 Auto Address Detection (AAD) Operation mode Enabled
#1
RS485AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation (AUO) mode Disabled
#0
1
RS-485 Auto Direction Operation (AUO) mode Enabled
#1
RS485NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UARTx Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal To 1
Refer to the table below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must = 3)
#1
BAUDM1
Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#1
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UARTx Receive / Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
0
8
read-write
UART_FIFO
UART_FIFO
UARTx FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control Use\n
16
4
read-write
RXOFF
Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UARTx FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
3
1
read-only
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
4
1
read-only
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
15
1
read-only
RXOVIF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
0
1
read-only
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
8
6
read-only
SCERR
Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
2
1
read-write
0
No any transmitter re-transmits over or receiver transfer error retry over
#0
1
one of the transmitter re-transmits over active or receiver transfer error retry over active
#1
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
23
1
read-only
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
24
1
read-only
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UARTx Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select Enable Bit\n
0
3
read-write
0
UART function
#000
1
LIN function Enabled
#001
2
IrDA function Enabled
#010
3
RS-485 function Enabled
#011
4
Smart-Card function Enabled
#100
UART_INTEN
UART_INTEN
UARTx Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
INT_BUF_ERR Disabled
#0
1
INT_BUF_ERR Enabled
#1
LINIEN
LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus RX break filed interrupt Disabled
#0
1
Lin bus RX break filed interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
INT_MODEM Disabled
#0
1
INT_MODEM Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
INT_RDA Disabled
#0
1
INT_RDA Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit \n
2
1
read-write
0
INT_RLS Disabled
#0
1
INT_RLS Enabled
#1
RXPDMAEN
RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTOIEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
NT_TOUT Disabled
#0
1
INT_TOUT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
INT_THRE Disabled
#0
1
INT_THRE Enabled
#1
TOCNTEN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TXPDMAEN
TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
WKCTSIEN
UART Wake-Up Function Enable Bit\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UARTx Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
HWBUFEIF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
21
1
read-only
HWBUFEINT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
The buffer error interrupt is generated in DMA mode
#1
HWMODIF
In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
19
1
read-only
HWMODINT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN and HWMODIF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HWRLSIF
In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HWRLSINT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HWTOIF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
HWTOINT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LINIF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
7
1
read-only
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
LIN RX Break interrupt is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
MODENIF
MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
RXTOINT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
1
1
read-only
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UARTx IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
FIXPULSE
Pulse width of TX is fixed 1.6us.
7
1
read-write
RXINV
IrDA Inverse Receive Input Signal\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal\n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UARTx LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
20
2
read-write
0
LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
HSEL
LIN Header Selection\n
22
2
read-write
0
LIN header includes break field
#00
1
LIN header includes break field and sync field
#01
2
LIN header includes break field , sync field and frame ID field
#10
3
LIN header includes break field , sync field and frame ID field , but this mode only supports Receiver mode, not support transmitter mode. This mode difference with mode 10 in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set)
#11
IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
4
1
read-write
0
LIN mute mode. Disabled
#0
1
LIN mute mode Enabled
#1
PID
This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
None
11
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
SENDH
LIN TX Send Header Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINDEBUG
UART_LINDEBUG
UARTx LIN Debug Register
0x3C
read-write
n
0x0
0x0
DEVERRF
LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
0
1
read-only
FRAMEERRF
LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
2
1
read-only
SYNCERRF
LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
3
1
read-only
TOF
LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
1
1
read-only
UART_LINE
UART_LINE
UARTx Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UART_LINSTS
UART_LINSTS
UARTx LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UARTx Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
RTS (Request-To-Send) Signal \n
1
1
read-write
0
Drive RTS pin to logic 1 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 0 (If the RTSACTLV set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 1 (If the RTSACTLV set to high level triggered)
#1
RTSACTLV
RTS Trigger Level \nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSSTS
RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UARTx Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
CTS Trigger Level \nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
CTSDETF
Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
0
1
read-only
CTSSTS
CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
4
1
read-only
UART_SCCTL
UART_SCCTL
UARTx SC Control Register
0x40
read-write
n
0x0
0x0
UART_SCSTATUS
UART_SCSTATUS
UARTx SC Flag Status Register
0x44
read-write
n
0x0
0x0
UART_TOUT
UART_TOUT
UARTx Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART2
UART Register Map
UART
0x0
0x0
0x48
registers
n
UART_ALTCTL
UART_ALTCTL
UARTx Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LINRXEN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
0
4
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection (AAD) Operation mode Disabled
#0
1
RS-485 Auto Address Detection (AAD) Operation mode Enabled
#1
RS485AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation (AUO) mode Disabled
#0
1
RS-485 Auto Direction Operation (AUO) mode Enabled
#1
RS485NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UARTx Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal To 1
Refer to the table below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must = 3)
#1
BAUDM1
Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#1
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UARTx Receive / Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
0
8
read-write
UART_FIFO
UART_FIFO
UARTx FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control Use\n
16
4
read-write
RXOFF
Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UARTx FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
3
1
read-only
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
4
1
read-only
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
15
1
read-only
RXOVIF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
0
1
read-only
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
8
6
read-only
SCERR
Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
2
1
read-write
0
No any transmitter re-transmits over or receiver transfer error retry over
#0
1
one of the transmitter re-transmits over active or receiver transfer error retry over active
#1
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
23
1
read-only
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
24
1
read-only
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UARTx Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select Enable Bit\n
0
3
read-write
0
UART function
#000
1
LIN function Enabled
#001
2
IrDA function Enabled
#010
3
RS-485 function Enabled
#011
4
Smart-Card function Enabled
#100
UART_INTEN
UART_INTEN
UARTx Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
INT_BUF_ERR Disabled
#0
1
INT_BUF_ERR Enabled
#1
LINIEN
LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus RX break filed interrupt Disabled
#0
1
Lin bus RX break filed interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
INT_MODEM Disabled
#0
1
INT_MODEM Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
INT_RDA Disabled
#0
1
INT_RDA Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit \n
2
1
read-write
0
INT_RLS Disabled
#0
1
INT_RLS Enabled
#1
RXPDMAEN
RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTOIEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
NT_TOUT Disabled
#0
1
INT_TOUT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
INT_THRE Disabled
#0
1
INT_THRE Enabled
#1
TOCNTEN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TXPDMAEN
TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
WKCTSIEN
UART Wake-Up Function Enable Bit\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UARTx Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
HWBUFEIF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
21
1
read-only
HWBUFEINT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
The buffer error interrupt is generated in DMA mode
#1
HWMODIF
In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
19
1
read-only
HWMODINT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN and HWMODIF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HWRLSIF
In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HWRLSINT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HWTOIF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
HWTOINT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LINIF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
7
1
read-only
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
LIN RX Break interrupt is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
MODENIF
MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
RXTOINT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
1
1
read-only
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UARTx IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
FIXPULSE
Pulse width of TX is fixed 1.6us.
7
1
read-write
RXINV
IrDA Inverse Receive Input Signal\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal\n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UARTx LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
20
2
read-write
0
LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
HSEL
LIN Header Selection\n
22
2
read-write
0
LIN header includes break field
#00
1
LIN header includes break field and sync field
#01
2
LIN header includes break field , sync field and frame ID field
#10
3
LIN header includes break field , sync field and frame ID field , but this mode only supports Receiver mode, not support transmitter mode. This mode difference with mode 10 in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set)
#11
IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
4
1
read-write
0
LIN mute mode. Disabled
#0
1
LIN mute mode Enabled
#1
PID
This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
None
11
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
SENDH
LIN TX Send Header Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINDEBUG
UART_LINDEBUG
UARTx LIN Debug Register
0x3C
read-write
n
0x0
0x0
DEVERRF
LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
0
1
read-only
FRAMEERRF
LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
2
1
read-only
SYNCERRF
LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
3
1
read-only
TOF
LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
1
1
read-only
UART_LINE
UART_LINE
UARTx Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UART_LINSTS
UART_LINSTS
UARTx LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UARTx Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
RTS (Request-To-Send) Signal \n
1
1
read-write
0
Drive RTS pin to logic 1 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 0 (If the RTSACTLV set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 1 (If the RTSACTLV set to high level triggered)
#1
RTSACTLV
RTS Trigger Level \nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSSTS
RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UARTx Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
CTS Trigger Level \nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
CTSDETF
Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
0
1
read-only
CTSSTS
CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
4
1
read-only
UART_SCCTL
UART_SCCTL
UARTx SC Control Register
0x40
read-write
n
0x0
0x0
UART_SCSTATUS
UART_SCSTATUS
UARTx SC Flag Status Register
0x44
read-write
n
0x0
0x0
UART_TOUT
UART_TOUT
UARTx Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART3
UART Register Map
UART
0x0
0x0
0x48
registers
n
UART_ALTCTL
UART_ALTCTL
UARTx Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LINRXEN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
0
4
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection (AAD) Operation mode Disabled
#0
1
RS-485 Auto Address Detection (AAD) Operation mode Enabled
#1
RS485AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation (AUO) mode Disabled
#0
1
RS-485 Auto Direction Operation (AUO) mode Enabled
#1
RS485NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UARTx Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal To 1
Refer to the table below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must = 3)
#1
BAUDM1
Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#1
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UARTx Receive / Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
0
8
read-write
UART_FIFO
UART_FIFO
UARTx FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control Use\n
16
4
read-write
RXOFF
Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UARTx FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
3
1
read-only
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
4
1
read-only
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
15
1
read-only
RXOVIF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
0
1
read-only
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
8
6
read-only
SCERR
Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
2
1
read-write
0
No any transmitter re-transmits over or receiver transfer error retry over
#0
1
one of the transmitter re-transmits over active or receiver transfer error retry over active
#1
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
23
1
read-only
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
24
1
read-only
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UARTx Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select Enable Bit\n
0
3
read-write
0
UART function
#000
1
LIN function Enabled
#001
2
IrDA function Enabled
#010
3
RS-485 function Enabled
#011
4
Smart-Card function Enabled
#100
UART_INTEN
UART_INTEN
UARTx Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
INT_BUF_ERR Disabled
#0
1
INT_BUF_ERR Enabled
#1
LINIEN
LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus RX break filed interrupt Disabled
#0
1
Lin bus RX break filed interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
INT_MODEM Disabled
#0
1
INT_MODEM Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
INT_RDA Disabled
#0
1
INT_RDA Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit \n
2
1
read-write
0
INT_RLS Disabled
#0
1
INT_RLS Enabled
#1
RXPDMAEN
RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTOIEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
NT_TOUT Disabled
#0
1
INT_TOUT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
INT_THRE Disabled
#0
1
INT_THRE Enabled
#1
TOCNTEN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TXPDMAEN
TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
WKCTSIEN
UART Wake-Up Function Enable Bit\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UARTx Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
HWBUFEIF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
21
1
read-only
HWBUFEINT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
The buffer error interrupt is generated in DMA mode
#1
HWMODIF
In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
19
1
read-only
HWMODINT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN and HWMODIF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HWRLSIF
In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HWRLSINT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HWTOIF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
HWTOINT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LINIF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
7
1
read-only
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
LIN RX Break interrupt is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
MODENIF
MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
RXTOINT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
1
1
read-only
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UARTx IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
FIXPULSE
Pulse width of TX is fixed 1.6us.
7
1
read-write
RXINV
IrDA Inverse Receive Input Signal\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal\n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UARTx LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
20
2
read-write
0
LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
HSEL
LIN Header Selection\n
22
2
read-write
0
LIN header includes break field
#00
1
LIN header includes break field and sync field
#01
2
LIN header includes break field , sync field and frame ID field
#10
3
LIN header includes break field , sync field and frame ID field , but this mode only supports Receiver mode, not support transmitter mode. This mode difference with mode 10 in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set)
#11
IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
4
1
read-write
0
LIN mute mode. Disabled
#0
1
LIN mute mode Enabled
#1
PID
This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
None
11
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
SENDH
LIN TX Send Header Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINDEBUG
UART_LINDEBUG
UARTx LIN Debug Register
0x3C
read-write
n
0x0
0x0
DEVERRF
LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
0
1
read-only
FRAMEERRF
LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
2
1
read-only
SYNCERRF
LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
3
1
read-only
TOF
LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
1
1
read-only
UART_LINE
UART_LINE
UARTx Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UART_LINSTS
UART_LINSTS
UARTx LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UARTx Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
RTS (Request-To-Send) Signal \n
1
1
read-write
0
Drive RTS pin to logic 1 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 0 (If the RTSACTLV set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 1 (If the RTSACTLV set to high level triggered)
#1
RTSACTLV
RTS Trigger Level \nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSSTS
RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UARTx Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
CTS Trigger Level \nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
CTSDETF
Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
0
1
read-only
CTSSTS
CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
4
1
read-only
UART_SCCTL
UART_SCCTL
UARTx SC Control Register
0x40
read-write
n
0x0
0x0
UART_SCSTATUS
UART_SCSTATUS
UARTx SC Flag Status Register
0x44
read-write
n
0x0
0x0
UART_TOUT
UART_TOUT
UARTx Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART4
UART Register Map
UART
0x0
0x0
0x48
registers
n
UART_ALTCTL
UART_ALTCTL
UARTx Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LINRXEN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
0
4
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection (AAD) Operation mode Disabled
#0
1
RS-485 Auto Address Detection (AAD) Operation mode Enabled
#1
RS485AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation (AUO) mode Disabled
#0
1
RS-485 Auto Direction Operation (AUO) mode Enabled
#1
RS485NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UARTx Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal To 1
Refer to the table below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must = 3)
#1
BAUDM1
Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#1
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UARTx Receive / Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
0
8
read-write
UART_FIFO
UART_FIFO
UARTx FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control Use\n
16
4
read-write
RXOFF
Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UARTx FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
3
1
read-only
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
4
1
read-only
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
15
1
read-only
RXOVIF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
0
1
read-only
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
8
6
read-only
SCERR
Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
2
1
read-write
0
No any transmitter re-transmits over or receiver transfer error retry over
#0
1
one of the transmitter re-transmits over active or receiver transfer error retry over active
#1
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
23
1
read-only
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
24
1
read-only
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UARTx Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select Enable Bit\n
0
3
read-write
0
UART function
#000
1
LIN function Enabled
#001
2
IrDA function Enabled
#010
3
RS-485 function Enabled
#011
4
Smart-Card function Enabled
#100
UART_INTEN
UART_INTEN
UARTx Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
INT_BUF_ERR Disabled
#0
1
INT_BUF_ERR Enabled
#1
LINIEN
LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus RX break filed interrupt Disabled
#0
1
Lin bus RX break filed interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
INT_MODEM Disabled
#0
1
INT_MODEM Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
INT_RDA Disabled
#0
1
INT_RDA Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit \n
2
1
read-write
0
INT_RLS Disabled
#0
1
INT_RLS Enabled
#1
RXPDMAEN
RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTOIEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
NT_TOUT Disabled
#0
1
INT_TOUT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
INT_THRE Disabled
#0
1
INT_THRE Enabled
#1
TOCNTEN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TXPDMAEN
TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
WKCTSIEN
UART Wake-Up Function Enable Bit\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UARTx Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
HWBUFEIF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
21
1
read-only
HWBUFEINT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
The buffer error interrupt is generated in DMA mode
#1
HWMODIF
In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
19
1
read-only
HWMODINT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN and HWMODIF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HWRLSIF
In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HWRLSINT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HWTOIF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
HWTOINT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LINIF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
7
1
read-only
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
LIN RX Break interrupt is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
MODENIF
MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
RXTOINT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
1
1
read-only
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UARTx IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
FIXPULSE
Pulse width of TX is fixed 1.6us.
7
1
read-write
RXINV
IrDA Inverse Receive Input Signal\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal\n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UARTx LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
20
2
read-write
0
LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
HSEL
LIN Header Selection\n
22
2
read-write
0
LIN header includes break field
#00
1
LIN header includes break field and sync field
#01
2
LIN header includes break field , sync field and frame ID field
#10
3
LIN header includes break field , sync field and frame ID field , but this mode only supports Receiver mode, not support transmitter mode. This mode difference with mode 10 in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set)
#11
IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
4
1
read-write
0
LIN mute mode. Disabled
#0
1
LIN mute mode Enabled
#1
PID
This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
None
11
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
SENDH
LIN TX Send Header Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINDEBUG
UART_LINDEBUG
UARTx LIN Debug Register
0x3C
read-write
n
0x0
0x0
DEVERRF
LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
0
1
read-only
FRAMEERRF
LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
2
1
read-only
SYNCERRF
LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
3
1
read-only
TOF
LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
1
1
read-only
UART_LINE
UART_LINE
UARTx Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UART_LINSTS
UART_LINSTS
UARTx LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UARTx Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
RTS (Request-To-Send) Signal \n
1
1
read-write
0
Drive RTS pin to logic 1 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 0 (If the RTSACTLV set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 1 (If the RTSACTLV set to high level triggered)
#1
RTSACTLV
RTS Trigger Level \nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSSTS
RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UARTx Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
CTS Trigger Level \nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
CTSDETF
Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
0
1
read-only
CTSSTS
CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
4
1
read-only
UART_SCCTL
UART_SCCTL
UARTx SC Control Register
0x40
read-write
n
0x0
0x0
UART_SCSTATUS
UART_SCSTATUS
UARTx SC Flag Status Register
0x44
read-write
n
0x0
0x0
UART_TOUT
UART_TOUT
UARTx Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
UART5
UART Register Map
UART
0x0
0x0
0x48
registers
n
UART_ALTCTL
UART_ALTCTL
UARTx Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ADDRDEN
RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LINRXEN
LIN RX Enable Bit\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
0
4
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection (AAD) Operation mode Disabled
#0
1
RS-485 Auto Address Detection (AAD) Operation mode Enabled
#1
RS485AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation (AUO) mode Disabled
#0
1
RS-485 Auto Direction Operation (AUO) mode Enabled
#1
RS485NMM
RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation Mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation Mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UARTx Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal To 1
Refer to the table below for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must = 3)
#1
BAUDM1
Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must = 8)
#1
BRD
Baud Rate Divider\nThe field indicated the baud rate divider
0
16
read-write
EDIVM1
Divider X\n
24
4
read-write
UART_DAT
UART_DAT
UARTx Receive / Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
0
8
read-write
UART_FIFO
UART_FIFO
UARTx FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control Use\n
16
4
read-write
RXOFF
Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UARTx FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ADDRDETF
RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
3
1
read-only
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing '1' to it.
4
1
read-only
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
15
1
read-only
RXOVIF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
0
1
read-only
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
8
6
read-only
SCERR
Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
2
1
read-write
0
No any transmitter re-transmits over or receiver transfer error retry over
#0
1
one of the transmitter re-transmits over active or receiver transfer error retry over active
#1
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
23
1
read-only
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
24
1
read-only
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UARTx Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select Enable Bit\n
0
3
read-write
0
UART function
#000
1
LIN function Enabled
#001
2
IrDA function Enabled
#010
3
RS-485 function Enabled
#011
4
Smart-Card function Enabled
#100
UART_INTEN
UART_INTEN
UARTx Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
13
1
read-write
0
CTS auto flow control Disabled
#0
1
CTS auto flow control Enabled
#1
ATORTSEN
RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
12
1
read-write
0
RTS auto flow control Disabled
#0
1
RTS auto flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit\n
5
1
read-write
0
INT_BUF_ERR Disabled
#0
1
INT_BUF_ERR Enabled
#1
LINIEN
LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus RX break filed interrupt Disabled
#0
1
Lin bus RX break filed interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit\n
3
1
read-write
0
INT_MODEM Disabled
#0
1
INT_MODEM Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit\n
0
1
read-write
0
INT_RDA Disabled
#0
1
INT_RDA Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit \n
2
1
read-write
0
INT_RLS Disabled
#0
1
INT_RLS Enabled
#1
RXPDMAEN
RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXTOIEN
RX Time-Out Interrupt Enable Bit\n
4
1
read-write
0
NT_TOUT Disabled
#0
1
INT_TOUT Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit\n
1
1
read-write
0
INT_THRE Disabled
#0
1
INT_THRE Enabled
#1
TOCNTEN
Time-Out Counter Enable Bit\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TXPDMAEN
TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
WKCTSIEN
UART Wake-Up Function Enable Bit\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UARTx Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
The buffer error interrupt is generated
#1
HWBUFEIF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
21
1
read-only
HWBUFEINT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
The buffer error interrupt is generated in DMA mode
#1
HWMODIF
In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
19
1
read-only
HWMODINT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN and HWMODIF are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HWRLSIF
In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HWRLSINT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HWTOIF
In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
HWTOINT
In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LINIF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
7
1
read-only
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
15
1
read-only
0
No LIN RX Break interrupt is generated
#0
1
LIN RX Break interrupt is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
MODENIF
MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note2: In SC function mode, this field includes error retry over flag .
Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
RXTOINT
Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
1
1
read-only
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
UART_IRDA
UART_IRDA
UARTx IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
FIXPULSE
Pulse width of TX is fixed 1.6us.
7
1
read-write
RXINV
IrDA Inverse Receive Input Signal\n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal\n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UARTx LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
20
2
read-write
0
LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
HSEL
LIN Header Selection\n
22
2
read-write
0
LIN header includes break field
#00
1
LIN header includes break field and sync field
#01
2
LIN header includes break field , sync field and frame ID field
#10
3
LIN header includes break field , sync field and frame ID field , but this mode only supports Receiver mode, not support transmitter mode. This mode difference with mode 10 in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set)
#11
IDPEN
LIN ID Parity Enable Bit\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
4
1
read-write
0
LIN mute mode. Disabled
#0
1
LIN mute mode Enabled
#1
PID
This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
None
11
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
SENDH
LIN TX Send Header Enable Bit
The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register.
Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINDEBUG
UART_LINDEBUG
UARTx LIN Debug Register
0x3C
read-write
n
0x0
0x0
DEVERRF
LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
0
1
read-only
FRAMEERRF
LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
2
1
read-only
SYNCERRF
LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
3
1
read-only
TOF
LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
1
1
read-only
UART_LINE
UART_LINE
UARTx Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number Of STOP Bit
Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable Bit\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable Bit\n
5
1
read-write
0
Stick parity Disabled
#0
1
If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UART_LINSTS
UART_LINSTS
UARTx LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UARTx Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
RTS (Request-To-Send) Signal \n
1
1
read-write
0
Drive RTS pin to logic 1 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 0 (If the RTSACTLV set to high level triggered)
#0
1
Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).\nDrive RTS pin to logic 1 (If the RTSACTLV set to high level triggered)
#1
RTSACTLV
RTS Trigger Level \nThis bit can change the RTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSSTS
RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UARTx Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
CTS Trigger Level \nThis bit can change the CTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
CTSDETF
Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
0
1
read-only
CTSSTS
CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
4
1
read-only
UART_SCCTL
UART_SCCTL
UARTx SC Control Register
0x40
read-write
n
0x0
0x0
UART_SCSTATUS
UART_SCSTATUS
UARTx SC Flag Status Register
0x44
read-write
n
0x0
0x0
UART_TOUT
UART_TOUT
UARTx Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
8
8
read-write
TOIC
Time-Out Interrupt Comparator\n
0
8
read-write
USBD
USBD Register Map
USBD
0x0
0x0
0x4
registers
n
0x10
0x234
registers
n
0x700
0x8
registers
n
0x8
0x4
registers
n
BUSINTEN
USBD_BUSINTEN
USB Bus Interrupt Enable Register
0x14
-1
read-write
n
0x0
0x0
DMADONEIEN
DMA Completion Interrupt \nThis bit enables the DMA completion interrupt\n
5
1
read-write
0
DMA completion interrupt Disabled
#0
1
DMA completion interrupt Enabled
#1
HISPDIEN
High-Speed Settle \nThis bit enables the high-speed settle interrupt.\n
4
1
read-write
0
High-speed settle interrupt Disabled
#0
1
High-speed settle interrupt Enabled
#1
PHYCLKVLDIEN
Usable Clock Interrupt\nThis bit enables the usable clock interrupt.\n
6
1
read-write
0
Usable clock interrupt Disabled
#0
1
Usable clock interrupt Enabled
#1
RESUMEIEN
Resume \nThis bit enables the Resume interrupt.\n
2
1
read-write
0
Resume interrupt Disabled
#0
1
Resume interrupt Enabled
#1
RSTIEN
Reset Status \nThis bit enables the USB-Reset interrupt.\n
1
1
read-write
0
USB-Reset interrupt Disabled
#0
1
USB-Reset interrupt Enabled
#1
SOFIEN
SOF Interrupt\nThis bit enables the SOF interrupt.\n
0
1
read-write
0
SOF interrupt Disabled
#0
1
SOF interrupt Enabled
#1
SUSPENDIEN
Suspend Request \nThis bit enables the Suspend interrupt.\n
3
1
read-write
0
Suspend interrupt Disabled
#0
1
Suspend interrupt Enabled
#1
VBUSDETIEN
VBUS Detection Interrupt Enable Bit\nThis bit enables the VBUS floating detection interrupt.\n
8
1
read-write
0
VBUS floating detection interrupt Disabled
#0
1
VBUS floating detection interrupt Enabled
#1
BUSINTSTS
USBD_BUSINTSTS
USB Bus Interrupt Status Register
0x10
read-write
n
0x0
0x0
DMADONEIF
DMA Completion Interrupt \nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
No DMA transfer over
#0
1
DMA transfer is over
#1
HISPDIF
High-Speed Settle \nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
No valid high-speed reset protocol is detected
#0
1
Valid high-speed reset protocol is over and the device has settled in high-speed
#1
PHYCLKVLDIF
Usable Clock Interrupt \nNote: Write 1 to clear this bit to 0.
6
1
read-write
0
Usable clock is not available
#0
1
Usable clock is available from the transceiver
#1
RESUMEIF
Resume \nWhen set, this bit indicates that a device resume has occurred.\nNote: Write 1 to clear this bit to 0.
2
1
read-write
0
No device resume has occurred
#0
1
Device resume has occurred
#1
RSTIF
Reset Status \nWhen set, this bit indicates that either the USB root port reset is end.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
No USB root port reset is end
#0
1
USB root port reset is end
#1
SOFIF
SOF Receive Control\nThis bit indicates when a start-of-frame packet has been received. \nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
No start-of-frame packet has been received
#0
1
Start-of-frame packet has been received
#1
SUSPENDIF
Suspend Request \nThis bit is set as default and it has to be cleared by writing '1' before the USB reset. This bit is also set when a USB Suspend request is detected from the host. \nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
No USB Suspend request is detected from the host
#0
1
USB Suspend request is detected from the host
#1
VBUSDETIF
VBUS Detection Interrupt Status \nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
No VBUS is plug-in
#0
1
VBUS is plug-in
#1
CEPBUFEND
USBD_CEPBUFEND
Control Endpoint RAM End Address Register
0x58
read-write
n
0x0
0x0
EADDR
Control-Endpoint End Address\nThis is the end-address of the RAM space allocated for the control-endpoint.
0
12
read-write
CEPBUFSTART
USBD_CEPBUFSTART
Control Endpoint RAM Start Address Register
0x54
read-write
n
0x0
0x0
SADDR
Control-Endpoint Start Address\nThis is the start-address of the RAM space allocated for the control-endpoint.
0
12
read-write
CEPCTL
USBD_CEPCTL
Control-endpoint Control and Status
0x2C
read-write
n
0x0
0x0
FLUSH
CEP-FLUSH Bit \n
3
1
read-write
0
No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared
#0
1
The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. This bit is self-cleaning
#1
NAKCLR
No Acknowledge Control\nThis bit plays a crucial role in any control transfer. \nNote: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
0
1
read-write
0
The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase. This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request
#0
1
This bit is set to one by the USB device controller, whenever a setup token is received. The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit
#1
STALLEN
Stall Enable Bit\nWhen this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter. This is typically used for response to invalid/unsupported requests. When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL. It is automatically cleared on receipt of a next setup-token. So, the local CPU need not write again to clear this bit.\nNote: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
1
1
read-write
0
No sends a stall handshake in response to any in or out token thereafter
#0
1
The control endpoint sends a stall handshake in response to any in or out token thereafter
#1
ZEROLEN
Zero Packet Length\nThis bit is valid for Auto Validation mode only. \n
2
1
read-write
0
No zero length packet to the host during Data stage to an IN token
#0
1
USB device controller can send a zero length packet to the host during Data stage to an IN token. This bit gets cleared once the zero length data packet is sent. So, the local CPU need not write again to clear this bit
#1
CEPDAT
USBD_CEPDAT
Control-endpoint Data Buffer
0x28
read-write
n
0x0
0x0
DAT
Control-Endpoint Data Buffer \nControl endpoint data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported.
0
32
read-write
CEPDATCNT
USBD_CEPDATCNT
Control-endpoint Data Count
0x40
read-only
n
0x0
0x0
DATCNT
Control-Endpoint Data Count \nThe USB device controller maintains the count of the data of control-endpoint.
0
16
read-only
CEPINTEN
USBD_CEPINTEN
Control-endpoint Interrupt Enable
0x30
read-write
n
0x0
0x0
BUFEMPTYIEN
Buffer Empty Interrupt \n
12
1
read-write
0
The buffer empty interrupt in Control Endpoint Disabled
#0
1
The buffer empty interrupt in Control Endpoint Enabled
#1
BUFFULLIEN
Buffer Full Interrupt \n
11
1
read-write
0
The buffer full interrupt in Control Endpoint Disabled
#0
1
The buffer full interrupt in Control Endpoint Enabled
#1
ERRIEN
USB Error Interrupt \n
9
1
read-write
0
The USB Error interrupt in Control Endpoint Disabled
#0
1
The USB Error interrupt in Control Endpoint Enabled
#1
INTKIEN
In Token Interrupt \n
3
1
read-write
0
The IN token interrupt in Control Endpoint Disabled
#0
1
The IN token interrupt in Control Endpoint Enabled
#1
NAKIEN
NAK Sent Interrupt \n
7
1
read-write
0
The NAK sent interrupt in Control Endpoint Disabled
#0
1
The NAK sent interrupt in Control Endpoint Enabled
#1
OUTTKIEN
Out Token Interrupt \n
2
1
read-write
0
The OUT token interrupt in Control Endpoint Disabled
#0
1
The OUT token interrupt in Control Endpoint Enabled
#1
PINGIEN
Ping Token Interrupt \n
4
1
read-write
0
The ping token interrupt in Control Endpoint Disabled
#0
1
The ping token interrupt Control Endpoint Enabled
#1
RXPKIEN
Data Packet Received Interrupt \n
6
1
read-write
0
The data received interrupt in Control Endpoint Disabled
#0
1
The data received interrupt in Control Endpoint Enabled
#1
SETUPPKIEN
Setup Packet Interrupt \n
1
1
read-write
0
The SETUP packet interrupt in Control Endpoint Disabled
#0
1
The SETUP packet interrupt in Control Endpoint Enabled
#1
SETUPTKIEN
Setup Token Interrupt Enable Bit \n
0
1
read-write
0
The SETUP token interrupt in Control Endpoint Disabled
#0
1
The SETUP token interrupt in Control Endpoint Enabled
#1
STALLIEN
STALL Sent Interrupt \n
8
1
read-write
0
The STALL sent interrupt in Control Endpoint Disabled
#0
1
The STALL sent interrupt in Control Endpoint Enabled
#1
STSDONEIEN
Status Completion Interrupt \n
10
1
read-write
0
The Status Completion interrupt in Control Endpoint Disabled
#0
1
The Status Completion interrupt in Control Endpoint Enabled
#1
TXPKIEN
Data Packet Transmitted Interrupt \n
5
1
read-write
0
The data packet transmitted interrupt in Control Endpoint Disabled
#0
1
The data packet transmitted interrupt in Control Endpoint Enabled
#1
CEPINTSTS
USBD_CEPINTSTS
Control-endpoint Interrupt Status
0x34
-1
read-write
n
0x0
0x0
BUFEMPTYIF
Buffer Empty Interrupt \nNote: Write 1 to clear this bit to 0.
12
1
read-write
0
The control-endpoint buffer is not empty
#0
1
The control-endpoint buffer is empty
#1
BUFFULLIF
Buffer Full Interrupt \nNote: Write 1 to clear this bit to 0.
11
1
read-write
0
The control-endpoint buffer is not full
#0
1
The control-endpoint buffer is full
#1
ERRIF
USB Error Interrupt\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No error had occurred during the transaction
#0
1
An error had occurred during the transaction
#1
INTKIF
In Token Interrupt \nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
The control-endpoint does not received an IN token from the host
#0
1
The control-endpoint receives an IN token from the host
#1
NAKIF
NAK Sent Interrupt \nNote: Write 1 to clear this bit to 0.
7
1
read-write
0
Not a NAK-token is sent in response to an IN/OUT token
#0
1
A NAK-token is sent in response to an IN/OUT token
#1
OUTTKIF
Out Token Interrupt \nNote: Write 1 to clear this bit to 0.
2
1
read-write
0
The control-endpoint does not received an OUT token from the host
#0
1
The control-endpoint receives an OUT token from the host
#1
PINGIF
Ping Token Interrupt \nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
The control-endpoint does not received a ping token from the host
#0
1
The control-endpoint receives a ping token from the host
#1
RXPKIF
Data Packet Received Interrupt \nNote: Write 1 to clear this bit to 0.
6
1
read-write
0
Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host
#0
1
A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host
#1
SETUPPKIF
Setup Packet Interrupt \nThis bit must be cleared (by writing 1) before the next setup packet can be received. If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
Not a Setup packet has been received from the host
#0
1
A Setup packet has been received from the host
#1
SETUPTKIF
Setup Token Interrupt \nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
Not a Setup token is received
#0
1
A Setup token is received. Writing 1 clears this status bit
#1
STALLIF
STALL Sent Interrupt \nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
Not a stall-token is sent in response to an IN/OUT token
#0
1
A stall-token is sent in response to an IN/OUT token
#1
STSDONEIF
Status Completion Interrupt \nNote: Write 1 to clear this bit to 0.
10
1
read-write
0
Not a USB transaction has completed successfully
#0
1
The status stage of a USB transaction has completed successfully
#1
TXPKIF
Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same
#0
1
A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same
#1
CEPRXCNT
USBD_CEPRXCNT
Control-endpoint Out-transfer Data Count
0x3C
read-only
n
0x0
0x0
RXCNT
Out-Transfer Data Count \nThe USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
0
8
read-only
CEPTXCNT
USBD_CEPTXCNT
Control-endpoint In-transfer Data Count
0x38
read-write
n
0x0
0x0
TXCNT
In-Transfer Data Count\nThere is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register. When zero is written into this field, a zero length packet is sent to the host. When the count written in the register is more than the MPS, the data sent will be of only MPS.
0
8
read-write
DMAADDR
USBD_DMAADDR
AHB DMA Address Register
0x700
read-write
n
0x0
0x0
DMAADDR
DMAADDR\nThe register specifies the address from which the DMA has to read / write. The address must WORD (32-bit) aligned.
0
32
read-write
DMACNT
USBD_DMACNT
DMA Count Register
0x60
read-write
n
0x0
0x0
DMACNT
DMA Transfer Count\nThe transfer count of the DMA operation to be performed is written to this register.
0
20
read-write
DMACTL
USBD_DMACTL
DMA Control Status Register
0x5C
read-write
n
0x0
0x0
DMAEN
DMA Enable Bit\n
5
1
read-write
0
DMA function Disabled
#0
1
DMA function Enabled
#1
DMARD
DMA Operation\n
4
1
read-write
0
The operation is a DMA write (read from USB buffer). DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation
#0
1
The operation is a DMA read (write to USB buffer)
#1
DMARST
Reset DMA State Machine\n
7
1
read-write
0
No reset the DMA state machine
#0
1
Reset the DMA state machine
#1
EPNUM
DMA Endpoint Address Bits\nUsed to define the Endpoint Address
0
4
read-write
SGEN
Scatter Gather Function Enable Bit\n
6
1
read-write
0
Scatter gather function Disabled
#0
1
Scatter gather function Enabled
#1
EPABUFEND
USBD_EPABUFEND
Endpoint A RAM End Address Register
0x88
read-write
n
0x0
0x0
EADDR
Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L.
0
12
read-write
EPABUFSTART
USBD_EPABUFSTART
Endpoint A RAM Start Address Register
0x84
read-write
n
0x0
0x0
SADDR
Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L.
0
12
read-write
EPACFG
USBD_EPACFG
Endpoint A Configuration Register
0x80
-1
read-write
n
0x0
0x0
EPDIR
Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
3
1
read-write
0
out-endpoint (Host OUT to Device)
#0
1
in-endpoint (Host IN to Device)
#1
EPEN
Endpoint Valid\nWhen set, this bit enables this endpoint. This bit has no effect on Endpoint 0, which is always enabled.\n
0
1
read-write
0
The endpoint Disabled
#0
1
The endpoint Enabled
#1
EPNUM
Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number.
4
4
read-write
EPTYPE
Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type. \n
1
2
read-write
0
Reserved
#00
1
Bulk
#01
2
Interrupt
#10
3
Isochronous
#11
EPADAT
USBD_EPADAT
Endpoint A Data Register
0x64
read-write
n
0x0
0x0
EPDAT
Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported.
0
32
read-write
EPADATCNT
USBD_EPADATCNT
Endpoint A Data Available Count Register
0x70
read-only
n
0x0
0x0
DATCNT
Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
0
16
read-only
DMALOOP
DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
16
15
read-only
EPAINTEN
USBD_EPAINTEN
Endpoint A Interrupt Enable Register
0x6C
read-write
n
0x0
0x0
BUFEMPTYIEN
Buffer Empty Interrupt\nWhen set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n
1
1
read-write
0
Buffer empty interrupt Disabled
#0
1
Buffer empty interrupt Enabled
#1
BUFFULLIEN
Buffer Full Interrupt \nWhen set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n
0
1
read-write
0
Buffer full interrupt Disabled
#0
1
Buffer full interrupt Enabled
#1
ERRIEN
ERR Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n
11
1
read-write
0
Error event interrupt Disabled
#0
1
Error event interrupt Enabled
#1
INTKIEN
Data IN Token Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n
6
1
read-write
0
Data IN token interrupt Disabled
#0
1
Data IN token interrupt Enabled
#1
NAKIEN
USB NAK Sent Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a NAK token is sent to the host.\n
8
1
read-write
0
NAK token interrupt Disabled
#0
1
NAK token interrupt Enabled
#1
NYETIEN
NYET Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n
10
1
read-write
0
NYET condition interrupt Disabled
#0
1
NYET condition interrupt Enabled
#1
OUTTKIEN
Data OUT Token Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n
5
1
read-write
0
Data OUT token interrupt Disabled
#0
1
Data OUT token interrupt Enabled
#1
PINGIEN
PING Token Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a PING token has been received from the host.\n
7
1
read-write
0
PING token interrupt Disabled
#0
1
PING token interrupt Enabled
#1
RXPKIEN
Data Packet Received Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n
4
1
read-write
0
Data packet has been transmitted to the host interrupt Disabled
#0
1
Data packet has been transmitted to the host interrupt Enabled
#1
SHORTRXIEN
Bulk Out Short Packet Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n
12
1
read-write
0
Bulk out interrupt Disabled
#0
1
Bulk out interrupt Enabled
#1
SHORTTXIEN
Short Packet Transferred Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n
2
1
read-write
0
Short data packet interrupt Disabled
#0
1
Short data packet interrupt Enabled
#1
STALLIEN
USB STALL Sent Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a stall token is sent to the host.\n
9
1
read-write
0
STALL token interrupt Disabled
#0
1
STALL token interrupt Enabled
#1
TXPKIEN
Data Packet Transmitted Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a data packet has been received from the host.\n
3
1
read-write
0
Data packet has been received from the host interrupt Disabled
#0
1
Data packet has been received from the host interrupt Enabled
#1
EPAINTSTS
USBD_EPAINTSTS
Endpoint A Interrupt Status Register
0x68
-1
read-write
n
0x0
0x0
BUFEMPTYIF
Buffer Empty\nFor an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only.
1
1
read-write
0
The endpoint buffer is not empty.\nThe currently selected buffer has not a count of 0
#0
1
The endpoint buffer is empty.\nThe currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read)
#1
BUFFULLIF
Buffer Full \nFor an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write). For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).\nNote: This bit is read-only.
0
1
read-write
0
The endpoint packet buffer is not full
#0
1
The endpoint packet buffer is full
#1
ERRIF
ERR Sent \nNote: Write 1 to clear this bit to 0.
11
1
read-write
0
No any error in the transaction
#0
1
There occurs any error in the transaction
#1
INTKIF
Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0.
6
1
read-write
0
Not Data IN token has been received from the host
#0
1
A Data IN token has been received from the host
#1
NAKIF
USB NAK Sent\nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
The last USB IN packet could be provided, and was acknowledged with an ACK
#0
1
The last USB IN packet could not be provided, and was acknowledged with a NAK
#1
NYETIF
NYET Sent \nNote: Write 1 to clear this bit to 0.
10
1
read-write
0
The space available in the RAM is sufficient to accommodate the next on coming data packet
#0
1
The space available in the RAM is not sufficient to accommodate the next on coming data packet
#1
OUTTKIF
Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
A Data OUT token has not been received from the host
#0
1
A Data OUT token has been received from the host. This bit also set by PING token (in high-speed only)
#1
PINGIF
PING Token Interrupt \nNote: Write 1 to clear this bit to 0.
7
1
read-write
0
A Data PING token has not been received from the host
#0
1
A Data PING token has been received from the host
#1
RXPKIF
Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
No data packet is received from the host by the endpoint
#0
1
A data packet is received from the host by the endpoint
#1
SHORTRXIF
Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0.
12
1
read-write
0
No bulk out short packet is received
#0
1
Received bulk out short packet (including zero length packet)
#1
SHORTTXIF
Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0.
2
1
read-write
0
The length of the last packet was not less than the Maximum Packet Size (EPMPS)
#0
1
The length of the last packet was less than the Maximum Packet Size (EPMPS)
#1
STALLIF
USB STALL Sent\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL
#0
1
The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL
#1
TXPKIF
Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
Not a data packet is transmitted from the endpoint to the host
#0
1
A data packet is transmitted from the endpoint to the host
#1
EPAMPS
USBD_EPAMPS
Endpoint A Maximum Packet Size Register
0x78
read-write
n
0x0
0x0
EPMPS
Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint.
0
11
read-write
EPARSPCTL
USBD_EPARSPCTL
Endpoint A Response Control Register
0x74
read-write
n
0x0
0x0
DISBUF
Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference USBD_EPxDATCNT register.\n
7
1
read-write
0
Buffer Not Disabled when Bulk-OUT short packet is received
#0
1
Buffer Disabled when Bulk-OUT short packet is received
#1
FLUSH
Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after an configuration event.\n
0
1
read-write
0
The packet buffer is not flushed
#0
1
The packet buffer is flushed by user
#1
HALT
Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.\n
4
1
read-write
0
Not send a STALL handshake as response to the token from the host
#0
1
Send a STALL handshake as response to the token from the host
#1
MODE
Mode Control\nThe two bits decide the operation mode of the in-endpoint. \n00: Auto-Validate Mode\n01: Manual-Validate Mode\n10: Fly Mode\n11: Reserved\nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected.
1
2
read-write
SHORTTXEN
Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer. This bit gets cleared once the data packet is sent.\n
6
1
read-write
0
Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint
#0
1
Validate any remaining data in the buffer which is not equal to the MPS of the endpoint
#1
TOGGLE
Endpoint Toggle
This bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.
The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host. Only when toggle bit is 1 , this bit can be written into the inversed write data bit[3].
3
1
read-write
0
Not clear the endpoint data toggle bit
#0
1
Clear the endpoint data toggle bit
#1
ZEROLEN
Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set, a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent.\n
5
1
read-write
0
A zero packet is not sent to the host on reception of an IN-token
#0
1
A zero packet is sent to the host on reception of an IN-token
#1
EPATXCNT
USBD_EPATXCNT
Endpoint A Transfer Count Register
0x7C
read-write
n
0x0
0x0
TXCNT
Endpoint Transfer Count\nFor IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints, this field has no effect.
0
11
read-write
EPBBUFEND
USBD_EPBBUFEND
Endpoint B RAM End Address Register
0xB0
read-write
n
0x0
0x0
EPBBUFSTART
USBD_EPBBUFSTART
Endpoint B RAM Start Address Register
0xAC
read-write
n
0x0
0x0
EPBCFG
USBD_EPBCFG
Endpoint B Configuration Register
0xA8
read-write
n
0x0
0x0
EPBDAT
USBD_EPBDAT
Endpoint B Data Register
0x8C
read-write
n
0x0
0x0
EPBDATCNT
USBD_EPBDATCNT
Endpoint B Data Available Count Register
0x98
read-write
n
0x0
0x0
EPBINTEN
USBD_EPBINTEN
Endpoint B Interrupt Enable Register
0x94
read-write
n
0x0
0x0
EPBINTSTS
USBD_EPBINTSTS
Endpoint B Interrupt Status Register
0x90
read-write
n
0x0
0x0
EPBMPS
USBD_EPBMPS
Endpoint B Maximum Packet Size Register
0xA0
read-write
n
0x0
0x0
EPBRSPCTL
USBD_EPBRSPCTL
Endpoint B Response Control Register
0x9C
read-write
n
0x0
0x0
EPBTXCNT
USBD_EPBTXCNT
Endpoint B Transfer Count Register
0xA4
read-write
n
0x0
0x0
EPCBUFEND
USBD_EPCBUFEND
Endpoint C RAM End Address Register
0xD8
read-write
n
0x0
0x0
EPCBUFSTART
USBD_EPCBUFSTART
Endpoint C RAM Start Address Register
0xD4
read-write
n
0x0
0x0
EPCCFG
USBD_EPCCFG
Endpoint C Configuration Register
0xD0
read-write
n
0x0
0x0
EPCDAT
USBD_EPCDAT
Endpoint C Data Register
0xB4
read-write
n
0x0
0x0
EPCDATCNT
USBD_EPCDATCNT
Endpoint C Data Available Count Register
0xC0
read-write
n
0x0
0x0
EPCINTEN
USBD_EPCINTEN
Endpoint C Interrupt Enable Register
0xBC
read-write
n
0x0
0x0
EPCINTSTS
USBD_EPCINTSTS
Endpoint C Interrupt Status Register
0xB8
read-write
n
0x0
0x0
EPCMPS
USBD_EPCMPS
Endpoint C Maximum Packet Size Register
0xC8
read-write
n
0x0
0x0
EPCRSPCTL
USBD_EPCRSPCTL
Endpoint C Response Control Register
0xC4
read-write
n
0x0
0x0
EPCTXCNT
USBD_EPCTXCNT
Endpoint C Transfer Count Register
0xCC
read-write
n
0x0
0x0
EPDBUFEND
USBD_EPDBUFEND
Endpoint D RAM End Address Register
0x100
read-write
n
0x0
0x0
EPDBUFSTART
USBD_EPDBUFSTART
Endpoint D RAM Start Address Register
0xFC
read-write
n
0x0
0x0
EPDCFG
USBD_EPDCFG
Endpoint D Configuration Register
0xF8
read-write
n
0x0
0x0
EPDDAT
USBD_EPDDAT
Endpoint D Data Register
0xDC
read-write
n
0x0
0x0
EPDDATCNT
USBD_EPDDATCNT
Endpoint D Data Available Count Register
0xE8
read-write
n
0x0
0x0
EPDINTEN
USBD_EPDINTEN
Endpoint D Interrupt Enable Register
0xE4
read-write
n
0x0
0x0
EPDINTSTS
USBD_EPDINTSTS
Endpoint D Interrupt Status Register
0xE0
read-write
n
0x0
0x0
EPDMPS
USBD_EPDMPS
Endpoint D Maximum Packet Size Register
0xF0
read-write
n
0x0
0x0
EPDRSPCTL
USBD_EPDRSPCTL
Endpoint D Response Control Register
0xEC
read-write
n
0x0
0x0
EPDTXCNT
USBD_EPDTXCNT
Endpoint D Transfer Count Register
0xF4
read-write
n
0x0
0x0
EPEBUFEND
USBD_EPEBUFEND
Endpoint E RAM End Address Register
0x128
read-write
n
0x0
0x0
EPEBUFSTART
USBD_EPEBUFSTART
Endpoint E RAM Start Address Register
0x124
read-write
n
0x0
0x0
EPECFG
USBD_EPECFG
Endpoint E Configuration Register
0x120
read-write
n
0x0
0x0
EPEDAT
USBD_EPEDAT
Endpoint E Data Register
0x104
read-write
n
0x0
0x0
EPEDATCNT
USBD_EPEDATCNT
Endpoint E Data Available Count Register
0x110
read-write
n
0x0
0x0
EPEINTEN
USBD_EPEINTEN
Endpoint E Interrupt Enable Register
0x10C
read-write
n
0x0
0x0
EPEINTSTS
USBD_EPEINTSTS
Endpoint E Interrupt Status Register
0x108
read-write
n
0x0
0x0
EPEMPS
USBD_EPEMPS
Endpoint E Maximum Packet Size Register
0x118
read-write
n
0x0
0x0
EPERSPCTL
USBD_EPERSPCTL
Endpoint E Response Control Register
0x114
read-write
n
0x0
0x0
EPETXCNT
USBD_EPETXCNT
Endpoint E Transfer Count Register
0x11C
read-write
n
0x0
0x0
EPFBUFEND
USBD_EPFBUFEND
Endpoint F RAM End Address Register
0x150
read-write
n
0x0
0x0
EPFBUFSTART
USBD_EPFBUFSTART
Endpoint F RAM Start Address Register
0x14C
read-write
n
0x0
0x0
EPFCFG
USBD_EPFCFG
Endpoint F Configuration Register
0x148
read-write
n
0x0
0x0
EPFDAT
USBD_EPFDAT
Endpoint F Data Register
0x12C
read-write
n
0x0
0x0
EPFDATCNT
USBD_EPFDATCNT
Endpoint F Data Available Count Register
0x138
read-write
n
0x0
0x0
EPFINTEN
USBD_EPFINTEN
Endpoint F Interrupt Enable Register
0x134
read-write
n
0x0
0x0
EPFINTSTS
USBD_EPFINTSTS
Endpoint F Interrupt Status Register
0x130
read-write
n
0x0
0x0
EPFMPS
USBD_EPFMPS
Endpoint F Maximum Packet Size Register
0x140
read-write
n
0x0
0x0
EPFRSPCTL
USBD_EPFRSPCTL
Endpoint F Response Control Register
0x13C
read-write
n
0x0
0x0
EPFTXCNT
USBD_EPFTXCNT
Endpoint F Transfer Count Register
0x144
read-write
n
0x0
0x0
EPGBUFEND
USBD_EPGBUFEND
Endpoint G RAM End Address Register
0x178
read-write
n
0x0
0x0
EPGBUFSTART
USBD_EPGBUFSTART
Endpoint G RAM Start Address Register
0x174
read-write
n
0x0
0x0
EPGCFG
USBD_EPGCFG
Endpoint G Configuration Register
0x170
read-write
n
0x0
0x0
EPGDAT
USBD_EPGDAT
Endpoint G Data Register
0x154
read-write
n
0x0
0x0
EPGDATCNT
USBD_EPGDATCNT
Endpoint G Data Available Count Register
0x160
read-write
n
0x0
0x0
EPGINTEN
USBD_EPGINTEN
Endpoint G Interrupt Enable Register
0x15C
read-write
n
0x0
0x0
EPGINTSTS
USBD_EPGINTSTS
Endpoint G Interrupt Status Register
0x158
read-write
n
0x0
0x0
EPGMPS
USBD_EPGMPS
Endpoint G Maximum Packet Size Register
0x168
read-write
n
0x0
0x0
EPGRSPCTL
USBD_EPGRSPCTL
Endpoint G Response Control Register
0x164
read-write
n
0x0
0x0
EPGTXCNT
USBD_EPGTXCNT
Endpoint G Transfer Count Register
0x16C
read-write
n
0x0
0x0
EPHBUFEND
USBD_EPHBUFEND
Endpoint H RAM End Address Register
0x1A0
read-write
n
0x0
0x0
EPHBUFSTART
USBD_EPHBUFSTART
Endpoint H RAM Start Address Register
0x19C
read-write
n
0x0
0x0
EPHCFG
USBD_EPHCFG
Endpoint H Configuration Register
0x198
read-write
n
0x0
0x0
EPHDAT
USBD_EPHDAT
Endpoint H Data Register
0x17C
read-write
n
0x0
0x0
EPHDATCNT
USBD_EPHDATCNT
Endpoint H Data Available Count Register
0x188
read-write
n
0x0
0x0
EPHINTEN
USBD_EPHINTEN
Endpoint H Interrupt Enable Register
0x184
read-write
n
0x0
0x0
EPHINTSTS
USBD_EPHINTSTS
Endpoint H Interrupt Status Register
0x180
read-write
n
0x0
0x0
EPHMPS
USBD_EPHMPS
Endpoint H Maximum Packet Size Register
0x190
read-write
n
0x0
0x0
EPHRSPCTL
USBD_EPHRSPCTL
Endpoint H Response Control Register
0x18C
read-write
n
0x0
0x0
EPHTXCNT
USBD_EPHTXCNT
Endpoint H Transfer Count Register
0x194
read-write
n
0x0
0x0
EPIBUFEND
USBD_EPIBUFEND
Endpoint I RAM End Address Register
0x1C8
read-write
n
0x0
0x0
EPIBUFSTART
USBD_EPIBUFSTART
Endpoint I RAM Start Address Register
0x1C4
read-write
n
0x0
0x0
EPICFG
USBD_EPICFG
Endpoint I Configuration Register
0x1C0
read-write
n
0x0
0x0
EPIDAT
USBD_EPIDAT
Endpoint I Data Register
0x1A4
read-write
n
0x0
0x0
EPIDATCNT
USBD_EPIDATCNT
Endpoint I Data Available Count Register
0x1B0
read-write
n
0x0
0x0
EPIINTEN
USBD_EPIINTEN
Endpoint I Interrupt Enable Register
0x1AC
read-write
n
0x0
0x0
EPIINTSTS
USBD_EPIINTSTS
Endpoint I Interrupt Status Register
0x1A8
read-write
n
0x0
0x0
EPIMPS
USBD_EPIMPS
Endpoint I Maximum Packet Size Register
0x1B8
read-write
n
0x0
0x0
EPIRSPCTL
USBD_EPIRSPCTL
Endpoint I Response Control Register
0x1B4
read-write
n
0x0
0x0
EPITXCNT
USBD_EPITXCNT
Endpoint I Transfer Count Register
0x1BC
read-write
n
0x0
0x0
EPJBUFEND
USBD_EPJBUFEND
Endpoint J RAM End Address Register
0x1F0
read-write
n
0x0
0x0
EPJBUFSTART
USBD_EPJBUFSTART
Endpoint J RAM Start Address Register
0x1EC
read-write
n
0x0
0x0
EPJCFG
USBD_EPJCFG
Endpoint J Configuration Register
0x1E8
read-write
n
0x0
0x0
EPJDAT
USBD_EPJDAT
Endpoint J Data Register
0x1CC
read-write
n
0x0
0x0
EPJDATCNT
USBD_EPJDATCNT
Endpoint J Data Available Count Register
0x1D8
read-write
n
0x0
0x0
EPJINTEN
USBD_EPJINTEN
Endpoint J Interrupt Enable Register
0x1D4
read-write
n
0x0
0x0
EPJINTSTS
USBD_EPJINTSTS
Endpoint J Interrupt Status Register
0x1D0
read-write
n
0x0
0x0
EPJMPS
USBD_EPJMPS
Endpoint J Maximum Packet Size Register
0x1E0
read-write
n
0x0
0x0
EPJRSPCTL
USBD_EPJRSPCTL
Endpoint J Response Control Register
0x1DC
read-write
n
0x0
0x0
EPJTXCNT
USBD_EPJTXCNT
Endpoint J Transfer Count Register
0x1E4
read-write
n
0x0
0x0
EPKBUFEND
USBD_EPKBUFEND
Endpoint K RAM End Address Register
0x218
read-write
n
0x0
0x0
EPKBUFSTART
USBD_EPKBUFSTART
Endpoint K RAM Start Address Register
0x214
read-write
n
0x0
0x0
EPKCFG
USBD_EPKCFG
Endpoint K Configuration Register
0x210
read-write
n
0x0
0x0
EPKDAT
USBD_EPKDAT
Endpoint K Data Register
0x1F4
read-write
n
0x0
0x0
EPKDATCNT
USBD_EPKDATCNT
Endpoint K Data Available Count Register
0x200
read-write
n
0x0
0x0
EPKINTEN
USBD_EPKINTEN
Endpoint K Interrupt Enable Register
0x1FC
read-write
n
0x0
0x0
EPKINTSTS
USBD_EPKINTSTS
Endpoint K Interrupt Status Register
0x1F8
read-write
n
0x0
0x0
EPKMPS
USBD_EPKMPS
Endpoint K Maximum Packet Size Register
0x208
read-write
n
0x0
0x0
EPKRSPCTL
USBD_EPKRSPCTL
Endpoint K Response Control Register
0x204
read-write
n
0x0
0x0
EPKTXCNT
USBD_EPKTXCNT
Endpoint K Transfer Count Register
0x20C
read-write
n
0x0
0x0
EPLBUFEND
USBD_EPLBUFEND
Endpoint L RAM End Address Register
0x240
read-write
n
0x0
0x0
EPLBUFSTART
USBD_EPLBUFSTART
Endpoint L RAM Start Address Register
0x23C
read-write
n
0x0
0x0
EPLCFG
USBD_EPLCFG
Endpoint L Configuration Register
0x238
read-write
n
0x0
0x0
EPLDAT
USBD_EPLDAT
Endpoint L Data Register
0x21C
read-write
n
0x0
0x0
EPLDATCNT
USBD_EPLDATCNT
Endpoint L Data Available Count Register
0x228
read-write
n
0x0
0x0
EPLINTEN
USBD_EPLINTEN
Endpoint L Interrupt Enable Register
0x224
read-write
n
0x0
0x0
EPLINTSTS
USBD_EPLINTSTS
Endpoint L Interrupt Status Register
0x220
read-write
n
0x0
0x0
EPLMPS
USBD_EPLMPS
Endpoint L Maximum Packet Size Register
0x230
read-write
n
0x0
0x0
EPLRSPCTL
USBD_EPLRSPCTL
Endpoint L Response Control Register
0x22C
read-write
n
0x0
0x0
EPLTXCNT
USBD_EPLTXCNT
Endpoint L Transfer Count Register
0x234
read-write
n
0x0
0x0
FADDR
USBD_FADDR
USB Function Address Register
0x20
read-write
n
0x0
0x0
FADDR
USB Function Address\nThis field contains the current USB address of the device. This field is cleared when a root port reset is detected.
0
7
read-write
FRAMECNT
USBD_FRAMECNT
USB Frame Count Register
0x1C
read-only
n
0x0
0x0
FRAMECNT
Frame Counter\nThis field contains the frame count from the most recent start-of-frame packet.
3
11
read-only
MFRAMECNT
Micro-Frame Counter\nThis field contains the micro-frame number for the frame number in the frame counter field.
0
3
read-only
GINTEN
USBD_GINTEN
Interrupt Enable Low Register
0x8
-1
read-write
n
0x0
0x0
GINTSTS
USBD_GINTSTS
Interrupt Status Low Register
0x0
read-only
n
0x0
0x0
CEPIEN
Control Endpoint Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.\n
1
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPAIEN
Interrupt Enable Control for Endpoint A \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.\n
2
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPBIEN
Interrupt Enable Control for Endpoint B \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B \n
3
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPCIEN
Interrupt Enable Control for Endpoint C \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C\n
4
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPDIEN
Interrupt Enable Control for Endpoint D \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D\n
5
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPEIEN
Interrupt Enable Control for Endpoint E \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E\n
6
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPFIEN
Interrupt Enable Control for Endpoint F \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F\n
7
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPGIEN
Interrupt Enable Control for Endpoint G\nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G\n
8
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPHIEN
Interrupt Enable Control for Endpoint H \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H\n
9
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPIIEN
Interrupt Enable Control for Endpoint I \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I\n
10
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPJIEN
Interrupt Enable Control for Endpoint J \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J\n
11
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPKIEN
Interrupt Enable Control for Endpoint K \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K\n
12
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPLIEN
Interrupt Enable Control for Endpoint L \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L\n
13
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
USBIEN
USB Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.\n
0
1
read-only
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
OPER
USBD_OPER
USB Operational Register
0x18
-1
read-write
n
0x0
0x0
CURSPD
USB Current Speed\n
2
1
read-write
0
The device has settled in Full Speed
#0
1
The USB device controller has settled in High-speed
#1
HISPDEN
USB High-Speed\n
1
1
read-write
0
The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host
#0
1
The USB device controller to initiate a chirp-sequence during reset protocol
#1
RESUMEEN
Generate Resume\n
0
1
read-write
0
No Resume sequence to be initiated to the host
#0
1
A Resume sequence to be initiated to the host if device remote wakeup is enabled. This bit is self-clearing
#1
PHYCTL
USBD_PHYCTL
USB PHY Control Register
0x704
-1
read-write
n
0x0
0x0
DPPUEN
DP Pull-Up\n
8
1
read-write
0
Pull-up resistor on D+ Disabled
#0
1
Pull-up resistor on D+ Enabled
#1
PHYEN
PHY Suspend Enable Bit\n
9
1
read-write
0
The USB PHY is suspend
#0
1
The USB PHY is not suspend
#1
VBUSDET
VBUS Status\n
31
1
read-write
0
The VBUS is not detected yet
#0
1
The VBUS is detected
#1
WKEN
Wake-Up Enable Bit\n
24
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
SETUP1_0
USBD_SETUP1_0
Setup1 Setup0 Bytes
0x44
-1
read-only
n
0x0
0x0
SETUP0
Setup Byte 0[7:0]
This register provides byte 0 of the last setup packet received. For a Standard Device Request, the following bmRequestType information is returned.
Bit 7(Direction):
0: Host to device
1: Device to host
Bit 6-5 (Type):
00: Standard
01: Class
10: Vendor
11: Reserved
Bit 4-0 (Recipient)
00000: Device
00001: Interface
00010: Endpoint
00011: Other
Others: Reserved
0
8
read-only
SETUP1
Setup Byte 1[15:8]\nThis register provides byte 1 of the last setup packet received. For a Standard Device Request, the following bRequest Code information is returned. \n
8
8
read-only
0
Get Status
#00000000
1
Clear Feature
#00000001
2
Reserved
#00000010
3
Set Feature
#00000011
4
Reserved
#00000100
5
Set Address
#00000101
6
Get Descriptor
#00000110
7
Set Descriptor
#00000111
8
Get Configuration
#00001000
9
Set Configuration
#00001001
10
Get Interface
#00001010
11
Set Interface
#00001011
12
Synch Frame
#00001100
SETUP3_2
USBD_SETUP3_2
Setup3 Setup2 Bytes
0x48
-1
read-only
n
0x0
0x0
SETUP2
Setup Byte 2 [7:0]\nThis register provides byte 2 of the last setup packet received. For a Standard Device Request, the least significant byte of the wValue field is returned.
0
8
read-only
SETUP3
Setup Byte 3 [15:8]\nThis register provides byte 3 of the last setup packet received. For a Standard Device Request, the most significant byte of the wValue field is returned.
8
8
read-only
SETUP5_4
USBD_SETUP5_4
Setup5 Setup4 Bytes
0x4C
-1
read-only
n
0x0
0x0
SETUP4
Setup Byte 4[7:0] \nThis register provides byte 4 of the last setup packet received. For a Standard Device Request, the least significant byte of the wIndex is returned.
0
8
read-only
SETUP5
Setup Byte 5[15:8] \nThis register provides byte 5 of the last setup packet received. For a Standard Device Request, the most significant byte of the wIndex field is returned.
8
8
read-only
SETUP7_6
USBD_SETUP7_6
Setup7 Setup6 Bytes
0x50
-1
read-only
n
0x0
0x0
SETUP6
Setup Byte 6[7:0] \nThis register provides byte 6 of the last setup packet received. For a Standard Device Request, the least significant byte of the wLength field is returned.
0
8
read-only
SETUP7
Setup Byte 7[15:8] \nThis register provides byte 7 of the last setup packet received. For a Standard Device Request, the most significant byte of the wLength field is returned.
8
8
read-only
TEST
USBD_TEST
USB Test Mode Register
0x24
read-write
n
0x0
0x0
TESTMODE
Test Mode Selection\nNote: This field is cleared when root port reset is detected.
0
3
read-write
0
Normal Operation
#000
1
Test_J
#001
2
Test_K
#010
3
Test_SE0_NAK
#011
4
Test_Packet
#100
5
Test_Force_Enable
#101
6
Reserved
#110
7
Reserved
#111
USBH
USBH Register Map
USBH
0x0
0x0
0x5C
registers
n
0x200
0x8
registers
n
HcBulkCurrentED
HcBulkCurrentED
Host Controller Bulk Current ED Register
0x2C
read-write
n
0x0
0x0
BCED
Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list.
4
28
read-write
HcBulkHeadED
HcBulkHeadED
Host Controller Bulk Head ED Register
0x28
read-write
n
0x0
0x0
BHED
Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
4
28
read-write
HcCommandStatus
HcCommandStatus
Host Controller Command Status Register
0x8
read-write
n
0x0
0x0
BLF
Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.\n
2
1
read-write
0
No active TD found or Host Controller begins to process the head of the Bulk list
#0
1
An active TD added or found on the Bulk list
#1
CLF
Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.\n
1
1
read-write
0
No active TD found or Host Controller begins to process the head of the Control list
#0
1
An active TD added or found on the Control list
#1
HCR
Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller, upon completed of the reset operation.\nThis bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.\n
0
1
read-write
0
Host Controller is not in software reset state
#0
1
Host Controller is in software reset state
#1
SOC
Scheduling Overrun Count\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
16
2
read-write
HcControl
HcControl
Host Controller Control Register
0x4
read-write
n
0x0
0x0
BLE
Bulk List Enable Bit\n
5
1
read-write
0
Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Bulk list in the next frame Enabled
#1
CBSR
Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this\nValue.\n
0
2
read-write
0
Number of Control EDs over Bulk EDs served is 1:1
#00
1
Number of Control EDs over Bulk EDs served is 2:1
#01
2
Number of Control EDs over Bulk EDs served is 3:1
#10
3
Number of Control EDs over Bulk EDs served is 4:1
#11
CLE
Control List Enable Bit\n
4
1
read-write
0
Processing of the Control list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Control list in the next frame Enabled
#1
HCFS
Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are:\n
6
2
read-write
0
USBSUSPEND
#00
1
USBOPERATIONAL
#01
2
USBRESUME
#10
3
USBRESET
#11
IE
Isochronous Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.\n
3
1
read-write
0
Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too
#1
PLE
Periodic List Enable Bit
When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
2
1
read-write
0
Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled
#1
HcControlCurrentED
HcControlCurrentED
Host Controller Control Current ED Register
0x24
read-write
n
0x0
0x0
CCED
Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
4
28
read-write
HcControlHeadED
HcControlHeadED
Host Controller Control Head ED Register
0x20
read-write
n
0x0
0x0
CHED
Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list.
4
28
read-write
HcDoneHead
HcDoneHead
Host Controller Done Head Register
0x30
read-write
n
0x0
0x0
DH
Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
4
28
read-write
HcFmInterval
HcFmInterval
Host Controller Frame Interval Register
0x34
-1
read-write
n
0x0
0x0
FI
Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here.
0
14
read-write
FIT
Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).\n
31
1
read-write
0
Host Controller Driver didn't load new value into FI (HcFmInterval[13:0])
#0
1
Host Controller Driver loads a new value into FI (HcFmInterval[13:0])
#1
FSMPS
FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
16
15
read-write
HcFmNumber
HcFmNumber
Host Controller Frame Number Register
0x3C
read-only
n
0x0
0x0
FN
Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the loading of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.'
0
16
read-only
HcFmRemaining
HcFmRemaining
Host Controller Frame Remaining Register
0x38
read-only
n
0x0
0x0
FR
Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
0
14
read-only
FRT
Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0
31
1
read-only
HcHCCA
HcHCCA
Host Controller Communication Area Register
0x18
read-write
n
0x0
0x0
HCCA
Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA).
8
24
read-write
HcInterruptDisable
HcInterruptDisable
Host Controller Interrupt Disable Control Register
0x14
read-write
n
0x0
0x0
FNO
Frame Number Overflow Disable Bit\nWrite Operation:\n
5
1
read-write
0
No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled
#0
1
Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Enabled
#1
MIE
Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation:\n
31
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high
#1
RD
Resume Detected Disable Bit\nWrite Operation:\n
3
1
read-write
0
No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled
#0
1
Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\nInterrupt generation due to RD (HcInterruptStatus[3]) Enabled
#1
RHSC
Root Hub Status Change Disable Bit\nWrite Operation:\n
6
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Enabled
#1
SF
Start Of Frame Disable Bit\nWrite Operation:\n
2
1
read-write
0
No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled
#0
1
Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\nInterrupt generation due to SF (HcInterruptStatus[2]) Enabled
#1
SO
Scheduling Overrun Disable Bit\nWrite Operation:\n
0
1
read-write
0
No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled
#0
1
Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\nInterrupt generation due to SO (HcInterruptStatus[0]) Enabled
#1
WDH
Write Back Done Head Disable Bit\nWrite Operation:\n
1
1
read-write
0
No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled
#0
1
Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Enabled
#1
HcInterruptEnable
HcInterruptEnable
Host Controller Interrupt Enable Control Register
0x10
read-write
n
0x0
0x0
FNO
Frame Number Overflow Interrupt Enable Bit\nWrite Operation:\n
5
1
read-write
0
No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled
#0
1
Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled
#1
MIE
Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation:\n
31
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high
#1
RD
Resume Detected Interrupt Enable Bit\nWrite Operation:\n
3
1
read-write
0
No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled
#0
1
Interrupt generation due to RD (HcInterruptStatus[3]) Enabled
#1
RHSC
Root Hub Status Change Interrupt Enable Bit\nWrite Operation:\n
6
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled
#1
SF
Start Of Frame Interrupt Enable Bit\nWrite Operation:\n
2
1
read-write
0
No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled
#0
1
Interrupt generation due to SF (HcInterruptStatus[2]) Enabled
#1
SO
Scheduling Overrun Interrupt Enable Bit\nWrite Operation:\n
0
1
read-write
0
No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled
#0
1
Interrupt generation due to SO (HcInterruptStatus[0]) Enabled
#1
WDH
Write Back Done Head Interrupt Enable Bit\nWrite Operation:\n
1
1
read-write
0
No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled
#0
1
Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled
#1
HcInterruptStatus
HcInterruptStatus
Host Controller Interrupt Status Register
0xC
read-write
n
0x0
0x0
FNO
Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\n
5
1
read-write
0
The bit 15 of Frame Number didn't change
#0
1
The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1
#1
RD
Resume Detected\nSet when Host Controller detects resume signaling on a downstream port.\n
3
1
read-write
0
No resume signaling detected on a downstream port
#0
1
Resume signaling detected on a downstream port
#1
RHSC
Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.\n
6
1
read-write
0
The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change
#0
1
The content of HcRhStatus or the content of HcRhPortStatus1 register has changed
#1
SF
Start Of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time.\n
2
1
read-write
0
.Not the start of a frame
#0
1
.Indicate the start of a frame and Host Controller generates a SOF token
#1
SO
Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred.\n
0
1
read-write
0
Schedule Overrun didn't occur
#0
1
Schedule Overrun has occurred
#1
WDH
Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared.\n
1
1
read-write
0
.Host Controller didn't update HccaDoneHead
#0
1
.Host Controller has written HcDoneHead to HccaDoneHead
#1
HcLSThreshold
HcLSThreshold
Host Controller Low-speed Threshold Register
0x44
-1
read-write
n
0x0
0x0
LST
Low-Speed Threshold\n
0
12
read-write
HcMiscControl
HcMiscControl
Host Controller Miscellaneous Control Register
0x204
read-write
n
0x0
0x0
ABORT
AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus.\n
1
1
read-write
0
No ERROR response received
#0
1
ERROR response received
#1
DBR16
Data Buffer Region 16
When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes.
0
1
read-write
DPRT1
Port 1 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.\n
16
1
read-write
0
The connection between USB host controller and transceiver of port 1 is enabled
#0
1
The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode
#1
DPRT2
Port 2 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 2 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 2 will also be forced into the standby mode no matter what USB host controller operation is.\n
17
1
read-write
0
The connection between USB host controller and transceiver of port 2 is enabled
#0
1
The connection between USB host controller and transceiver of port 2 is disabled and the transceiver of port 2 will also be forced into the standby mode
#1
OCAL
Overcurrent Active Low\nThis bit controls the polarity of overcurrent flag from external power IC.\n
3
1
read-write
0
Overcurrent flag is high active
#0
1
Overcurrent flag is low active
#1
PCAL
Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC.\n
4
1
read-write
0
Port power control is high active
#0
1
Port power control is low active
#1
SIEPD
SIE Pipeline Disable Bit
When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor. This is a failsafe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz.
8
1
read-write
HcPeriodCurrentED
HcPeriodCurrentED
Host Controller Period Current ED Register
0x1C
read-write
n
0x0
0x0
PCED
Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
4
28
read-write
HcPeriodicStart
HcPeriodicStart
Host Controller Periodic Start Register
0x40
read-write
n
0x0
0x0
PS
Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
0
14
read-write
HcPhyControl
HcPhyControl
Host Controller PHY Control Register
0x200
read-write
n
0x0
0x0
STBYEN
USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption.\n
27
1
read-write
0
The USB transceiver would never enter the standby mode
#0
1
The USB transceiver will enter standby mode while port is in power off state (port power is inactive)
#1
HcRevision
HcRevision
Host Controller Revision Register
0x0
-1
read-only
n
0x0
0x0
REV
Revision
Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification.
0
8
read-only
HcRhDescriptorA
HcRhDescriptorA
Host Controller Root Hub Descriptor A Register
0x48
-1
read-write
n
0x0
0x0
NDP
Number Downstream Ports\nRoot Hub supports two downstream ports. It's 2 in this Root Hub.
0
8
read-write
NOCP
No Overcurrent Protection\nThis bit describes how the over current status for the Root Hub ports reported.\n
12
1
read-write
0
Over current status is reported
#0
1
Over current status is not reported
#1
OCPM
Overcurrent Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.\n
11
1
read-write
0
Global Over current
#0
1
Individual Over current
#1
PSM
Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled.\n
8
1
read-write
0
Global Switching
#0
1
Individual Switching
#1
HcRhDescriptorB
HcRhDescriptorB
Host Controller Root Hub Descriptor B Register
0x4C
read-write
n
0x0
0x0
PPCM
Port Power Control Mask\nGlobal power switching. This field is only valid if PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).\nNote: PPCM[15:3] and PPCM[0] are reserved.
16
16
read-write
0
Port power controlled by global power switching
0
1
Port power controlled by port power switching
1
HcRhPortStatus1
HcRhPortStatus1
Host Controller Root Hub Port Status [1]
0x54
read-write
n
0x0
0x0
CCS
CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)\nWrite Operation:\n
0
1
read-write
0
No effect.\nNo device connected
#0
1
Clear port enable.\nDevice connected
#1
CSC
Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero.\n
16
1
read-write
0
No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change)
#0
1
Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed)
#1
LSDA
Low Speed Device Attached (Read) Or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation:\n
9
1
read-write
0
No effect.\nFull Speed device
#0
1
Clear PPS (HcRhPortStatus1[8]).\nLow-speed device
#1
OCIC
Port Over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero.\n
19
1
read-write
0
POCI (HcRhPortStatus1[3]) didn't change
#0
1
POCI (HcRhPortStatus1[3]) changes
#1
PES
Port Enable Status\nWrite Operation:\n
1
1
read-write
0
No effect.\nPort Disabled
#0
1
Set port enable.\nPort Enabled
#1
PESC
Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero.\n
17
1
read-write
0
PES (HcRhPortStatus1[1]) didn't change
#0
1
PES (HcRhPortStatus1[1]) changed
#1
POCI
Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
This bit reflects the state of the over current status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
This bit is also used to initiate the selective result sequence for the port.
Write Operation:
3
1
read-write
0
No effect.\nNo over current condition
#0
1
Clear port suspend.\nOver current condition
#1
PPS
Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:\n
8
1
read-write
0
No effect.\nPort power is Diabled
#0
1
Port Power Enabled.\nPort power is Enabled
#1
PRS
Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation:\n
4
1
read-write
0
No effect.\nPort reset signal is not active
#0
1
Set port reset.\nPort reset signal is active
#1
PRSC
Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero.\n
20
1
read-write
0
Port reset is not complete
#0
1
Port reset is complete
#1
PSS
Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation:\n
2
1
read-write
0
No effect.\nPort is not suspended
#0
1
Set port suspend.\nPort is selectively suspended
#1
PSSC
Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero.\n
18
1
read-write
0
Port resume is not completed
#0
1
Port resume completed
#1
HcRhPortStatus2
HcRhPortStatus2
Host Controller Root Hub Port Status [2]
0x58
read-write
n
0x0
0x0
HcRhStatus
HcRhStatus
Host Controller Root Hub Status Register
0x50
read-write
n
0x0
0x0
CRWE
Clear Remote Wake-Up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation:\n
31
1
read-write
0
No effect
#0
1
Clear DRWE (HcRhStatus[15])
#1
DRWE
Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation:\n
15
1
read-write
0
No effect.\nConnect Status Change as a remote wake-up event Disabled
#0
1
Connect Status Change as a remote wake-up event Enabled
#1
LPS
Clear Global Power\n
0
1
read-write
0
No effect
#0
1
Clear global power
#1
LPSC
SetGlobalPower\n
16
1
read-write
0
No effect
#0
1
Set global power
#1
OCI
Overcurrent Indicator\nThis bit reflects the state of the over current status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.\n
1
1
read-write
0
No over current condition
#0
1
Over current condition
#1
OCIC
Over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero.\n
17
1
read-write
0
OCI (HcRhStatus[1]) didn't change
#0
1
OCI (HcRhStatus[1]) change
#1
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
ALTCTL
WDT_ALTCTL
Watchdog Timer Alternative Control Register
0x4
read-write
n
0x0
0x0
RSTDSEL
Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset delay period for different WDT time-out period.\nNote: This register will be reset to 0 if WDT time-out reset happened
0
2
read-write
0
Watchdog Timer reset delay period is (1024+2) * WDT_CLK
#00
1
Watchdog Timer reset delay period is (128+2) * WDT_CLK
#01
2
Watchdog Timer reset delay period is (16+2) * WDT_CLK
#10
3
Watchdog Timer reset delay period is (1+2) * WDT_CLK
#11
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nNote: Watchdog Timer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement affects Watchdog Timer counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
Watchdog Timer time-out interrupt did not occur
#0
1
Watchdog Timer time-out interrupt occurred
#1
INTEN
Watchdog Timer Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \n
6
1
read-write
0
Watchdog Timer interrupt Disabled
#0
1
Watchdog Timer interrupt Enabled
#1
RSTCNT
Clear Watchdog Timer (Write Protect)\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT counter
#1
RSTEN
Watchdog Timer Reset Enable Bit (Write Protect)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires.\n
1
1
read-write
0
Watchdog Timer time-out reset function Disabled
#0
1
Watchdog Timer time-out reset function Enabled
#1
RSTF
Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
Watchdog Timer time-out reset did not occur
#0
1
Watchdog Timer time-out reset occurred
#1
TOUTSEL
Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the Watchdog Timer.\n
8
3
read-write
0
24 *TWDT
#000
1
26 *TWDT
#001
2
28 *TWDT
#010
3
210 *TWDT
#011
4
212 *TWDT
#100
5
214 *TWDT
#101
6
216 *TWDT
#110
7
218 *TWDT
#111
WDTEN
Watchdog Timer Enable Bit (Write Protect)\nNote: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
7
1
read-write
0
Watchdog Timer Disabled (This action will reset the internal counter)
#0
1
Watchdog Timer Enabled
#1
WKEN
Watchdog Timer Wake-Up Function Enable Bit (Write Protect)\nIf this bit is set to 1, while WDT interrupt flag IF(WDT_CTL[3]) is generated to 1 and INTEN (WDT_CTL[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
Watchdog Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
Watchdog Timer does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
Window Watchdog Timer Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only.
0
6
read-only
CTL
WWDT_CTL
Window Watchdog Timer Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Bits\nSet this register to adjust the valid reload window. \nNote: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection\n
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * TWWDT
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * TWWDT
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * TWWDT
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * TWWDT
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * TWWDT
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * TWWDT
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * TWWDT
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * TWWDT
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * TWWDT
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * TWWDT
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * TWWDT
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * TWWDT
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * TWWDT
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * TWWDT
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * TWWDT
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * TWWDT
#1111
WWDTEN
WWDT Enable Bit\nSet this bit to enable Window Watchdog Timer counter counting.\n
0
1
read-write
0
Window Watchdog Timer counter is stopped
#0
1
Window Watchdog Timer counter is starting counting
#1
RLDCNT
WWDT_RLDCNT
Window Watchdog Timer Reload Counter Register
0x0
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Bit\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
0
32
write-only
STATUS
WWDT_STATUS
Window Watchdog Timer Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT value
#1
WWDTRF
WWDT Timer-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1