\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : Peripheral enable
bits : 0 - 0 (1 bit)
TXIE : TX Interrupt enable
bits : 1 - 1 (1 bit)
RXIE : RX Interrupt enable
bits : 2 - 2 (1 bit)
ADDRIE : Address match interrupt enable (slave only)
bits : 3 - 3 (1 bit)
NACKIE : Not acknowledge received interrupt enable
bits : 4 - 4 (1 bit)
STOPIE : STOP detection Interrupt enable
bits : 5 - 5 (1 bit)
TCIE : Transfer Complete interrupt enable
bits : 6 - 6 (1 bit)
ERRIE : Error interrupts enable
bits : 7 - 7 (1 bit)
DNF : Digital noise filter
bits : 8 - 11 (4 bit)
ANFOFF : Analog noise filter OFF
bits : 12 - 12 (1 bit)
TXDMAEN : DMA transmission requests enable
bits : 14 - 14 (1 bit)
RXDMAEN : DMA reception requests enable
bits : 15 - 15 (1 bit)
SBC : Slave byte control
bits : 16 - 16 (1 bit)
NOSTRETCH : Clock stretching disable
bits : 17 - 17 (1 bit)
WUPEN : Wakeup from STOP enable
bits : 18 - 18 (1 bit)
GCEN : General call enable
bits : 19 - 19 (1 bit)
SMBHEN : SMBus Host address enable
bits : 20 - 20 (1 bit)
SMBDEN : SMBus Device Default address enable
bits : 21 - 21 (1 bit)
ALERTEN : SMBUS alert enable
bits : 22 - 22 (1 bit)
PECEN : PEC enable
bits : 23 - 23 (1 bit)
Timing register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLL : SCL low period (master mode)
bits : 0 - 7 (8 bit)
SCLH : SCL high period (master mode)
bits : 8 - 15 (8 bit)
SDADEL : Data hold time
bits : 16 - 19 (4 bit)
SCLDEL : Data setup time
bits : 20 - 23 (4 bit)
PRESC : Timing prescaler
bits : 28 - 31 (4 bit)
Status register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUTA : Bus timeout A
bits : 0 - 11 (12 bit)
TIDLE : Idle clock timeout detection
bits : 12 - 12 (1 bit)
TIMOUTEN : Clock timeout enable
bits : 15 - 15 (1 bit)
TIMEOUTB : Bus timeout B
bits : 16 - 27 (12 bit)
TEXTEN : Extended clock timeout enable
bits : 31 - 31 (1 bit)
Interrupt and Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXE : Transmit data register empty (transmitters)
bits : 0 - 0 (1 bit)
access : read-write
TXIS : Transmit interrupt status (transmitters)
bits : 1 - 1 (1 bit)
access : read-write
RXNE : Receive data register not empty (receivers)
bits : 2 - 2 (1 bit)
access : read-only
ADDR : Address matched (slave mode)
bits : 3 - 3 (1 bit)
access : read-only
NACKF : Not acknowledge received flag
bits : 4 - 4 (1 bit)
access : read-only
STOPF : Stop detection flag
bits : 5 - 5 (1 bit)
access : read-only
TC : Transfer Complete (master mode)
bits : 6 - 6 (1 bit)
access : read-only
TCR : Transfer Complete Reload
bits : 7 - 7 (1 bit)
access : read-only
BERR : Bus error
bits : 8 - 8 (1 bit)
access : read-only
ARLO : Arbitration lost
bits : 9 - 9 (1 bit)
access : read-only
OVR : Overrun/Underrun (slave mode)
bits : 10 - 10 (1 bit)
access : read-only
PECERR : PEC Error in reception
bits : 11 - 11 (1 bit)
access : read-only
TIMEOUT : Timeout or t_low detection flag
bits : 12 - 12 (1 bit)
access : read-only
ALERT : SMBus alert
bits : 13 - 13 (1 bit)
access : read-only
BUSY : Bus busy
bits : 15 - 15 (1 bit)
access : read-only
DIR : Transfer direction (Slave mode)
bits : 16 - 16 (1 bit)
access : read-only
ADDCODE : Address match code (Slave mode)
bits : 17 - 23 (7 bit)
access : read-only
Interrupt clear register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDRCF : Address Matched flag clear
bits : 3 - 3 (1 bit)
NACKCF : Not Acknowledge flag clear
bits : 4 - 4 (1 bit)
STOPCF : Stop detection flag clear
bits : 5 - 5 (1 bit)
BERRCF : Bus error flag clear
bits : 8 - 8 (1 bit)
ARLOCF : Arbitration lost flag clear
bits : 9 - 9 (1 bit)
OVRCF : Overrun/Underrun flag clear
bits : 10 - 10 (1 bit)
PECCF : PEC Error flag clear
bits : 11 - 11 (1 bit)
TIMOUTCF : Timeout detection flag clear
bits : 12 - 12 (1 bit)
ALERTCF : Alert flag clear
bits : 13 - 13 (1 bit)
PEC register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PEC : Packet error checking register
bits : 0 - 7 (8 bit)
Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : 8-bit receive data
bits : 0 - 7 (8 bit)
Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : 8-bit transmit data
bits : 0 - 7 (8 bit)
Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADD : Slave address bit (master mode)
bits : 0 - 9 (10 bit)
RD_WRN : Transfer direction (master mode)
bits : 10 - 10 (1 bit)
ADD10 : 10-bit addressing mode (master mode)
bits : 11 - 11 (1 bit)
HEAD10R : 10-bit address header only read direction (master receiver mode)
bits : 12 - 12 (1 bit)
START : Start generation
bits : 13 - 13 (1 bit)
STOP : Stop generation (master mode)
bits : 14 - 14 (1 bit)
NACK : NACK generation (slave mode)
bits : 15 - 15 (1 bit)
NBYTES : Number of bytes
bits : 16 - 23 (8 bit)
RELOAD : NBYTES reload mode
bits : 24 - 24 (1 bit)
AUTOEND : Automatic end mode (master mode)
bits : 25 - 25 (1 bit)
PECBYTE : Packet error checking byte
bits : 26 - 26 (1 bit)
Own address register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1 : Interface address
bits : 0 - 9 (10 bit)
OA1MODE : Own Address 1 10-bit mode
bits : 10 - 10 (1 bit)
OA1EN : Own Address 1 enable
bits : 15 - 15 (1 bit)
Own address register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA2 : Interface address
bits : 1 - 7 (7 bit)
OA2MSK : Own Address 2 masks
bits : 8 - 10 (3 bit)
OA2EN : Own Address 2 enable
bits : 15 - 15 (1 bit)
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