\n

OPAMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3A4 byte (0x0)
mem_usage : registers
protection :

Registers

CSR

OTR

LPOTR


CSR

control/status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPA1PD S3SEL1 S4SEL1 S5SEL1 S6SEL1 OPA1CAL_L OPA1CAL_H OPA1LPM OPA2PD S3SEL2 S4SEL2 S5SEL2 S6SEL2 OPA2CAL_L OPA2CAL_H OPA2LPM OPA3PD S3SEL3 S4SEL3 S5SEL3 S6SEL3 OPA3CAL_L OPA3CAL_H OPA3LPM ANAWSEL1 ANAWSEL2 ANAWSEL3 S7SEL2 AOP_RANGE OPA1CALOUT OPA2CALOUT OPA3CALOUT

OPA1PD : OPAMP1 power down
bits : 0 - 0 (1 bit)

S3SEL1 : Switch 3 for OPAMP1 enable
bits : 1 - 1 (1 bit)

S4SEL1 : Switch 4 for OPAMP1 enable
bits : 2 - 2 (1 bit)

S5SEL1 : Switch 5 for OPAMP1 enable
bits : 3 - 3 (1 bit)

S6SEL1 : Switch 6 for OPAMP1 enable
bits : 4 - 4 (1 bit)

OPA1CAL_L : OPAMP1 offset calibration for P differential pair
bits : 5 - 5 (1 bit)

OPA1CAL_H : OPAMP1 offset calibration for N differential pair
bits : 6 - 6 (1 bit)

OPA1LPM : OPAMP1 low power mode
bits : 7 - 7 (1 bit)

OPA2PD : OPAMP2 power down
bits : 8 - 8 (1 bit)

S3SEL2 : Switch 3 for OPAMP2 enable
bits : 9 - 9 (1 bit)

S4SEL2 : Switch 4 for OPAMP2 enable
bits : 10 - 10 (1 bit)

S5SEL2 : Switch 5 for OPAMP2 enable
bits : 11 - 11 (1 bit)

S6SEL2 : Switch 6 for OPAMP2 enable
bits : 12 - 12 (1 bit)

OPA2CAL_L : OPAMP2 offset Calibration for P differential pair
bits : 13 - 13 (1 bit)

OPA2CAL_H : OPAMP2 offset calibration for N differential pair
bits : 14 - 14 (1 bit)

OPA2LPM : OPAMP2 low power mode
bits : 15 - 15 (1 bit)

OPA3PD : OPAMP3 power down
bits : 16 - 16 (1 bit)

S3SEL3 : Switch 3 for OPAMP3 Enable
bits : 17 - 17 (1 bit)

S4SEL3 : Switch 4 for OPAMP3 enable
bits : 18 - 18 (1 bit)

S5SEL3 : Switch 5 for OPAMP3 enable
bits : 19 - 19 (1 bit)

S6SEL3 : Switch 6 for OPAMP3 enable
bits : 20 - 20 (1 bit)

OPA3CAL_L : OPAMP3 offset Calibration for P differential pair
bits : 21 - 21 (1 bit)

OPA3CAL_H : OPAMP3 offset calibration for N differential pair
bits : 22 - 22 (1 bit)

OPA3LPM : OPAMP3 low power mode
bits : 23 - 23 (1 bit)

ANAWSEL1 : Switch SanA enable for OPAMP1
bits : 24 - 24 (1 bit)

ANAWSEL2 : Switch SanA enable for OPAMP2
bits : 25 - 25 (1 bit)

ANAWSEL3 : Switch SanA enable for OPAMP3
bits : 26 - 26 (1 bit)

S7SEL2 : Switch 7 for OPAMP2 enable
bits : 27 - 27 (1 bit)

AOP_RANGE : Power range selection
bits : 28 - 28 (1 bit)

OPA1CALOUT : OPAMP1 calibration output
bits : 29 - 29 (1 bit)

OPA2CALOUT : OPAMP2 calibration output
bits : 30 - 30 (1 bit)

OPA3CALOUT : OPAMP3 calibration output
bits : 31 - 31 (1 bit)


OTR

offset trimming register for normal mode
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTR OTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AO1_OPT_OFFSET_TRIM AO2_OPT_OFFSET_TRIM AO3_OPT_OFFSET_TRIM OT_USER

AO1_OPT_OFFSET_TRIM : OPAMP1, 10-bit offset trim value for normal mode
bits : 0 - 9 (10 bit)

AO2_OPT_OFFSET_TRIM : OPAMP2, 10-bit offset trim value for normal mode
bits : 10 - 19 (10 bit)

AO3_OPT_OFFSET_TRIM : OPAMP3, 10-bit offset trim value for normal mode
bits : 20 - 29 (10 bit)

OT_USER : Select user or factory trimming value
bits : 31 - 31 (1 bit)


LPOTR

OPAMP offset trimming register for low power mode
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOTR LPOTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AO1_OPT_OFFSET_TRIM_LP AO2_OPT_OFFSET_TRIM_LP AO3_OPT_OFFSET_TRIM_LP

AO1_OPT_OFFSET_TRIM_LP : OPAMP1, 10-bit offset trim value for low power mode
bits : 0 - 9 (10 bit)

AO2_OPT_OFFSET_TRIM_LP : OPAMP2, 10-bit offset trim value for low power mode
bits : 10 - 19 (10 bit)

AO3_OPT_OFFSET_TRIM_LP : OPAMP3, 10-bit offset trim value for low power mode
bits : 20 - 29 (10 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.