\n

DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x15 byte (0x0)
mem_usage : registers
protection :

Registers

IDCODE

CR

APB1_FZ

APB2_FZ


IDCODE

DBGMCU_IDCODE
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDCODE IDCODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device identifier
bits : 0 - 11 (12 bit)

REV_ID : Revision identifie
bits : 16 - 31 (16 bit)


CR

Debug MCU configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_SLEEP DBG_STOP DBG_STANDBY TRACE_IOEN TRACE_MODE

DBG_SLEEP : Debug Sleep mode
bits : 0 - 0 (1 bit)

DBG_STOP : Debug Stop mode
bits : 1 - 1 (1 bit)

DBG_STANDBY : Debug Standby mode
bits : 2 - 2 (1 bit)

TRACE_IOEN : Trace pin assignment control
bits : 5 - 5 (1 bit)

TRACE_MODE : Trace pin assignment control
bits : 6 - 7 (2 bit)


APB1_FZ

Debug MCU APB1 freeze register1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1_FZ APB1_FZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM2_STOP DBG_TIM3_STOP DBG_TIM4_STOP DBG_TIM5_STOP DBG_TIM6_STOP DBG_TIM7_STOP DBG_RTC_STOP DBG_WWDG_STOP DBG_IWDG_STOP DBG_I2C1_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT

DBG_TIM2_STOP : TIM2 counter stopped when core is halted
bits : 0 - 0 (1 bit)

DBG_TIM3_STOP : TIM3 counter stopped when core is halted
bits : 1 - 1 (1 bit)

DBG_TIM4_STOP : TIM4 counter stopped when core is halted
bits : 2 - 2 (1 bit)

DBG_TIM5_STOP : TIM5 counter stopped when core is halted
bits : 3 - 3 (1 bit)

DBG_TIM6_STOP : TIM6 counter stopped when core is halted
bits : 4 - 4 (1 bit)

DBG_TIM7_STOP : TIM7 counter stopped when core is halted
bits : 5 - 5 (1 bit)

DBG_RTC_STOP : Debug RTC stopped when core is halted
bits : 10 - 10 (1 bit)

DBG_WWDG_STOP : Debug window watchdog stopped when core is halted
bits : 11 - 11 (1 bit)

DBG_IWDG_STOP : Debug independent watchdog stopped when core is halted
bits : 12 - 12 (1 bit)

DBG_I2C1_SMBUS_TIMEOUT : SMBUS timeout mode stopped when core is halted
bits : 21 - 21 (1 bit)

DBG_I2C2_SMBUS_TIMEOUT : SMBUS timeout mode stopped when core is halted
bits : 22 - 22 (1 bit)


APB2_FZ

Debug MCU APB1 freeze register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2_FZ APB2_FZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM9_STOP DBG_TIM10_STOP DBG_TIM11_STOP

DBG_TIM9_STOP : TIM counter stopped when core is halted
bits : 2 - 2 (1 bit)

DBG_TIM10_STOP : TIM counter stopped when core is halted
bits : 3 - 3 (1 bit)

DBG_TIM11_STOP : TIM counter stopped when core is halted
bits : 4 - 4 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.