\n

RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

CIER

CIFR

CICR

AHB1RSTR

AHB2RSTR

AHB3RSTR

APB1RSTR1

APB1RSTR2

ICSCR

APB2RSTR

AHB1ENR

AHB2ENR

AHB3ENR

APB1ENR1

APB1ENR2

APB2ENR

AHB1SMENR

AHB2SMENR

AHB3SMENR

APB1SMENR1

APB1SMENR2

CFGR

APB2SMENR

CCIPR

BDCR

CSR

CRRCR

CCIPR2

PLLCFGR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSION MSIRDY MSIPLLEN MSIRGSEL MSIRANGE HSION HSIKERON HSIRDY HSIASFS HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

MSION : MSI clock enable
bits : 0 - 0 (1 bit)
access : read-write

MSIRDY : MSI clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

MSIPLLEN : MSI clock PLL enable
bits : 2 - 2 (1 bit)
access : read-write

MSIRGSEL : MSI clock range selection
bits : 3 - 3 (1 bit)
access : write-only

MSIRANGE : MSI clock ranges
bits : 4 - 7 (4 bit)
access : read-write

HSION : HSI clock enable
bits : 8 - 8 (1 bit)
access : read-write

HSIKERON : HSI always enable for peripheral kernels
bits : 9 - 9 (1 bit)
access : read-write

HSIRDY : HSI clock ready flag
bits : 10 - 10 (1 bit)
access : read-only

HSIASFS : HSI automatic start from Stop
bits : 11 - 11 (1 bit)
access : read-write

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSE crystal oscillator bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock security system enable
bits : 19 - 19 (1 bit)
access : write-only

PLLON : Main PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : Main PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


CIER

Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYIE LSERDYIE MSIRDYIE HSIRDYIE HSERDYIE PLLRDYIE LSECSSIE HSI48RDYIE

LSIRDYIE : LSI ready interrupt enable
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)

MSIRDYIE : MSI ready interrupt enable
bits : 2 - 2 (1 bit)

HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)

HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)

PLLRDYIE : PLL ready interrupt enable
bits : 5 - 5 (1 bit)

LSECSSIE : LSE clock security system interrupt enable
bits : 9 - 9 (1 bit)

HSI48RDYIE : HSI48 ready interrupt enable
bits : 10 - 10 (1 bit)


CIFR

Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF MSIRDYF HSIRDYF HSERDYF PLLRDYF CSSF LSECSSF HSI48RDYF

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

MSIRDYF : MSI ready interrupt flag
bits : 2 - 2 (1 bit)

HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)

HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)

PLLRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)

CSSF : Clock security system interrupt flag
bits : 8 - 8 (1 bit)

LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)

HSI48RDYF : HSI48 ready interrupt flag
bits : 10 - 10 (1 bit)


CICR

Clock interrupt clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CICR CICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYC LSERDYC MSIRDYC HSIRDYC HSERDYC PLLRDYC CSSC LSECSSC HSI48RDYC

LSIRDYC : LSI ready interrupt clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)

MSIRDYC : MSI ready interrupt clear
bits : 2 - 2 (1 bit)

HSIRDYC : HSI ready interrupt clear
bits : 3 - 3 (1 bit)

HSERDYC : HSE ready interrupt clear
bits : 4 - 4 (1 bit)

PLLRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)

CSSC : Clock security system interrupt clear
bits : 8 - 8 (1 bit)

LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)

HSI48RDYC : HSI48 oscillator ready interrupt clear
bits : 10 - 10 (1 bit)


AHB1RSTR

AHB1 peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1RSTR AHB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1RST DMA2RST FLASHRST CRCRST TSCRST

DMA1RST : DMA1 reset
bits : 0 - 0 (1 bit)

DMA2RST : DMA2 reset
bits : 1 - 1 (1 bit)

FLASHRST : Flash memory interface reset
bits : 8 - 8 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

TSCRST : Touch Sensing Controller reset
bits : 16 - 16 (1 bit)


AHB2RSTR

AHB2 peripheral reset register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2RSTR AHB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOARST GPIOBRST GPIOCRST GPIOHRST ADCRST RNGRST

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)

ADCRST : ADC reset
bits : 13 - 13 (1 bit)

RNGRST : Random number generator reset
bits : 18 - 18 (1 bit)


AHB3RSTR

AHB3 peripheral reset register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3RSTR AHB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIRST

QSPIRST : Quad SPI memory interface reset
bits : 8 - 8 (1 bit)


APB1RSTR1

APB1 peripheral reset register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR1 APB1RSTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM6RST SPI2RST USART2RST USART3RST I2C1RST I2C2RST I2C3RST CRSRST USBFSRST PWRRST OPAMPRST LPTIM1RST

TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)

TIM6RST : TIM6 timer reset
bits : 4 - 4 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

USART2RST : USART2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART3 reset
bits : 18 - 18 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

I2C3RST : I2C3 reset
bits : 23 - 23 (1 bit)

CRSRST : CRS reset
bits : 24 - 24 (1 bit)

USBFSRST : USB FS reset
bits : 26 - 26 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

OPAMPRST : OPAMP interface reset
bits : 30 - 30 (1 bit)

LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)


APB1RSTR2

APB1 peripheral reset register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR2 APB1RSTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1RST LPTIM2RST

LPUART1RST : Low-power UART 1 reset
bits : 0 - 0 (1 bit)

LPTIM2RST : Low-power timer 2 reset
bits : 5 - 5 (1 bit)


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSICAL MSITRIM HSICAL HSITRIM

MSICAL : MSI clock calibration
bits : 0 - 7 (8 bit)
access : read-only

MSITRIM : MSI clock trimming
bits : 8 - 15 (8 bit)
access : read-write

HSICAL : HSI clock calibration
bits : 16 - 23 (8 bit)
access : read-only

HSITRIM : HSI clock trimming
bits : 24 - 28 (5 bit)
access : read-write


APB2RSTR

APB2 peripheral reset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST TIM1RST SPI1RST USART1RST TIM15RST TIM16RST

SYSCFGRST : System configuration (SYSCFG) reset
bits : 0 - 0 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

TIM15RST : TIM15 timer reset
bits : 16 - 16 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)


AHB1ENR

AHB1 peripheral clock enable register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1ENR AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN FLASHEN CRCEN TSCEN

DMA1EN : DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : DMA2 clock enable
bits : 1 - 1 (1 bit)

FLASHEN : Flash memory interface clock enable
bits : 8 - 8 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

TSCEN : Touch Sensing Controller clock enable
bits : 16 - 16 (1 bit)


AHB2ENR

AHB2 peripheral clock enable register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2ENR AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIOHEN ADCEN RNGEN

GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)

GPIOHEN : IO port H clock enable
bits : 7 - 7 (1 bit)

ADCEN : ADC clock enable
bits : 13 - 13 (1 bit)

RNGEN : Random Number Generator clock enable
bits : 18 - 18 (1 bit)


AHB3ENR

AHB3 peripheral clock enable register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3ENR AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPIEN

QSPIEN : QSPIEN
bits : 8 - 8 (1 bit)


APB1ENR1

APB1ENR1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR1 APB1ENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM6EN RTCAPBEN WWDGEN SPI2EN USART2EN USART3EN I2C1EN I2C2EN I2C3EN CRSEN USBF PWREN OPAMPEN LPTIM1EN

TIM2EN : TIM2 timer clock enable
bits : 0 - 0 (1 bit)

TIM6EN : TIM6 timer clock enable
bits : 4 - 4 (1 bit)

RTCAPBEN : RTC APB clock enable
bits : 10 - 10 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)

USART2EN : USART2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 clock enable
bits : 18 - 18 (1 bit)

I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)

I2C3EN : I2C3 clock enable
bits : 23 - 23 (1 bit)

CRSEN : CRS clock enable
bits : 24 - 24 (1 bit)

USBF : USB FS clock enable
bits : 26 - 26 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

OPAMPEN : OPAMP interface clock enable
bits : 30 - 30 (1 bit)

LPTIM1EN : Low power timer 1 clock enable
bits : 31 - 31 (1 bit)


APB1ENR2

APB1 peripheral clock enable register 2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR2 APB1ENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1EN LPTIM2EN

LPUART1EN : Low power UART 1 clock enable
bits : 0 - 0 (1 bit)

LPTIM2EN : LPTIM2EN
bits : 5 - 5 (1 bit)


APB2ENR

APB2ENR
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN FIREWALLEN TIM1EN SPI1EN USART1EN TIM15EN TIM16EN

SYSCFGEN : SYSCFG clock enable
bits : 0 - 0 (1 bit)

FIREWALLEN : Firewall clock enable
bits : 7 - 7 (1 bit)

TIM1EN : TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : USART1clock enable
bits : 14 - 14 (1 bit)

TIM15EN : TIM15 timer clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)


AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1SMENR AHB1SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1SMEN DMA2SMEN FLASHSMEN SRAM1SMEN CRCSMEN TSCSMEN

DMA1SMEN : DMA1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

DMA2SMEN : DMA2 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

FLASHSMEN : Flash memory interface clocks enable during Sleep and Stop modes
bits : 8 - 8 (1 bit)

SRAM1SMEN : SRAM1 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)

CRCSMEN : CRCSMEN
bits : 12 - 12 (1 bit)

TSCSMEN : Touch Sensing Controller clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)


AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2SMENR AHB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOASMEN GPIOBSMEN GPIOCSMEN GPIODSMEN GPIOHSMEN SRAM2SMEN ADCFSSMEN RNGSMEN

GPIOASMEN : IO port A clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

GPIOBSMEN : IO port B clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

GPIOCSMEN : IO port C clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

GPIODSMEN : IO port D clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)

GPIOHSMEN : IO port H clocks enable during Sleep and Stop modes
bits : 7 - 7 (1 bit)

SRAM2SMEN : SRAM2 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)

ADCFSSMEN : ADC clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)

RNGSMEN : Random Number Generator clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)


AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3SMENR AHB3SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPISMEN

QSPISMEN : QSPISMEN
bits : 8 - 8 (1 bit)


APB1SMENR1

APB1SMENR1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR1 APB1SMENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN TIM6SMEN RTCAPBSMEN WWDGSMEN SPI2SMEN USART2SMEN USART3SMEN I2C1SMEN I2C2SMEN I2C3SMEN CRSSMEN USBFSSMEN PWRSMEN OPAMPSMEN LPTIM1SMEN

TIM2SMEN : TIM2 timer clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

TIM6SMEN : TIM6 timer clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)

RTCAPBSMEN : RTC APB clock enable during Sleep and Stop modes
bits : 10 - 10 (1 bit)

WWDGSMEN : Window watchdog clocks enable during Sleep and Stop modes
bits : 11 - 11 (1 bit)

SPI2SMEN : SPI2 clocks enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)

USART2SMEN : USART2 clocks enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)

USART3SMEN : USART3 clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)

I2C1SMEN : I2C1 clocks enable during Sleep and Stop modes
bits : 21 - 21 (1 bit)

I2C2SMEN : I2C2 clocks enable during Sleep and Stop modes
bits : 22 - 22 (1 bit)

I2C3SMEN : I2C3 clocks enable during Sleep and Stop modes
bits : 23 - 23 (1 bit)

CRSSMEN : CRS clock enable during Sleep and Stop modes
bits : 24 - 24 (1 bit)

USBFSSMEN : USB FS clock enable during Sleep and Stop modes
bits : 26 - 26 (1 bit)

PWRSMEN : Power interface clocks enable during Sleep and Stop modes
bits : 28 - 28 (1 bit)

OPAMPSMEN : OPAMP interface clocks enable during Sleep and Stop modes
bits : 30 - 30 (1 bit)

LPTIM1SMEN : Low power timer 1 clocks enable during Sleep and Stop modes
bits : 31 - 31 (1 bit)


APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR2 APB1SMENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1SMEN LPTIM2SMEN

LPUART1SMEN : Low power UART 1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

LPTIM2SMEN : LPTIM2SMEN
bits : 5 - 5 (1 bit)


CFGR

Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 STOPWUCK MCOSEL MCOPRE

SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : PB low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

STOPWUCK : Wakeup from Stop and CSS backup clock selection
bits : 15 - 15 (1 bit)
access : read-write

MCOSEL : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write

MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-only


APB2SMENR

APB2SMENR
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2SMENR APB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGSMEN TIM1SMEN SPI1SMEN USART1SMEN TIM15SMEN TIM16SMEN

SYSCFGSMEN : SYSCFG clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

TIM1SMEN : TIM1 timer clocks enable during Sleep and Stop modes
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clocks enable during Sleep and Stop modes
bits : 12 - 12 (1 bit)

USART1SMEN : USART1clocks enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)

TIM15SMEN : TIM15 timer clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)

TIM16SMEN : TIM16 timer clocks enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)


CCIPR

CCIPR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCIPR CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SEL USART2SEL USART3SEL LPUART1SEL I2C1SEL I2C2SEL I2C3SEL LPTIM1SEL LPTIM2SEL CLK48SEL ADCSEL

USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)

USART2SEL : USART2 clock source selection
bits : 2 - 3 (2 bit)

USART3SEL : USART3 clock source selection
bits : 4 - 5 (2 bit)

LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)

I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)

I2C2SEL : I2C2 clock source selection
bits : 14 - 15 (2 bit)

I2C3SEL : I2C3 clock source selection
bits : 16 - 17 (2 bit)

LPTIM1SEL : Low power timer 1 clock source selection
bits : 18 - 19 (2 bit)

LPTIM2SEL : Low power timer 2 clock source selection
bits : 20 - 21 (2 bit)

CLK48SEL : 48 MHz clock source selection
bits : 26 - 27 (2 bit)

ADCSEL : ADCSEL
bits : 28 - 29 (2 bit)


BDCR

BDCR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV LSECSSON LSECSSD RTCSEL RTCEN BDRST LSCOEN LSCOSEL

LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEDRV : SE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write

LSECSSON : LSECSSON
bits : 5 - 5 (1 bit)
access : read-write

LSECSSD : LSECSSD
bits : 6 - 6 (1 bit)
access : read-only

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write

LSCOEN : Low speed clock output enable
bits : 24 - 24 (1 bit)
access : read-write

LSCOSEL : Low speed clock output selection
bits : 25 - 25 (1 bit)
access : read-write


CSR

CSR
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY MSISRANGE RMVF FIREWALLRSTF OBLRSTF PINRSTF BORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRSTF

LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

MSISRANGE : SI range after Standby mode
bits : 8 - 11 (4 bit)
access : read-write

RMVF : Remove reset flag
bits : 23 - 23 (1 bit)
access : read-write

FIREWALLRSTF : Firewall reset flag
bits : 24 - 24 (1 bit)
access : read-only

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-only

PINRSTF : Pin reset flag
bits : 26 - 26 (1 bit)
access : read-only

BORRSTF : BOR flag
bits : 27 - 27 (1 bit)
access : read-only

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

IWDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPWRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only


CRRCR

Clock recovery RC register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRRCR CRRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSI48ON HSI48RDY HSI48CAL

HSI48ON : HSI48 clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSI48RDY : HSI48 clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSI48CAL : HSI48 clock calibration
bits : 7 - 15 (9 bit)
access : read-only


CCIPR2

Peripherals independent clock configuration register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCIPR2 CCIPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C4SEL_0 I2C4SEL_1

I2C4SEL_0 : I2C4 clock source selection
bits : 0 - 0 (1 bit)
access : read-write

I2C4SEL_1 : I2C4 clock source selection
bits : 1 - 1 (1 bit)
access : read-only


PLLCFGR

PLL configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCFGR PLLCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC PLLM PLLN PLLPEN PLLP PLLQEN PLLQ PLLREN PLLR PLLPDIV

PLLSRC : Main PLL, PLLSAI1 and PLLSAI2 entry clock source
bits : 0 - 1 (2 bit)

PLLM : Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bits : 4 - 6 (3 bit)

PLLN : Main PLL multiplication factor for VCO
bits : 8 - 14 (7 bit)

PLLPEN : Main PLL PLLSAI3CLK output enable
bits : 16 - 16 (1 bit)

PLLP : Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bits : 17 - 17 (1 bit)

PLLQEN : Main PLL PLLUSB1CLK output enable
bits : 20 - 20 (1 bit)

PLLQ : Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bits : 21 - 22 (2 bit)

PLLREN : Main PLL PLLCLK output enable
bits : 24 - 24 (1 bit)

PLLR : Main PLL division factor for PLLCLK (system clock)
bits : 25 - 26 (2 bit)

PLLPDIV : Main PLL division factor for PLLSAI2CLK
bits : 27 - 31 (5 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.