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DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

IDCODE

APB2_FZR

CR

APB1_FZR1

APB1_FZR2


IDCODE

MCU Device ID Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDCODE IDCODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device Identifier
bits : 0 - 15 (16 bit)

REV_ID : Revision Identifier
bits : 16 - 31 (16 bit)


APB2_FZR

APB High Freeze Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2_FZR APB2_FZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM1_STOP DBG_TIM8_STOP DBG_TIM15_STOP DBG_TIM16_STOP DBG_TIM17_STOP

DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 11 - 11 (1 bit)

DBG_TIM8_STOP : TIM8 counter stopped when core is halted
bits : 13 - 13 (1 bit)

DBG_TIM15_STOP : TIM15 counter stopped when core is halted
bits : 16 - 16 (1 bit)

DBG_TIM16_STOP : TIM16 counter stopped when core is halted
bits : 17 - 17 (1 bit)

DBG_TIM17_STOP : TIM17 counter stopped when core is halted
bits : 18 - 18 (1 bit)


CR

Debug MCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_SLEEP DBG_STOP DBG_STANDBY TRACE_IOEN TRACE_MODE

DBG_SLEEP : Debug Sleep Mode
bits : 0 - 0 (1 bit)

DBG_STOP : Debug Stop Mode
bits : 1 - 1 (1 bit)

DBG_STANDBY : Debug Standby Mode
bits : 2 - 2 (1 bit)

TRACE_IOEN : Trace pin assignment control
bits : 5 - 5 (1 bit)

TRACE_MODE : Trace pin assignment control
bits : 6 - 7 (2 bit)


APB1_FZR1

APB Low Freeze Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1_FZR1 APB1_FZR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIMER2_STOP DBG_TIM3_STOP DBG_TIM4_STOP DBG_TIM5_STOP DBG_TIMER6_STOP DBG_TIM7_STOP DBG_RTC_STOP DBG_WWDG_STOP DBG_IWDG_STOP DBG_I2C1_STOP DBG_I2C2_STOP DBG_I2C3_STOP DBG_CAN_STOP DBG_LPTIMER_STOP

DBG_TIMER2_STOP : Debug Timer 2 stopped when Core is halted
bits : 0 - 0 (1 bit)

DBG_TIM3_STOP : TIM3 counter stopped when core is halted
bits : 1 - 1 (1 bit)

DBG_TIM4_STOP : TIM4 counter stopped when core is halted
bits : 2 - 2 (1 bit)

DBG_TIM5_STOP : TIM5 counter stopped when core is halted
bits : 3 - 3 (1 bit)

DBG_TIMER6_STOP : Debug Timer 6 stopped when Core is halted
bits : 4 - 4 (1 bit)

DBG_TIM7_STOP : TIM7 counter stopped when core is halted
bits : 5 - 5 (1 bit)

DBG_RTC_STOP : Debug RTC stopped when Core is halted
bits : 10 - 10 (1 bit)

DBG_WWDG_STOP : Debug Window Wachdog stopped when Core is halted
bits : 11 - 11 (1 bit)

DBG_IWDG_STOP : Debug Independent Wachdog stopped when Core is halted
bits : 12 - 12 (1 bit)

DBG_I2C1_STOP : I2C1 SMBUS timeout mode stopped when core is halted
bits : 21 - 21 (1 bit)

DBG_I2C2_STOP : I2C2 SMBUS timeout mode stopped when core is halted
bits : 22 - 22 (1 bit)

DBG_I2C3_STOP : I2C3 SMBUS timeout counter stopped when core is halted
bits : 23 - 23 (1 bit)

DBG_CAN_STOP : bxCAN stopped when core is halted
bits : 25 - 25 (1 bit)

DBG_LPTIMER_STOP : LPTIM1 counter stopped when core is halted
bits : 31 - 31 (1 bit)


APB1_FZR2

APB Low Freeze Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1_FZR2 APB1_FZR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_LPTIM2_STOP

DBG_LPTIM2_STOP : LPTIM2 counter stopped when core is halted
bits : 5 - 5 (1 bit)



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