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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

Registers

MEMRMP

EXTICR3

EXTICR4

SCSR

CFGR2

SWPR

SKR

CFGR1

EXTICR1

EXTICR2


MEMRMP

memory remap register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMRMP MEMRMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE QFS FB_MODE

MEM_MODE : Memory mapping selection
bits : 0 - 2 (3 bit)

QFS : QUADSPI memory mapping swap
bits : 3 - 3 (1 bit)

FB_MODE : Flash Bank mode selection
bits : 8 - 8 (1 bit)


EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI 8 configuration bits
bits : 0 - 2 (3 bit)

EXTI9 : EXTI 9 configuration bits
bits : 4 - 6 (3 bit)

EXTI10 : EXTI 10 configuration bits
bits : 8 - 10 (3 bit)

EXTI11 : EXTI 11 configuration bits
bits : 12 - 14 (3 bit)


EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12 configuration bits
bits : 0 - 2 (3 bit)

EXTI13 : EXTI13 configuration bits
bits : 4 - 6 (3 bit)

EXTI14 : EXTI14 configuration bits
bits : 8 - 10 (3 bit)

EXTI15 : EXTI15 configuration bits
bits : 12 - 14 (3 bit)


SCSR

SCSR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM2ER SRAM2BSY

SRAM2ER : SRAM2 Erase
bits : 0 - 0 (1 bit)
access : read-write

SRAM2BSY : SRAM2 busy by erase operation
bits : 1 - 1 (1 bit)
access : read-only


CFGR2

CFGR2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLL SPL PVDL ECCL SPF

CLL : Cortex-M4 LOCKUP (Hardfault) output enable bit
bits : 0 - 0 (1 bit)
access : write-only

SPL : SRAM2 parity lock bit
bits : 1 - 1 (1 bit)
access : write-only

PVDL : PVD lock enable bit
bits : 2 - 2 (1 bit)
access : write-only

ECCL : ECC Lock
bits : 3 - 3 (1 bit)
access : write-only

SPF : SRAM2 parity error flag
bits : 8 - 8 (1 bit)
access : read-write


SWPR

SWPR
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPR SWPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0WP P1WP P2WP P3WP P4WP P5WP P6WP P7WP P8WP P9WP P10WP P11WP P12WP P13WP P14WP P15WP P16WP P17WP P18WP P19WP P20WP P21WP P22WP P23WP P24WP P25WP P26WP P27WP P28WP P29WP P30WP P31WP

P0WP : P0WP
bits : 0 - 0 (1 bit)

P1WP : P1WP
bits : 1 - 1 (1 bit)

P2WP : P2WP
bits : 2 - 2 (1 bit)

P3WP : P3WP
bits : 3 - 3 (1 bit)

P4WP : P4WP
bits : 4 - 4 (1 bit)

P5WP : P5WP
bits : 5 - 5 (1 bit)

P6WP : P6WP
bits : 6 - 6 (1 bit)

P7WP : P7WP
bits : 7 - 7 (1 bit)

P8WP : P8WP
bits : 8 - 8 (1 bit)

P9WP : P9WP
bits : 9 - 9 (1 bit)

P10WP : P10WP
bits : 10 - 10 (1 bit)

P11WP : P11WP
bits : 11 - 11 (1 bit)

P12WP : P12WP
bits : 12 - 12 (1 bit)

P13WP : P13WP
bits : 13 - 13 (1 bit)

P14WP : P14WP
bits : 14 - 14 (1 bit)

P15WP : P15WP
bits : 15 - 15 (1 bit)

P16WP : P16WP
bits : 16 - 16 (1 bit)

P17WP : P17WP
bits : 17 - 17 (1 bit)

P18WP : P18WP
bits : 18 - 18 (1 bit)

P19WP : P19WP
bits : 19 - 19 (1 bit)

P20WP : P20WP
bits : 20 - 20 (1 bit)

P21WP : P21WP
bits : 21 - 21 (1 bit)

P22WP : P22WP
bits : 22 - 22 (1 bit)

P23WP : P23WP
bits : 23 - 23 (1 bit)

P24WP : P24WP
bits : 24 - 24 (1 bit)

P25WP : P25WP
bits : 25 - 25 (1 bit)

P26WP : P26WP
bits : 26 - 26 (1 bit)

P27WP : P27WP
bits : 27 - 27 (1 bit)

P28WP : P28WP
bits : 28 - 28 (1 bit)

P29WP : P29WP
bits : 29 - 29 (1 bit)

P30WP : P30WP
bits : 30 - 30 (1 bit)

P31WP : SRAM2 page 31 write protection
bits : 31 - 31 (1 bit)


SKR

SKR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SKR SKR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : SRAM2 write protection key for software erase
bits : 0 - 7 (8 bit)


CFGR1

configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FWDIS BOOSTEN I2C_PB6_FMP I2C_PB7_FMP I2C_PB8_FMP I2C_PB9_FMP I2C1_FMP I2C2_FMP I2C3_FMP FPU_IE

FWDIS : Firewall disable
bits : 0 - 0 (1 bit)

BOOSTEN : I/O analog switch voltage booster enable
bits : 8 - 8 (1 bit)

I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6
bits : 16 - 16 (1 bit)

I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7
bits : 17 - 17 (1 bit)

I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8
bits : 18 - 18 (1 bit)

I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9
bits : 19 - 19 (1 bit)

I2C1_FMP : I2C1 Fast-mode Plus driving capability activation
bits : 20 - 20 (1 bit)

I2C2_FMP : I2C2 Fast-mode Plus driving capability activation
bits : 21 - 21 (1 bit)

I2C3_FMP : I2C3 Fast-mode Plus driving capability activation
bits : 22 - 22 (1 bit)

FPU_IE : Floating Point Unit interrupts enable bits
bits : 26 - 31 (6 bit)


EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI 0 configuration bits
bits : 0 - 2 (3 bit)

EXTI1 : EXTI 1 configuration bits
bits : 4 - 6 (3 bit)

EXTI2 : EXTI 2 configuration bits
bits : 8 - 10 (3 bit)

EXTI3 : EXTI 3 configuration bits
bits : 12 - 14 (3 bit)


EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI 4 configuration bits
bits : 0 - 2 (3 bit)

EXTI5 : EXTI 5 configuration bits
bits : 4 - 6 (3 bit)

EXTI6 : EXTI 6 configuration bits
bits : 8 - 10 (3 bit)

EXTI7 : EXTI 7 configuration bits
bits : 12 - 14 (3 bit)



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