\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
channel 0 configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 4 configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
request generator channel 0 configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification
bits : 0 - 4 (5 bit)
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
GE : DMA request generator channel 0 enable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)
request generator channel 1 configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification
bits : 0 - 4 (5 bit)
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
GE : DMA request generator channel 1 enable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)
request generator channel 2 configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification
bits : 0 - 4 (5 bit)
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
GE : DMA request generator channel 2 enable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)
request generator channel 3 configuration register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_ID : Signal identification
bits : 0 - 4 (5 bit)
OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)
GE : DMA request generator channel 3 enable
bits : 16 - 16 (1 bit)
GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)
GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)
channel 5 configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
request generator interrupt status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OF0 : Trigger overrun event flag
bits : 0 - 0 (1 bit)
OF1 : Trigger overrun event flag
bits : 1 - 1 (1 bit)
OF2 : Trigger overrun event flag
bits : 2 - 2 (1 bit)
OF3 : Trigger overrun event flag
bits : 3 - 3 (1 bit)
request generator interrupt clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COF0 : Clear trigger overrun event flag
bits : 0 - 0 (1 bit)
COF1 : Clear trigger overrun event flag
bits : 1 - 1 (1 bit)
COF2 : Clear trigger overrun event flag
bits : 2 - 2 (1 bit)
COF3 : Clear trigger overrun event flag
bits : 3 - 3 (1 bit)
channel 6 configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 7 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 8 configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 9 configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 10 configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 11 configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 12 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 13 configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 1 configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel 2 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF0 : Synchronization overrun event flag
bits : 0 - 0 (1 bit)
SOF1 : Synchronization overrun event flag
bits : 1 - 1 (1 bit)
SOF2 : Synchronization overrun event flag
bits : 2 - 2 (1 bit)
SOF3 : Synchronization overrun event flag
bits : 3 - 3 (1 bit)
SOF4 : Synchronization overrun event flag
bits : 4 - 4 (1 bit)
SOF5 : Synchronization overrun event flag
bits : 5 - 5 (1 bit)
SOF6 : Synchronization overrun event flag
bits : 6 - 6 (1 bit)
SOF7 : Synchronization overrun event flag
bits : 7 - 7 (1 bit)
SOF8 : Synchronization overrun event flag
bits : 8 - 8 (1 bit)
SOF9 : Synchronization overrun event flag
bits : 9 - 9 (1 bit)
SOF10 : Synchronization overrun event flag
bits : 10 - 10 (1 bit)
SOF11 : Synchronization overrun event flag
bits : 11 - 11 (1 bit)
SOF12 : Synchronization overrun event flag
bits : 12 - 12 (1 bit)
SOF13 : Synchronization overrun event flag
bits : 13 - 13 (1 bit)
clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CSOF0 : Clear synchronization overrun event flag
bits : 0 - 0 (1 bit)
CSOF1 : Clear synchronization overrun event flag
bits : 1 - 1 (1 bit)
CSOF2 : Clear synchronization overrun event flag
bits : 2 - 2 (1 bit)
CSOF3 : Clear synchronization overrun event flag
bits : 3 - 3 (1 bit)
CSOF4 : Clear synchronization overrun event flag
bits : 4 - 4 (1 bit)
CSOF5 : Clear synchronization overrun event flag
bits : 5 - 5 (1 bit)
CSOF6 : Clear synchronization overrun event flag
bits : 6 - 6 (1 bit)
CSOF7 : Clear synchronization overrun event flag
bits : 7 - 7 (1 bit)
CSOF8 : Clear synchronization overrun event flag
bits : 8 - 8 (1 bit)
CSOF9 : Clear synchronization overrun event flag
bits : 9 - 9 (1 bit)
CSOF10 : Clear synchronization overrun event flag
bits : 10 - 10 (1 bit)
CSOF11 : Clear synchronization overrun event flag
bits : 11 - 11 (1 bit)
CSOF12 : Clear synchronization overrun event flag
bits : 12 - 12 (1 bit)
CSOF13 : Clear synchronization overrun event flag
bits : 13 - 13 (1 bit)
channel 3 configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)
SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)
EGE : Event generation enable
bits : 9 - 9 (1 bit)
SE : Synchronization enable
bits : 16 - 16 (1 bit)
SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)
NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)
SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)
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