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DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

C0CR

C4CR

RG0CR

RG1CR

RG2CR

RG3CR

C5CR

RGSR

RGCFR

C6CR

C7CR

C8CR

C9CR

C10CR

C11CR

C12CR

C13CR

C1CR

C2CR

CSR

CFR

C3CR


C0CR

channel 0 configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0CR C0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C4CR

channel 4 configuration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C4CR C4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


RG0CR

request generator channel 0 configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0CR RG0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal identification
bits : 0 - 4 (5 bit)

OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)

GE : DMA request generator channel 0 enable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)


RG1CR

request generator channel 1 configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1CR RG1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal identification
bits : 0 - 4 (5 bit)

OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)

GE : DMA request generator channel 1 enable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)


RG2CR

request generator channel 2 configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG2CR RG2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal identification
bits : 0 - 4 (5 bit)

OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)

GE : DMA request generator channel 2 enable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)


RG3CR

request generator channel 3 configuration register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG3CR RG3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal identification
bits : 0 - 4 (5 bit)

OIE : Trigger overrun interrupt enable
bits : 8 - 8 (1 bit)

GE : DMA request generator channel 3 enable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to be generated minus 1
bits : 19 - 23 (5 bit)


C5CR

channel 5 configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C5CR C5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


RGSR

request generator interrupt status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RGSR RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF0 OF1 OF2 OF3

OF0 : Trigger overrun event flag
bits : 0 - 0 (1 bit)

OF1 : Trigger overrun event flag
bits : 1 - 1 (1 bit)

OF2 : Trigger overrun event flag
bits : 2 - 2 (1 bit)

OF3 : Trigger overrun event flag
bits : 3 - 3 (1 bit)


RGCFR

request generator interrupt clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RGCFR RGCFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COF0 COF1 COF2 COF3

COF0 : Clear trigger overrun event flag
bits : 0 - 0 (1 bit)

COF1 : Clear trigger overrun event flag
bits : 1 - 1 (1 bit)

COF2 : Clear trigger overrun event flag
bits : 2 - 2 (1 bit)

COF3 : Clear trigger overrun event flag
bits : 3 - 3 (1 bit)


C6CR

channel 6 configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C6CR C6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C7CR

channel 7 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C7CR C7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C8CR

channel 8 configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C8CR C8CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C9CR

channel 9 configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C9CR C9CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C10CR

channel 10 configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C10CR C10CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C11CR

channel 11 configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C11CR C11CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C12CR

channel 12 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C12CR C12CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C13CR

channel 13 configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C13CR C13CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C1CR

channel 1 configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1CR C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C2CR

channel 2 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2CR C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


CSR

channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF0 SOF1 SOF2 SOF3 SOF4 SOF5 SOF6 SOF7 SOF8 SOF9 SOF10 SOF11 SOF12 SOF13

SOF0 : Synchronization overrun event flag
bits : 0 - 0 (1 bit)

SOF1 : Synchronization overrun event flag
bits : 1 - 1 (1 bit)

SOF2 : Synchronization overrun event flag
bits : 2 - 2 (1 bit)

SOF3 : Synchronization overrun event flag
bits : 3 - 3 (1 bit)

SOF4 : Synchronization overrun event flag
bits : 4 - 4 (1 bit)

SOF5 : Synchronization overrun event flag
bits : 5 - 5 (1 bit)

SOF6 : Synchronization overrun event flag
bits : 6 - 6 (1 bit)

SOF7 : Synchronization overrun event flag
bits : 7 - 7 (1 bit)

SOF8 : Synchronization overrun event flag
bits : 8 - 8 (1 bit)

SOF9 : Synchronization overrun event flag
bits : 9 - 9 (1 bit)

SOF10 : Synchronization overrun event flag
bits : 10 - 10 (1 bit)

SOF11 : Synchronization overrun event flag
bits : 11 - 11 (1 bit)

SOF12 : Synchronization overrun event flag
bits : 12 - 12 (1 bit)

SOF13 : Synchronization overrun event flag
bits : 13 - 13 (1 bit)


CFR

clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CFR CFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF0 CSOF1 CSOF2 CSOF3 CSOF4 CSOF5 CSOF6 CSOF7 CSOF8 CSOF9 CSOF10 CSOF11 CSOF12 CSOF13

CSOF0 : Clear synchronization overrun event flag
bits : 0 - 0 (1 bit)

CSOF1 : Clear synchronization overrun event flag
bits : 1 - 1 (1 bit)

CSOF2 : Clear synchronization overrun event flag
bits : 2 - 2 (1 bit)

CSOF3 : Clear synchronization overrun event flag
bits : 3 - 3 (1 bit)

CSOF4 : Clear synchronization overrun event flag
bits : 4 - 4 (1 bit)

CSOF5 : Clear synchronization overrun event flag
bits : 5 - 5 (1 bit)

CSOF6 : Clear synchronization overrun event flag
bits : 6 - 6 (1 bit)

CSOF7 : Clear synchronization overrun event flag
bits : 7 - 7 (1 bit)

CSOF8 : Clear synchronization overrun event flag
bits : 8 - 8 (1 bit)

CSOF9 : Clear synchronization overrun event flag
bits : 9 - 9 (1 bit)

CSOF10 : Clear synchronization overrun event flag
bits : 10 - 10 (1 bit)

CSOF11 : Clear synchronization overrun event flag
bits : 11 - 11 (1 bit)

CSOF12 : Clear synchronization overrun event flag
bits : 12 - 12 (1 bit)

CSOF13 : Clear synchronization overrun event flag
bits : 13 - 13 (1 bit)


C3CR

channel 3 configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C3CR C3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)



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