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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

ADC_ISR (ISR)

ADC_CFGR2 (CFGR2)

ADC_SMPR1 (SMPR1)

ADC_SMPR2 (SMPR2)

ADC_PCSEL (PCSEL)

ADC_LTR1 (LTR1)

ADC_HTR1 (HTR1)

ADC_SQR1 (SQR1)

ADC_SQR2 (SQR2)

ADC_SQR3 (SQR3)

ADC_SQR4 (SQR4)

ADC_IER (IER)

ADC_DR (DR)

ADC_JSQR (JSQR)

ADC_OFR1 (OFR1)

ADC_OFR2 (OFR2)

ADC_OFR3 (OFR3)

ADC_OFR4 (OFR4)

ADC_CR (CR)

ADC_JDR1 (JDR1)

ADC_JDR2 (JDR2)

ADC_JDR3 (JDR3)

ADC_JDR4 (JDR4)

ADC_AWD2CR (AWD2CR)

ADC_AWD3CR (AWD3CR)

ADC_LTR2 (LTR2)

ADC_HTR2 (HTR2)

ADC_LTR3 (LTR3)

ADC_HTR3 (HTR3)

ADC_CFGR (CFGR)

ADC_DIFSEL (DIFSEL)

ADC_CALFACT (CALFACT)

ADC_CALFACT2 (CALFACT2)


ADC_ISR (ISR)

ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ISR ADC_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDY EOSMP EOC EOS OVR JEOC JEOS AWD1 AWD2 AWD3 JQOVF

ADRDY : ADRDY
bits : 0 - 0 (1 bit)

EOSMP : EOSMP
bits : 1 - 1 (1 bit)

EOC : EOC
bits : 2 - 2 (1 bit)

EOS : EOS
bits : 3 - 3 (1 bit)

OVR : OVR
bits : 4 - 4 (1 bit)

JEOC : JEOC
bits : 5 - 5 (1 bit)

JEOS : JEOS
bits : 6 - 6 (1 bit)

AWD1 : AWD1
bits : 7 - 7 (1 bit)

AWD2 : AWD2
bits : 8 - 8 (1 bit)

AWD3 : AWD3
bits : 9 - 9 (1 bit)

JQOVF : JQOVF
bits : 10 - 10 (1 bit)


ADC_CFGR2 (CFGR2)

ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFGR2 ADC_CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROVSE JOVSE OVSS TROVS ROVSM RSHIFT1 RSHIFT2 RSHIFT3 RSHIFT4 OSVR LSHIFT

ROVSE : ROVSE
bits : 0 - 0 (1 bit)

JOVSE : JOVSE
bits : 1 - 1 (1 bit)

OVSS : OVSS
bits : 5 - 8 (4 bit)

TROVS : TROVS
bits : 9 - 9 (1 bit)

ROVSM : ROVSM
bits : 10 - 10 (1 bit)

RSHIFT1 : RSHIFT1
bits : 11 - 11 (1 bit)

RSHIFT2 : RSHIFT2
bits : 12 - 12 (1 bit)

RSHIFT3 : RSHIFT3
bits : 13 - 13 (1 bit)

RSHIFT4 : RSHIFT4
bits : 14 - 14 (1 bit)

OSVR : OSVR
bits : 16 - 25 (10 bit)

LSHIFT : LSHIFT
bits : 28 - 31 (4 bit)


ADC_SMPR1 (SMPR1)

ADC sample time register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SMPR1 ADC_SMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP0 SMP1 SMP2 SMP3 SMP4 SMP5 SMP6 SMP7 SMP8 SMP9

SMP0 : SMP0
bits : 0 - 2 (3 bit)

SMP1 : SMP1
bits : 3 - 5 (3 bit)

SMP2 : SMP2
bits : 6 - 8 (3 bit)

SMP3 : SMP3
bits : 9 - 11 (3 bit)

SMP4 : SMP4
bits : 12 - 14 (3 bit)

SMP5 : SMP5
bits : 15 - 17 (3 bit)

SMP6 : SMP6
bits : 18 - 20 (3 bit)

SMP7 : SMP7
bits : 21 - 23 (3 bit)

SMP8 : SMP8
bits : 24 - 26 (3 bit)

SMP9 : SMP9
bits : 27 - 29 (3 bit)


ADC_SMPR2 (SMPR2)

ADC sample time register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SMPR2 ADC_SMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP10 SMP11 SMP12 SMP13 SMP14 SMP15 SMP16 SMP17 SMP18 SMP19

SMP10 : SMP10
bits : 0 - 2 (3 bit)

SMP11 : SMP11
bits : 3 - 5 (3 bit)

SMP12 : SMP12
bits : 6 - 8 (3 bit)

SMP13 : SMP13
bits : 9 - 11 (3 bit)

SMP14 : SMP14
bits : 12 - 14 (3 bit)

SMP15 : SMP15
bits : 15 - 17 (3 bit)

SMP16 : SMP16
bits : 18 - 20 (3 bit)

SMP17 : SMP17
bits : 21 - 23 (3 bit)

SMP18 : SMP18
bits : 24 - 26 (3 bit)

SMP19 : SMP19
bits : 27 - 29 (3 bit)


ADC_PCSEL (PCSEL)

ADC channel preselection register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_PCSEL ADC_PCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCSEL0 PCSEL1 PCSEL2 PCSEL3 PCSEL4 PCSEL5 PCSEL6 PCSEL7 PCSEL8 PCSEL9 PCSEL10 PCSEL11 PCSEL12 PCSEL13 PCSEL14 PCSEL15 PCSEL16 PCSEL17 PCSEL18 PCSEL19

PCSEL0 : PCSEL0
bits : 0 - 0 (1 bit)

PCSEL1 : PCSEL1
bits : 1 - 1 (1 bit)

PCSEL2 : PCSEL2
bits : 2 - 2 (1 bit)

PCSEL3 : PCSEL3
bits : 3 - 3 (1 bit)

PCSEL4 : PCSEL4
bits : 4 - 4 (1 bit)

PCSEL5 : PCSEL5
bits : 5 - 5 (1 bit)

PCSEL6 : PCSEL6
bits : 6 - 6 (1 bit)

PCSEL7 : PCSEL7
bits : 7 - 7 (1 bit)

PCSEL8 : PCSEL8
bits : 8 - 8 (1 bit)

PCSEL9 : PCSEL9
bits : 9 - 9 (1 bit)

PCSEL10 : PCSEL10
bits : 10 - 10 (1 bit)

PCSEL11 : PCSEL11
bits : 11 - 11 (1 bit)

PCSEL12 : PCSEL12
bits : 12 - 12 (1 bit)

PCSEL13 : PCSEL13
bits : 13 - 13 (1 bit)

PCSEL14 : PCSEL14
bits : 14 - 14 (1 bit)

PCSEL15 : PCSEL15
bits : 15 - 15 (1 bit)

PCSEL16 : PCSEL16
bits : 16 - 16 (1 bit)

PCSEL17 : PCSEL17
bits : 17 - 17 (1 bit)

PCSEL18 : PCSEL18
bits : 18 - 18 (1 bit)

PCSEL19 : PCSEL19
bits : 19 - 19 (1 bit)


ADC_LTR1 (LTR1)

ADC watchdog threshold register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LTR1 ADC_LTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTR1

LTR1 : LTR1
bits : 0 - 25 (26 bit)


ADC_HTR1 (HTR1)

ADC watchdog threshold register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HTR1 ADC_HTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTR1

HTR1 : HTR1
bits : 0 - 25 (26 bit)


ADC_SQR1 (SQR1)

ADC regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SQR1 ADC_SQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L SQ1 SQ2 SQ3 SQ4

L : L
bits : 0 - 3 (4 bit)

SQ1 : SQ1
bits : 6 - 10 (5 bit)

SQ2 : SQ2
bits : 12 - 16 (5 bit)

SQ3 : SQ3
bits : 18 - 22 (5 bit)

SQ4 : SQ4
bits : 24 - 28 (5 bit)


ADC_SQR2 (SQR2)

ADC regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SQR2 ADC_SQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ5 SQ6 SQ7 SQ8 SQ9

SQ5 : SQ5
bits : 0 - 4 (5 bit)

SQ6 : SQ6
bits : 6 - 10 (5 bit)

SQ7 : SQ7
bits : 12 - 16 (5 bit)

SQ8 : SQ8
bits : 18 - 22 (5 bit)

SQ9 : SQ9
bits : 24 - 28 (5 bit)


ADC_SQR3 (SQR3)

ADC regular sequence register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SQR3 ADC_SQR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ10 SQ11 SQ12 SQ13 SQ14

SQ10 : SQ10
bits : 0 - 4 (5 bit)

SQ11 : SQ11
bits : 6 - 10 (5 bit)

SQ12 : SQ12
bits : 12 - 16 (5 bit)

SQ13 : SQ13
bits : 18 - 22 (5 bit)

SQ14 : SQ14
bits : 24 - 28 (5 bit)


ADC_SQR4 (SQR4)

ADC regular sequence register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SQR4 ADC_SQR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ15 SQ16

SQ15 : SQ15
bits : 0 - 4 (5 bit)

SQ16 : SQ16
bits : 6 - 10 (5 bit)


ADC_IER (IER)

ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IER ADC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDYIE EOSMPIE EOCIE EOSIE OVRIE JEOCIE JEOSIE AWD1IE AWD2IE AWD3IE JQOVFIE

ADRDYIE : ADRDYIE
bits : 0 - 0 (1 bit)

EOSMPIE : EOSMPIE
bits : 1 - 1 (1 bit)

EOCIE : EOCIE
bits : 2 - 2 (1 bit)

EOSIE : EOSIE
bits : 3 - 3 (1 bit)

OVRIE : OVRIE
bits : 4 - 4 (1 bit)

JEOCIE : JEOCIE
bits : 5 - 5 (1 bit)

JEOSIE : JEOSIE
bits : 6 - 6 (1 bit)

AWD1IE : AWD1IE
bits : 7 - 7 (1 bit)

AWD2IE : AWD2IE
bits : 8 - 8 (1 bit)

AWD3IE : AWD3IE
bits : 9 - 9 (1 bit)

JQOVFIE : JQOVFIE
bits : 10 - 10 (1 bit)


ADC_DR (DR)

ADC regular Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DR ADC_DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : RDATA
bits : 0 - 31 (32 bit)


ADC_JSQR (JSQR)

ADC injected sequence register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_JSQR ADC_JSQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JL JEXTSEL JEXTEN JSQ1 JSQ2 JSQ3 JSQ4

JL : JL
bits : 0 - 1 (2 bit)

JEXTSEL : JEXTSEL
bits : 2 - 6 (5 bit)

JEXTEN : JEXTEN
bits : 7 - 8 (2 bit)

JSQ1 : JSQ1
bits : 9 - 13 (5 bit)

JSQ2 : JSQ2
bits : 15 - 19 (5 bit)

JSQ3 : JSQ3
bits : 21 - 25 (5 bit)

JSQ4 : JSQ4
bits : 27 - 31 (5 bit)


ADC_OFR1 (OFR1)

ADC offset register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR1 ADC_OFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET1 OFFSET1_CH SSATE

OFFSET1 : OFFSET1
bits : 0 - 25 (26 bit)

OFFSET1_CH : OFFSET1_CH
bits : 26 - 30 (5 bit)

SSATE : SSATE
bits : 31 - 31 (1 bit)


ADC_OFR2 (OFR2)

ADC offset register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR2 ADC_OFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET2 OFFSET2_CH SSATE

OFFSET2 : OFFSET2
bits : 0 - 25 (26 bit)

OFFSET2_CH : OFFSET2_CH
bits : 26 - 30 (5 bit)

SSATE : SSATE
bits : 31 - 31 (1 bit)


ADC_OFR3 (OFR3)

ADC offset register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR3 ADC_OFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET3 OFFSET3_CH SSATE

OFFSET3 : OFFSET3
bits : 0 - 25 (26 bit)

OFFSET3_CH : OFFSET3_CH
bits : 26 - 30 (5 bit)

SSATE : SSATE
bits : 31 - 31 (1 bit)


ADC_OFR4 (OFR4)

ADC offset register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFR4 ADC_OFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET4 OFFSET4_CH SSATE

OFFSET4 : OFFSET4
bits : 0 - 25 (26 bit)

OFFSET4_CH : OFFSET4_CH
bits : 26 - 30 (5 bit)

SSATE : SSATE
bits : 31 - 31 (1 bit)


ADC_CR (CR)

ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CR ADC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN ADDIS ADSTART JADSTART ADSTP JADSTP BOOST ADCALLIN LINCALRDYW1 LINCALRDYW2 LINCALRDYW3 LINCALRDYW4 LINCALRDYW5 LINCALRDYW6 ADVREGEN DEEPPWD ADCALDIF ADCAL

ADEN : ADEN
bits : 0 - 0 (1 bit)

ADDIS : ADDIS
bits : 1 - 1 (1 bit)

ADSTART : ADSTART
bits : 2 - 2 (1 bit)

JADSTART : JADSTART
bits : 3 - 3 (1 bit)

ADSTP : ADSTP
bits : 4 - 4 (1 bit)

JADSTP : JADSTP
bits : 5 - 5 (1 bit)

BOOST : BOOST
bits : 8 - 8 (1 bit)

ADCALLIN : ADCALLIN
bits : 16 - 16 (1 bit)

LINCALRDYW1 : LINCALRDYW1
bits : 22 - 22 (1 bit)

LINCALRDYW2 : LINCALRDYW2
bits : 23 - 23 (1 bit)

LINCALRDYW3 : LINCALRDYW3
bits : 24 - 24 (1 bit)

LINCALRDYW4 : LINCALRDYW4
bits : 25 - 25 (1 bit)

LINCALRDYW5 : LINCALRDYW5
bits : 26 - 26 (1 bit)

LINCALRDYW6 : LINCALRDYW6
bits : 27 - 27 (1 bit)

ADVREGEN : ADVREGEN
bits : 28 - 28 (1 bit)

DEEPPWD : DEEPPWD
bits : 29 - 29 (1 bit)

ADCALDIF : ADCALDIF
bits : 30 - 30 (1 bit)

ADCAL : ADCAL
bits : 31 - 31 (1 bit)


ADC_JDR1 (JDR1)

ADC injected data register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_JDR1 ADC_JDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 31 (32 bit)


ADC_JDR2 (JDR2)

ADC injected data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_JDR2 ADC_JDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 31 (32 bit)


ADC_JDR3 (JDR3)

ADC injected data register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_JDR3 ADC_JDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 31 (32 bit)


ADC_JDR4 (JDR4)

ADC injected data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_JDR4 ADC_JDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA

JDATA : JDATA
bits : 0 - 31 (32 bit)


ADC_AWD2CR (AWD2CR)

ADC analog watchdog 2 configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD2CR ADC_AWD2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD2CH

AWD2CH : AWD2CH
bits : 0 - 19 (20 bit)


ADC_AWD3CR (AWD3CR)

ADC analog watchdog 3 configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AWD3CR ADC_AWD3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD3CH

AWD3CH : AWD3CH
bits : 0 - 19 (20 bit)


ADC_LTR2 (LTR2)

ADC watchdog lower threshold register 2
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LTR2 ADC_LTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTR2

LTR2 : LTR2
bits : 0 - 25 (26 bit)


ADC_HTR2 (HTR2)

ADC watchdog higher threshold register 2
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HTR2 ADC_HTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTR2

HTR2 : HTR2
bits : 0 - 25 (26 bit)


ADC_LTR3 (LTR3)

ADC watchdog lower threshold register 3
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_LTR3 ADC_LTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTR3

LTR3 : LTR3
bits : 0 - 25 (26 bit)


ADC_HTR3 (HTR3)

ADC watchdog higher threshold register 3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_HTR3 ADC_HTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTR3

HTR3 : HTR3
bits : 0 - 25 (26 bit)


ADC_CFGR (CFGR)

ADC configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFGR ADC_CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMNGT RES EXTSEL EXTEN OVRMOD CONT AUTDLY DISCEN DISCNUM JDISCEN JQM AWD1SGL AWD1EN JAWD1EN JAUTO AWD1CH JQDIS

DMNGT : DMNGT
bits : 0 - 1 (2 bit)

RES : RES
bits : 2 - 4 (3 bit)

EXTSEL : EXTSEL
bits : 5 - 9 (5 bit)

EXTEN : EXTEN
bits : 10 - 11 (2 bit)

OVRMOD : OVRMOD
bits : 12 - 12 (1 bit)

CONT : CONT
bits : 13 - 13 (1 bit)

AUTDLY : AUTDLY
bits : 14 - 14 (1 bit)

DISCEN : DISCEN
bits : 16 - 16 (1 bit)

DISCNUM : DISCNUM
bits : 17 - 19 (3 bit)

JDISCEN : JDISCEN
bits : 20 - 20 (1 bit)

JQM : JQM
bits : 21 - 21 (1 bit)

AWD1SGL : AWD1SGL
bits : 22 - 22 (1 bit)

AWD1EN : AWD1EN
bits : 23 - 23 (1 bit)

JAWD1EN : JAWD1EN
bits : 24 - 24 (1 bit)

JAUTO : JAUTO
bits : 25 - 25 (1 bit)

AWD1CH : AWD1CH
bits : 26 - 30 (5 bit)

JQDIS : JQDIS
bits : 31 - 31 (1 bit)


ADC_DIFSEL (DIFSEL)

ADC differential mode selection register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DIFSEL ADC_DIFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIFSEL

DIFSEL : DIFSEL
bits : 0 - 19 (20 bit)


ADC_CALFACT (CALFACT)

ADC calibration factors register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CALFACT ADC_CALFACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALFACT_S CALFACT_D

CALFACT_S : CALFACT_S
bits : 0 - 10 (11 bit)

CALFACT_D : CALFACT_D
bits : 16 - 26 (11 bit)


ADC_CALFACT2 (CALFACT2)

ADC calibration factor register 2
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CALFACT2 ADC_CALFACT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINCALFACT

LINCALFACT : LINCALFACT
bits : 0 - 29 (30 bit)



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