\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
CRYP control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALGODIR : ALGODIR
bits : 2 - 2 (1 bit)
access : read-write
ALGOMODE : ALGOMODE
bits : 3 - 5 (3 bit)
access : read-write
DATATYPE : DATATYPE
bits : 6 - 7 (2 bit)
access : read-write
KEYSIZE : KEYSIZE
bits : 8 - 9 (2 bit)
access : read-write
FFLUSH : FFLUSH
bits : 14 - 14 (1 bit)
access : write-only
CRYPEN : CRYPEN
bits : 15 - 15 (1 bit)
access : read-write
GCM_CCMPH : GCM_CCMPH
bits : 16 - 17 (2 bit)
access : read-write
ALGOMODE3 : ALGOMODE3
bits : 19 - 19 (1 bit)
access : read-write
NPBLB : NPBLB
bits : 20 - 23 (4 bit)
access : read-write
CRYP DMA control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIEN : DIEN
bits : 0 - 0 (1 bit)
DOEN : DOEN
bits : 1 - 1 (1 bit)
The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIM : INIM
bits : 0 - 0 (1 bit)
OUTIM : OUTIM
bits : 1 - 1 (1 bit)
The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INRIS : INRIS
bits : 0 - 0 (1 bit)
OUTRIS : OUTRIS
bits : 1 - 1 (1 bit)
The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INMIS : INMIS
bits : 0 - 0 (1 bit)
OUTMIS : OUTMIS
bits : 1 - 1 (1 bit)
CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
K : K
bits : 0 - 31 (32 bit)
CRYP hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFG1 : CFG1
bits : 0 - 3 (4 bit)
CFG2 : CFG2
bits : 4 - 7 (4 bit)
CFG3 : CFG3
bits : 8 - 11 (4 bit)
CFG4 : CFG4
bits : 12 - 15 (4 bit)
CRYP HW Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VER : VER
bits : 0 - 7 (8 bit)
CRYP Identification
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
CRYP HW Magic ID
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MID : MID
bits : 0 - 31 (32 bit)
CRYP status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IFEM : IFEM
bits : 0 - 0 (1 bit)
IFNF : IFNF
bits : 1 - 1 (1 bit)
OFNE : OFNE
bits : 2 - 2 (1 bit)
OFFU : OFFU
bits : 3 - 3 (1 bit)
BUSY : BUSY
bits : 4 - 4 (1 bit)
The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV31 : IV31
bits : 0 - 0 (1 bit)
IV30 : IV30
bits : 1 - 1 (1 bit)
IV29 : IV29
bits : 2 - 2 (1 bit)
IV28 : IV28
bits : 3 - 3 (1 bit)
IV27 : IV27
bits : 4 - 4 (1 bit)
IV26 : IV26
bits : 5 - 5 (1 bit)
IV25 : IV25
bits : 6 - 6 (1 bit)
IV24 : IV24
bits : 7 - 7 (1 bit)
IV23 : IV23
bits : 8 - 8 (1 bit)
IV22 : IV22
bits : 9 - 9 (1 bit)
IV21 : IV21
bits : 10 - 10 (1 bit)
IV20 : IV20
bits : 11 - 11 (1 bit)
IV19 : IV19
bits : 12 - 12 (1 bit)
IV18 : IV18
bits : 13 - 13 (1 bit)
IV17 : IV17
bits : 14 - 14 (1 bit)
IV16 : IV16
bits : 15 - 15 (1 bit)
IV15 : IV15
bits : 16 - 16 (1 bit)
IV14 : IV14
bits : 17 - 17 (1 bit)
IV13 : IV13
bits : 18 - 18 (1 bit)
IV12 : IV12
bits : 19 - 19 (1 bit)
IV11 : IV11
bits : 20 - 20 (1 bit)
IV10 : IV10
bits : 21 - 21 (1 bit)
IV9 : IV9
bits : 22 - 22 (1 bit)
IV8 : IV8
bits : 23 - 23 (1 bit)
IV7 : IV7
bits : 24 - 24 (1 bit)
IV6 : IV6
bits : 25 - 25 (1 bit)
IV5 : IV5
bits : 26 - 26 (1 bit)
IV4 : IV4
bits : 27 - 27 (1 bit)
IV3 : IV3
bits : 28 - 28 (1 bit)
IV2 : IV2
bits : 29 - 29 (1 bit)
IV1 : IV1
bits : 30 - 30 (1 bit)
IV0 : IV0
bits : 31 - 31 (1 bit)
Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV63 : IV63
bits : 0 - 0 (1 bit)
IV62 : IV62
bits : 1 - 1 (1 bit)
IV61 : IV61
bits : 2 - 2 (1 bit)
IV60 : IV60
bits : 3 - 3 (1 bit)
IV59 : IV59
bits : 4 - 4 (1 bit)
IV58 : IV58
bits : 5 - 5 (1 bit)
IV57 : IV57
bits : 6 - 6 (1 bit)
IV56 : IV56
bits : 7 - 7 (1 bit)
IV55 : IV55
bits : 8 - 8 (1 bit)
IV54 : IV54
bits : 9 - 9 (1 bit)
IV53 : IV53
bits : 10 - 10 (1 bit)
IV52 : IV52
bits : 11 - 11 (1 bit)
IV51 : IV51
bits : 12 - 12 (1 bit)
IV50 : IV50
bits : 13 - 13 (1 bit)
IV49 : IV49
bits : 14 - 14 (1 bit)
IV48 : IV48
bits : 15 - 15 (1 bit)
IV47 : IV47
bits : 16 - 16 (1 bit)
IV46 : IV46
bits : 17 - 17 (1 bit)
IV45 : IV45
bits : 18 - 18 (1 bit)
IV44 : IV44
bits : 19 - 19 (1 bit)
IV43 : IV43
bits : 20 - 20 (1 bit)
IV42 : IV42
bits : 21 - 21 (1 bit)
IV41 : IV41
bits : 22 - 22 (1 bit)
IV40 : IV40
bits : 23 - 23 (1 bit)
IV39 : IV39
bits : 24 - 24 (1 bit)
IV38 : IV38
bits : 25 - 25 (1 bit)
IV37 : IV37
bits : 26 - 26 (1 bit)
IV36 : IV36
bits : 27 - 27 (1 bit)
IV35 : IV35
bits : 28 - 28 (1 bit)
IV34 : IV34
bits : 29 - 29 (1 bit)
IV33 : IV33
bits : 30 - 30 (1 bit)
IV32 : IV32
bits : 31 - 31 (1 bit)
Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV95 : IV95
bits : 0 - 0 (1 bit)
IV94 : IV94
bits : 1 - 1 (1 bit)
IV93 : IV93
bits : 2 - 2 (1 bit)
IV92 : IV92
bits : 3 - 3 (1 bit)
IV91 : IV91
bits : 4 - 4 (1 bit)
IV90 : IV90
bits : 5 - 5 (1 bit)
IV89 : IV89
bits : 6 - 6 (1 bit)
IV88 : IV88
bits : 7 - 7 (1 bit)
IV87 : IV87
bits : 8 - 8 (1 bit)
IV86 : IV86
bits : 9 - 9 (1 bit)
IV85 : IV85
bits : 10 - 10 (1 bit)
IV84 : IV84
bits : 11 - 11 (1 bit)
IV83 : IV83
bits : 12 - 12 (1 bit)
IV82 : IV82
bits : 13 - 13 (1 bit)
IV81 : IV81
bits : 14 - 14 (1 bit)
IV80 : IV80
bits : 15 - 15 (1 bit)
IV79 : IV79
bits : 16 - 16 (1 bit)
IV78 : IV78
bits : 17 - 17 (1 bit)
IV77 : IV77
bits : 18 - 18 (1 bit)
IV76 : IV76
bits : 19 - 19 (1 bit)
IV75 : IV75
bits : 20 - 20 (1 bit)
IV74 : IV74
bits : 21 - 21 (1 bit)
IV73 : IV73
bits : 22 - 22 (1 bit)
IV72 : IV72
bits : 23 - 23 (1 bit)
IV71 : IV71
bits : 24 - 24 (1 bit)
IV70 : IV70
bits : 25 - 25 (1 bit)
IV69 : IV69
bits : 26 - 26 (1 bit)
IV68 : IV68
bits : 27 - 27 (1 bit)
IV67 : IV67
bits : 28 - 28 (1 bit)
IV66 : IV66
bits : 29 - 29 (1 bit)
IV65 : IV65
bits : 30 - 30 (1 bit)
IV64 : IV64
bits : 31 - 31 (1 bit)
Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV127 : IV127
bits : 0 - 0 (1 bit)
IV126 : IV126
bits : 1 - 1 (1 bit)
IV125 : IV125
bits : 2 - 2 (1 bit)
IV124 : IV124
bits : 3 - 3 (1 bit)
IV123 : IV123
bits : 4 - 4 (1 bit)
IV122 : IV122
bits : 5 - 5 (1 bit)
IV121 : IV121
bits : 6 - 6 (1 bit)
IV120 : IV120
bits : 7 - 7 (1 bit)
IV119 : IV119
bits : 8 - 8 (1 bit)
IV118 : IV118
bits : 9 - 9 (1 bit)
IV117 : IV117
bits : 10 - 10 (1 bit)
IV116 : IV116
bits : 11 - 11 (1 bit)
IV115 : IV115
bits : 12 - 12 (1 bit)
IV114 : IV114
bits : 13 - 13 (1 bit)
IV113 : IV113
bits : 14 - 14 (1 bit)
IV112 : IV112
bits : 15 - 15 (1 bit)
IV111 : IV111
bits : 16 - 16 (1 bit)
IV110 : IV110
bits : 17 - 17 (1 bit)
IV109 : IV109
bits : 18 - 18 (1 bit)
IV108 : IV108
bits : 19 - 19 (1 bit)
IV107 : IV107
bits : 20 - 20 (1 bit)
IV106 : IV106
bits : 21 - 21 (1 bit)
IV105 : IV105
bits : 22 - 22 (1 bit)
IV104 : IV104
bits : 23 - 23 (1 bit)
IV103 : IV103
bits : 24 - 24 (1 bit)
IV102 : IV102
bits : 25 - 25 (1 bit)
IV101 : IV101
bits : 26 - 26 (1 bit)
IV100 : IV100
bits : 27 - 27 (1 bit)
IV99 : IV99
bits : 28 - 28 (1 bit)
IV98 : IV98
bits : 29 - 29 (1 bit)
IV97 : IV97
bits : 30 - 30 (1 bit)
IV96 : IV96
bits : 31 - 31 (1 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM0 : CSGCMCCM0
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM1 : CSGCMCCM1
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM2 : CSGCMCCM2
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM3 : CSGCMCCM3
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM4 : CSGCMCCM4
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM5 : CSGCMCCM5
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM6 : CSGCMCCM6
bits : 0 - 31 (32 bit)
These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCMCCM7 : CSGCMCCM7
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM0 : CSGCM0
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM1 : CSGCM1
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM2 : CSGCM2
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM3 : CSGCM3
bits : 0 - 31 (32 bit)
The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAIN : DATAIN
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM4 : CSGCM4
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM5 : CSGCM5
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM6 : CSGCM6
bits : 0 - 31 (32 bit)
Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSGCM7 : CSGCM7
bits : 0 - 31 (32 bit)
The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATAOUT : DATAOUT
bits : 0 - 31 (32 bit)
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