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DAC1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DAC_CR

DAC_DHR8R1

DAC_DHR12R2

DAC_DHR12L2

DAC_DHR8R2

DAC_DHR12RD

DAC_DHR12LD

DAC_DHR8RD

DAC_DOR1

DAC_DOR2

DAC_SR

DAC_CCR

DAC_MCR

DAC_HWCFGR0

DAC_VERR

DAC_IPIDR

DAC_SIDR

DAC_SWTRGR

DAC_SHSR1

DAC_SHSR2

DAC_SHHR

DAC_SHRR

DAC_DHR12R1

DAC_DHR12L1


DAC_CR

DAC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_CR DAC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN1 TEN1 TSEL10 TSEL11 TSEL12 TSEL13 WAVE1 MAMP1 DMAEN1 DMAUDRIE1 CEN1 HFSEL EN2 TEN2 TSEL20 TSEL21 TSEL22 TSEL23 WAVE2 MAMP2 DMAEN2 DMAUDRIE2 CEN2

EN1 : EN1
bits : 0 - 0 (1 bit)

TEN1 : TEN1
bits : 1 - 1 (1 bit)

TSEL10 : TSEL10
bits : 2 - 2 (1 bit)

TSEL11 : TSEL11
bits : 3 - 3 (1 bit)

TSEL12 : TSEL12
bits : 4 - 4 (1 bit)

TSEL13 : TSEL13
bits : 5 - 5 (1 bit)

WAVE1 : WAVE1
bits : 6 - 7 (2 bit)

MAMP1 : MAMP1
bits : 8 - 11 (4 bit)

DMAEN1 : DMAEN1
bits : 12 - 12 (1 bit)

DMAUDRIE1 : DMAUDRIE1
bits : 13 - 13 (1 bit)

CEN1 : CEN1
bits : 14 - 14 (1 bit)

HFSEL : HFSEL
bits : 15 - 15 (1 bit)

EN2 : EN2
bits : 16 - 16 (1 bit)

TEN2 : TEN2
bits : 17 - 17 (1 bit)

TSEL20 : TSEL20
bits : 18 - 18 (1 bit)

TSEL21 : TSEL21
bits : 19 - 19 (1 bit)

TSEL22 : TSEL22
bits : 20 - 20 (1 bit)

TSEL23 : TSEL23
bits : 21 - 21 (1 bit)

WAVE2 : WAVE2
bits : 22 - 23 (2 bit)

MAMP2 : MAMP2
bits : 24 - 27 (4 bit)

DMAEN2 : DMAEN2
bits : 28 - 28 (1 bit)

DMAUDRIE2 : DMAUDRIE2
bits : 29 - 29 (1 bit)

CEN2 : CEN2
bits : 30 - 30 (1 bit)


DAC_DHR8R1

DAC channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR8R1 DAC_DHR8R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DACC1DHR
bits : 0 - 7 (8 bit)


DAC_DHR12R2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12R2 DAC_DHR12R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR

DACC2DHR : DACC2DHR
bits : 0 - 11 (12 bit)


DAC_DHR12L2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12L2 DAC_DHR12L2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR

DACC2DHR : DACC2DHR
bits : 4 - 15 (12 bit)


DAC_DHR8R2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR8R2 DAC_DHR8R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR

DACC2DHR : DACC2DHR
bits : 0 - 7 (8 bit)


DAC_DHR12RD

Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12RD DAC_DHR12RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DACC1DHR
bits : 0 - 11 (12 bit)

DACC2DHR : DACC2DHR
bits : 16 - 27 (12 bit)


DAC_DHR12LD

Dual DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12LD DAC_DHR12LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DACC1DHR
bits : 4 - 15 (12 bit)

DACC2DHR : DACC2DHR
bits : 20 - 31 (12 bit)


DAC_DHR8RD

Dual DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR8RD DAC_DHR8RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DACC1DHR
bits : 0 - 7 (8 bit)

DACC2DHR : DACC2DHR
bits : 8 - 15 (8 bit)


DAC_DOR1

DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_DOR1 DAC_DOR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DOR

DACC1DOR : DACC1DOR
bits : 0 - 11 (12 bit)


DAC_DOR2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_DOR2 DAC_DOR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DOR

DACC2DOR : DACC2DOR
bits : 0 - 11 (12 bit)


DAC_SR

DAC status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SR DAC_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAUDR1 CAL_FLAG1 BWST1 DMAUDR2 CAL_FLAG2 BWST2

DMAUDR1 : DMAUDR1
bits : 13 - 13 (1 bit)
access : read-write

CAL_FLAG1 : CAL_FLAG1
bits : 14 - 14 (1 bit)
access : read-only

BWST1 : BWST1
bits : 15 - 15 (1 bit)
access : read-only

DMAUDR2 : DMAUDR2
bits : 29 - 29 (1 bit)
access : read-write

CAL_FLAG2 : CAL_FLAG2
bits : 30 - 30 (1 bit)
access : read-only

BWST2 : BWST2
bits : 31 - 31 (1 bit)
access : read-only


DAC_CCR

DAC calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_CCR DAC_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTRIM1 OTRIM2

OTRIM1 : OTRIM1
bits : 0 - 4 (5 bit)

OTRIM2 : OTRIM2
bits : 16 - 20 (5 bit)


DAC_MCR

DAC mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_MCR DAC_MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE1 MODE2

MODE1 : MODE1
bits : 0 - 2 (3 bit)

MODE2 : MODE2
bits : 16 - 18 (3 bit)


DAC_HWCFGR0

DAC IP hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_HWCFGR0 DAC_HWCFGR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUAL LFSR TRIANGLE SAMPLE OR_CFG

DUAL : DUAL
bits : 0 - 3 (4 bit)

LFSR : LFSR
bits : 4 - 7 (4 bit)

TRIANGLE : TRIANGLE
bits : 8 - 11 (4 bit)

SAMPLE : SAMPLE
bits : 12 - 15 (4 bit)

OR_CFG : OR_CFG
bits : 16 - 23 (8 bit)


DAC_VERR

No
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_VERR DAC_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


DAC_IPIDR

No
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_IPIDR DAC_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


DAC_SIDR

No
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_SIDR DAC_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


DAC_SWTRGR

DAC software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DAC_SWTRGR DAC_SWTRGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG1 SWTRIG2

SWTRIG1 : SWTRIG1
bits : 0 - 0 (1 bit)

SWTRIG2 : SWTRIG2
bits : 1 - 1 (1 bit)


DAC_SHSR1

DAC channel 1 sample and hold sample time register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHSR1 DAC_SHSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAMPLE1

TSAMPLE1 : TSAMPLE1
bits : 0 - 9 (10 bit)


DAC_SHSR2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHSR2 DAC_SHSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAMPLE2

TSAMPLE2 : TSAMPLE2
bits : 0 - 9 (10 bit)


DAC_SHHR

DAC sample and hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHHR DAC_SHHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THOLD1 THOLD2

THOLD1 : THOLD1
bits : 0 - 9 (10 bit)

THOLD2 : THOLD2
bits : 16 - 25 (10 bit)


DAC_SHRR

DAC sample and hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHRR DAC_SHRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TREFRESH1 TREFRESH2

TREFRESH1 : TREFRESH1
bits : 0 - 7 (8 bit)

TREFRESH2 : TREFRESH2
bits : 16 - 23 (8 bit)


DAC_DHR12R1

DAC channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12R1 DAC_DHR12R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DACC1DHR
bits : 0 - 11 (12 bit)


DAC_DHR12L1

DAC channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12L1 DAC_DHR12L1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DACC1DHR
bits : 4 - 15 (12 bit)



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