\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
DAC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN1 : EN1
bits : 0 - 0 (1 bit)
TEN1 : TEN1
bits : 1 - 1 (1 bit)
TSEL10 : TSEL10
bits : 2 - 2 (1 bit)
TSEL11 : TSEL11
bits : 3 - 3 (1 bit)
TSEL12 : TSEL12
bits : 4 - 4 (1 bit)
TSEL13 : TSEL13
bits : 5 - 5 (1 bit)
WAVE1 : WAVE1
bits : 6 - 7 (2 bit)
MAMP1 : MAMP1
bits : 8 - 11 (4 bit)
DMAEN1 : DMAEN1
bits : 12 - 12 (1 bit)
DMAUDRIE1 : DMAUDRIE1
bits : 13 - 13 (1 bit)
CEN1 : CEN1
bits : 14 - 14 (1 bit)
HFSEL : HFSEL
bits : 15 - 15 (1 bit)
EN2 : EN2
bits : 16 - 16 (1 bit)
TEN2 : TEN2
bits : 17 - 17 (1 bit)
TSEL20 : TSEL20
bits : 18 - 18 (1 bit)
TSEL21 : TSEL21
bits : 19 - 19 (1 bit)
TSEL22 : TSEL22
bits : 20 - 20 (1 bit)
TSEL23 : TSEL23
bits : 21 - 21 (1 bit)
WAVE2 : WAVE2
bits : 22 - 23 (2 bit)
MAMP2 : MAMP2
bits : 24 - 27 (4 bit)
DMAEN2 : DMAEN2
bits : 28 - 28 (1 bit)
DMAUDRIE2 : DMAUDRIE2
bits : 29 - 29 (1 bit)
CEN2 : CEN2
bits : 30 - 30 (1 bit)
DAC channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DACC1DHR
bits : 0 - 7 (8 bit)
This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DACC2DHR
bits : 0 - 11 (12 bit)
This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DACC2DHR
bits : 4 - 15 (12 bit)
This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC2DHR : DACC2DHR
bits : 0 - 7 (8 bit)
Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DACC1DHR
bits : 0 - 11 (12 bit)
DACC2DHR : DACC2DHR
bits : 16 - 27 (12 bit)
Dual DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DACC1DHR
bits : 4 - 15 (12 bit)
DACC2DHR : DACC2DHR
bits : 20 - 31 (12 bit)
Dual DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DACC1DHR
bits : 0 - 7 (8 bit)
DACC2DHR : DACC2DHR
bits : 8 - 15 (8 bit)
DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC1DOR : DACC1DOR
bits : 0 - 11 (12 bit)
This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DACC2DOR : DACC2DOR
bits : 0 - 11 (12 bit)
DAC status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAUDR1 : DMAUDR1
bits : 13 - 13 (1 bit)
access : read-write
CAL_FLAG1 : CAL_FLAG1
bits : 14 - 14 (1 bit)
access : read-only
BWST1 : BWST1
bits : 15 - 15 (1 bit)
access : read-only
DMAUDR2 : DMAUDR2
bits : 29 - 29 (1 bit)
access : read-write
CAL_FLAG2 : CAL_FLAG2
bits : 30 - 30 (1 bit)
access : read-only
BWST2 : BWST2
bits : 31 - 31 (1 bit)
access : read-only
DAC calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTRIM1 : OTRIM1
bits : 0 - 4 (5 bit)
OTRIM2 : OTRIM2
bits : 16 - 20 (5 bit)
DAC mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE1 : MODE1
bits : 0 - 2 (3 bit)
MODE2 : MODE2
bits : 16 - 18 (3 bit)
DAC IP hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUAL : DUAL
bits : 0 - 3 (4 bit)
LFSR : LFSR
bits : 4 - 7 (4 bit)
TRIANGLE : TRIANGLE
bits : 8 - 11 (4 bit)
SAMPLE : SAMPLE
bits : 12 - 15 (4 bit)
OR_CFG : OR_CFG
bits : 16 - 23 (8 bit)
No
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
No
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
No
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
DAC software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRIG1 : SWTRIG1
bits : 0 - 0 (1 bit)
SWTRIG2 : SWTRIG2
bits : 1 - 1 (1 bit)
DAC channel 1 sample and hold sample time register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE1 : TSAMPLE1
bits : 0 - 9 (10 bit)
This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAMPLE2 : TSAMPLE2
bits : 0 - 9 (10 bit)
DAC sample and hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THOLD1 : THOLD1
bits : 0 - 9 (10 bit)
THOLD2 : THOLD2
bits : 16 - 25 (10 bit)
DAC sample and hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TREFRESH1 : TREFRESH1
bits : 0 - 7 (8 bit)
TREFRESH2 : TREFRESH2
bits : 16 - 23 (8 bit)
DAC channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DACC1DHR
bits : 0 - 11 (12 bit)
DAC channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACC1DHR : DACC1DHR
bits : 4 - 15 (12 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.