\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
DDRCTRL_DFIPHYMSTR (DFIPHYMSTR)
DDRCTRL_POISONSTAT (POISONSTAT)
DDRCTRL_PCFGQOS0_0 (PCFGQOS0_0)
DDRCTRL_PCFGQOS1_0 (PCFGQOS1_0)
DDRCTRL_PCFGWQOS0_0 (PCFGWQOS0_0)
DDRCTRL_PCFGWQOS1_0 (PCFGWQOS1_0)
DDRCTRL_PCFGQOS0_1 (PCFGQOS0_1)
DDRCTRL_PCFGQOS1_1 (PCFGQOS1_1)
DDRCTRL_PCFGWQOS0_1 (PCFGWQOS0_1)
DDRCTRL_PCFGWQOS1_1 (PCFGWQOS1_1)
DDRCTRL_CRCPARCTL0 (CRCPARCTL0)
DDRCTRL_CRCPARSTAT (CRCPARSTAT)
DDRCTRL master register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDR3 : DDR3
bits : 0 - 0 (1 bit)
LPDDR2 : LPDDR2
bits : 2 - 2 (1 bit)
LPDDR3 : LPDDR3
bits : 3 - 3 (1 bit)
BURSTCHOP : BURSTCHOP
bits : 9 - 9 (1 bit)
EN_2T_TIMING_MODE : EN_2T_TIMING_MODE
bits : 10 - 10 (1 bit)
DATA_BUS_WIDTH : DATA_BUS_WIDTH
bits : 12 - 13 (2 bit)
DLL_OFF_MODE : DLL_OFF_MODE
bits : 15 - 15 (1 bit)
BURST_RDWR : BURST_RDWR
bits : 16 - 19 (4 bit)
Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR_TYPE : MR_TYPE
bits : 0 - 0 (1 bit)
MR_RANK : MR_RANK
bits : 4 - 4 (1 bit)
MR_ADDR : MR_ADDR
bits : 12 - 15 (4 bit)
MR_WR : MR_WR
bits : 31 - 31 (1 bit)
DDRCTRL SDRAM timing register 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_RAS_MIN : T_RAS_MIN
bits : 0 - 5 (6 bit)
T_RAS_MAX : T_RAS_MAX
bits : 8 - 14 (7 bit)
T_FAW : T_FAW
bits : 16 - 21 (6 bit)
WR2PRE : WR2PRE
bits : 24 - 30 (7 bit)
DDRCTRL SDRAM timing register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_RC : T_RC
bits : 0 - 6 (7 bit)
RD2PRE : RD2PRE
bits : 8 - 13 (6 bit)
T_XP : T_XP
bits : 16 - 20 (5 bit)
DDRCTRL SDRAM timing register 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR2RD : WR2RD
bits : 0 - 5 (6 bit)
RD2WR : RD2WR
bits : 8 - 13 (6 bit)
READ_LATENCY : READ_LATENCY
bits : 16 - 21 (6 bit)
WRITE_LATENCY : WRITE_LATENCY
bits : 24 - 29 (6 bit)
DDRCTRL SDRAM timing register 3
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_MOD : T_MOD
bits : 0 - 9 (10 bit)
T_MRD : T_MRD
bits : 12 - 17 (6 bit)
T_MRW : T_MRW
bits : 20 - 29 (10 bit)
DDRCTRL SDRAM timing register 4
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_RP : T_RP
bits : 0 - 4 (5 bit)
T_RRD : T_RRD
bits : 8 - 11 (4 bit)
T_CCD : T_CCD
bits : 16 - 19 (4 bit)
T_RCD : T_RCD
bits : 24 - 28 (5 bit)
DDRCTRL SDRAM timing register 5
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_CKE : T_CKE
bits : 0 - 4 (5 bit)
T_CKESR : T_CKESR
bits : 8 - 13 (6 bit)
T_CKSRE : T_CKSRE
bits : 16 - 19 (4 bit)
T_CKSRX : T_CKSRX
bits : 24 - 27 (4 bit)
DDRCTRL SDRAM timing register 6
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_CKCSX : T_CKCSX
bits : 0 - 3 (4 bit)
T_CKDPDX : T_CKDPDX
bits : 16 - 19 (4 bit)
T_CKDPDE : T_CKDPDE
bits : 24 - 27 (4 bit)
DDRCTRL SDRAM timing register 7
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_CKPDX : T_CKPDX
bits : 0 - 3 (4 bit)
T_CKPDE : T_CKPDE
bits : 8 - 11 (4 bit)
DDRCTRL SDRAM timing register 8
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_XS_X32 : T_XS_X32
bits : 0 - 6 (7 bit)
T_XS_DLL_X32 : T_XS_DLL_X32
bits : 8 - 14 (7 bit)
DDRCTRL SDRAM timing register 14
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_XSR : T_XSR
bits : 0 - 11 (12 bit)
DDRCTRL SDRAM timing register 15
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_STAB_X32 : T_STAB_X32
bits : 0 - 7 (8 bit)
EN_DFI_LP_T_STAB : EN_DFI_LP_T_STAB
bits : 31 - 31 (1 bit)
DDRCTRL mode register read/write control register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR_DATA : MR_DATA
bits : 0 - 15 (16 bit)
DDRCTRL mode register read/write status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MR_WR_BUSY : MR_WR_BUSY
bits : 0 - 0 (1 bit)
DDRCTRL ZQ control register 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_ZQ_SHORT_NOP : T_ZQ_SHORT_NOP
bits : 0 - 9 (10 bit)
T_ZQ_LONG_NOP : T_ZQ_LONG_NOP
bits : 16 - 26 (11 bit)
ZQ_RESISTOR_SHARED : ZQ_RESISTOR_SHARED
bits : 29 - 29 (1 bit)
DIS_SRX_ZQCL : DIS_SRX_ZQCL
bits : 30 - 30 (1 bit)
DIS_AUTO_ZQ : DIS_AUTO_ZQ
bits : 31 - 31 (1 bit)
DDRCTRL ZQ control register 1
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_ZQ_SHORT_INTERVAL_X1024 : T_ZQ_SHORT_INTERVAL_X1024
bits : 0 - 19 (20 bit)
T_ZQ_RESET_NOP : T_ZQ_RESET_NOP
bits : 20 - 29 (10 bit)
DDRCTRL ZQ control register 2
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_RESET : ZQ_RESET
bits : 0 - 0 (1 bit)
DDRCTRL ZQ status register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ZQ_RESET_BUSY : ZQ_RESET_BUSY
bits : 0 - 0 (1 bit)
DDRCTRL DFI timing register 0
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_TPHY_WRLAT : DFI_TPHY_WRLAT
bits : 0 - 5 (6 bit)
DFI_TPHY_WRDATA : DFI_TPHY_WRDATA
bits : 8 - 13 (6 bit)
DFI_T_RDDATA_EN : DFI_T_RDDATA_EN
bits : 16 - 22 (7 bit)
DFI_T_CTRL_DELAY : DFI_T_CTRL_DELAY
bits : 24 - 28 (5 bit)
DDRCTRL DFI timing register 1
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_T_DRAM_CLK_ENABLE : DFI_T_DRAM_CLK_ENABLE
bits : 0 - 4 (5 bit)
DFI_T_DRAM_CLK_DISABLE : DFI_T_DRAM_CLK_DISABLE
bits : 8 - 12 (5 bit)
DFI_T_WRDATA_DELAY : DFI_T_WRDATA_DELAY
bits : 16 - 20 (5 bit)
DDRCTRL low power configuration register 0
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_LP_EN_PD : DFI_LP_EN_PD
bits : 0 - 0 (1 bit)
DFI_LP_WAKEUP_PD : DFI_LP_WAKEUP_PD
bits : 4 - 7 (4 bit)
DFI_LP_EN_SR : DFI_LP_EN_SR
bits : 8 - 8 (1 bit)
DFI_LP_WAKEUP_SR : DFI_LP_WAKEUP_SR
bits : 12 - 15 (4 bit)
DFI_LP_EN_DPD : DFI_LP_EN_DPD
bits : 16 - 16 (1 bit)
DFI_LP_WAKEUP_DPD : DFI_LP_WAKEUP_DPD
bits : 20 - 23 (4 bit)
DFI_TLP_RESP : DFI_TLP_RESP
bits : 24 - 28 (5 bit)
DDRCTRL DFI update register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_T_CTRLUP_MIN : DFI_T_CTRLUP_MIN
bits : 0 - 9 (10 bit)
DFI_T_CTRLUP_MAX : DFI_T_CTRLUP_MAX
bits : 16 - 25 (10 bit)
CTRLUPD_PRE_SRX : CTRLUPD_PRE_SRX
bits : 29 - 29 (1 bit)
DIS_AUTO_CTRLUPD_SRX : DIS_AUTO_CTRLUPD_SRX
bits : 30 - 30 (1 bit)
DIS_AUTO_CTRLUPD : DIS_AUTO_CTRLUPD
bits : 31 - 31 (1 bit)
DDRCTRL DFI update register 1
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_T_CTRLUPD_INTERVAL_MAX_X1024 : DFI_T_CTRLUPD_INTERVAL_MAX_X1024
bits : 0 - 7 (8 bit)
DFI_T_CTRLUPD_INTERVAL_MIN_X1024 : DFI_T_CTRLUPD_INTERVAL_MIN_X1024
bits : 16 - 23 (8 bit)
DDRCTRL DFI update register 2
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_PHYUPD_EN : DFI_PHYUPD_EN
bits : 31 - 31 (1 bit)
DDRCTRL DFI miscellaneous control register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_INIT_COMPLETE_EN : DFI_INIT_COMPLETE_EN
bits : 0 - 0 (1 bit)
CTL_IDLE_EN : CTL_IDLE_EN
bits : 4 - 4 (1 bit)
DFI_INIT_START : DFI_INIT_START
bits : 5 - 5 (1 bit)
DFI_FREQUENCY : DFI_FREQUENCY
bits : 8 - 12 (5 bit)
DDRCTRL DFI status register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFI_INIT_COMPLETE : DFI_INIT_COMPLETE
bits : 0 - 0 (1 bit)
DFI_LP_ACK : DFI_LP_ACK
bits : 1 - 1 (1 bit)
DDRCTRL DFI PHY master register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_PHYMSTR_EN : DFI_PHYMSTR_EN
bits : 0 - 0 (1 bit)
DDRCTRL temperature derate enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DERATE_ENABLE : DERATE_ENABLE
bits : 0 - 0 (1 bit)
DERATE_VALUE : DERATE_VALUE
bits : 1 - 2 (2 bit)
DERATE_BYTE : DERATE_BYTE
bits : 4 - 7 (4 bit)
DDRCTRL address map register 1
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_BANK_B0 : ADDRMAP_BANK_B0
bits : 0 - 5 (6 bit)
ADDRMAP_BANK_B1 : ADDRMAP_BANK_B1
bits : 8 - 13 (6 bit)
ADDRMAP_BANK_B2 : ADDRMAP_BANK_B2
bits : 16 - 21 (6 bit)
DDRCTRL address map register 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_COL_B2 : ADDRMAP_COL_B2
bits : 0 - 3 (4 bit)
ADDRMAP_COL_B3 : ADDRMAP_COL_B3
bits : 8 - 11 (4 bit)
ADDRMAP_COL_B4 : ADDRMAP_COL_B4
bits : 16 - 19 (4 bit)
ADDRMAP_COL_B5 : ADDRMAP_COL_B5
bits : 24 - 27 (4 bit)
DDRCTRL address map register 3
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_COL_B6 : ADDRMAP_COL_B6
bits : 0 - 3 (4 bit)
ADDRMAP_COL_B7 : ADDRMAP_COL_B7
bits : 8 - 12 (5 bit)
ADDRMAP_COL_B8 : ADDRMAP_COL_B8
bits : 16 - 20 (5 bit)
ADDRMAP_COL_B9 : ADDRMAP_COL_B9
bits : 24 - 28 (5 bit)
DDRCTRL address map register 4
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_COL_B10 : ADDRMAP_COL_B10
bits : 0 - 4 (5 bit)
ADDRMAP_COL_B11 : ADDRMAP_COL_B11
bits : 8 - 12 (5 bit)
DDRCTRL address map register 5
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_ROW_B0 : ADDRMAP_ROW_B0
bits : 0 - 3 (4 bit)
ADDRMAP_ROW_B1 : ADDRMAP_ROW_B1
bits : 8 - 11 (4 bit)
ADDRMAP_ROW_B2_10 : ADDRMAP_ROW_B2_10
bits : 16 - 19 (4 bit)
ADDRMAP_ROW_B11 : ADDRMAP_ROW_B11
bits : 24 - 27 (4 bit)
DDRCTRL address register 6
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_ROW_B12 : ADDRMAP_ROW_B12
bits : 0 - 3 (4 bit)
ADDRMAP_ROW_B13 : ADDRMAP_ROW_B13
bits : 8 - 11 (4 bit)
ADDRMAP_ROW_B14 : ADDRMAP_ROW_B14
bits : 16 - 19 (4 bit)
ADDRMAP_ROW_B15 : ADDRMAP_ROW_B15
bits : 24 - 27 (4 bit)
LPDDR3_6GB_12GB : LPDDR3_6GB_12GB
bits : 31 - 31 (1 bit)
DDRCTRL address map register 9
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_ROW_B2 : ADDRMAP_ROW_B2
bits : 0 - 3 (4 bit)
ADDRMAP_ROW_B3 : ADDRMAP_ROW_B3
bits : 8 - 11 (4 bit)
ADDRMAP_ROW_B4 : ADDRMAP_ROW_B4
bits : 16 - 19 (4 bit)
ADDRMAP_ROW_B5 : ADDRMAP_ROW_B5
bits : 24 - 27 (4 bit)
DDRCTRL address map register 10
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_ROW_B6 : ADDRMAP_ROW_B6
bits : 0 - 3 (4 bit)
ADDRMAP_ROW_B7 : ADDRMAP_ROW_B7
bits : 8 - 11 (4 bit)
ADDRMAP_ROW_B8 : ADDRMAP_ROW_B8
bits : 16 - 19 (4 bit)
ADDRMAP_ROW_B9 : ADDRMAP_ROW_B9
bits : 24 - 27 (4 bit)
DDRCTRL address map register 11
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMAP_ROW_B10 : ADDRMAP_ROW_B10
bits : 0 - 3 (4 bit)
DDRCTRL temperature derate interval register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR4_READ_INTERVAL : MR4_READ_INTERVAL
bits : 0 - 31 (32 bit)
DDRCTRL ODT configuration register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_ODT_DELAY : RD_ODT_DELAY
bits : 2 - 6 (5 bit)
RD_ODT_HOLD : RD_ODT_HOLD
bits : 8 - 11 (4 bit)
WR_ODT_DELAY : WR_ODT_DELAY
bits : 16 - 20 (5 bit)
WR_ODT_HOLD : WR_ODT_HOLD
bits : 24 - 27 (4 bit)
DDRCTRL ODT/Rank map register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANK0_WR_ODT : RANK0_WR_ODT
bits : 0 - 0 (1 bit)
RANK0_RD_ODT : RANK0_RD_ODT
bits : 4 - 4 (1 bit)
DDRCTRL scheduler control register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCE_LOW_PRI_N : FORCE_LOW_PRI_N
bits : 0 - 0 (1 bit)
PREFER_WRITE : PREFER_WRITE
bits : 1 - 1 (1 bit)
PAGECLOSE : PAGECLOSE
bits : 2 - 2 (1 bit)
LPR_NUM_ENTRIES : LPR_NUM_ENTRIES
bits : 8 - 11 (4 bit)
GO2CRITICAL_HYSTERESIS : GO2CRITICAL_HYSTERESIS
bits : 16 - 23 (8 bit)
RDWR_IDLE_GAP : RDWR_IDLE_GAP
bits : 24 - 30 (7 bit)
DDRCTRL scheduler control register 1
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAGECLOSE_TIMER : PAGECLOSE_TIMER
bits : 0 - 7 (8 bit)
DDRCTRL high priority read CAM register 1
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPR_MAX_STARVE : HPR_MAX_STARVE
bits : 0 - 15 (16 bit)
HPR_XACT_RUN_LENGTH : HPR_XACT_RUN_LENGTH
bits : 24 - 31 (8 bit)
DDRCTRL low priority read CAM register 1
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPR_MAX_STARVE : LPR_MAX_STARVE
bits : 0 - 15 (16 bit)
LPR_XACT_RUN_LENGTH : LPR_XACT_RUN_LENGTH
bits : 24 - 31 (8 bit)
DDRCTRL write CAM register 1
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
W_MAX_STARVE : W_MAX_STARVE
bits : 0 - 15 (16 bit)
W_XACT_RUN_LENGTH : W_XACT_RUN_LENGTH
bits : 24 - 31 (8 bit)
DDRCTRL low power control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELFREF_EN : SELFREF_EN
bits : 0 - 0 (1 bit)
POWERDOWN_EN : POWERDOWN_EN
bits : 1 - 1 (1 bit)
DEEPPOWERDOWN_EN : DEEPPOWERDOWN_EN
bits : 2 - 2 (1 bit)
EN_DFI_DRAM_CLK_DISABLE : EN_DFI_DRAM_CLK_DISABLE
bits : 3 - 3 (1 bit)
SELFREF_SW : SELFREF_SW
bits : 5 - 5 (1 bit)
DIS_CAM_DRAIN_SELFREF : DIS_CAM_DRAIN_SELFREF
bits : 7 - 7 (1 bit)
DDRCTRL debug register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS_WC : DIS_WC
bits : 0 - 0 (1 bit)
DIS_COLLISION_PAGE_OPT : DIS_COLLISION_PAGE_OPT
bits : 4 - 4 (1 bit)
DDRCTRL debug register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS_DQ : DIS_DQ
bits : 0 - 0 (1 bit)
DIS_HIF : DIS_HIF
bits : 1 - 1 (1 bit)
DDRCTRL CAM debug register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DBG_HPR_Q_DEPTH : DBG_HPR_Q_DEPTH
bits : 0 - 4 (5 bit)
DBG_LPR_Q_DEPTH : DBG_LPR_Q_DEPTH
bits : 8 - 12 (5 bit)
DBG_W_Q_DEPTH : DBG_W_Q_DEPTH
bits : 16 - 20 (5 bit)
DBG_STALL : DBG_STALL
bits : 24 - 24 (1 bit)
DBG_RD_Q_EMPTY : DBG_RD_Q_EMPTY
bits : 25 - 25 (1 bit)
DBG_WR_Q_EMPTY : DBG_WR_Q_EMPTY
bits : 26 - 26 (1 bit)
RD_DATA_PIPELINE_EMPTY : RD_DATA_PIPELINE_EMPTY
bits : 28 - 28 (1 bit)
WR_DATA_PIPELINE_EMPTY : WR_DATA_PIPELINE_EMPTY
bits : 29 - 29 (1 bit)
DDRCTRL command debug register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANK0_REFRESH : RANK0_REFRESH
bits : 0 - 0 (1 bit)
ZQ_CALIB_SHORT : ZQ_CALIB_SHORT
bits : 4 - 4 (1 bit)
CTRLUPD : CTRLUPD
bits : 5 - 5 (1 bit)
DDRCTRL status debug register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RANK0_REFRESH_BUSY : RANK0_REFRESH_BUSY
bits : 0 - 0 (1 bit)
ZQ_CALIB_SHORT_BUSY : ZQ_CALIB_SHORT_BUSY
bits : 4 - 4 (1 bit)
CTRLUPD_BUSY : CTRLUPD_BUSY
bits : 5 - 5 (1 bit)
DDRCTRL software register programming control enable
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_DONE : SW_DONE
bits : 0 - 0 (1 bit)
DDRCTRL software register programming control status
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SW_DONE_ACK : SW_DONE_ACK
bits : 0 - 0 (1 bit)
DDRCTRL low power timing register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWERDOWN_TO_X32 : POWERDOWN_TO_X32
bits : 0 - 4 (5 bit)
T_DPD_X4096 : T_DPD_X4096
bits : 8 - 15 (8 bit)
SELFREF_TO_X32 : SELFREF_TO_X32
bits : 16 - 23 (8 bit)
AXI Poison configuration register common for all AXI ports.
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_POISON_SLVERR_EN : WR_POISON_SLVERR_EN
bits : 0 - 0 (1 bit)
WR_POISON_INTR_EN : WR_POISON_INTR_EN
bits : 4 - 4 (1 bit)
WR_POISON_INTR_CLR : WR_POISON_INTR_CLR
bits : 8 - 8 (1 bit)
RD_POISON_SLVERR_EN : RD_POISON_SLVERR_EN
bits : 16 - 16 (1 bit)
RD_POISON_INTR_EN : RD_POISON_INTR_EN
bits : 20 - 20 (1 bit)
RD_POISON_INTR_CLR : RD_POISON_INTR_CLR
bits : 24 - 24 (1 bit)
DDRCTRL AXI Poison status register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_POISON_INTR_0 : WR_POISON_INTR_0
bits : 0 - 0 (1 bit)
WR_POISON_INTR_1 : WR_POISON_INTR_1
bits : 1 - 1 (1 bit)
RD_POISON_INTR_0 : RD_POISON_INTR_0
bits : 16 - 16 (1 bit)
RD_POISON_INTR_1 : RD_POISON_INTR_1
bits : 17 - 17 (1 bit)
DDRCTRL hardware low power control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_LP_EN : HW_LP_EN
bits : 0 - 0 (1 bit)
HW_LP_EXIT_IDLE_EN : HW_LP_EXIT_IDLE_EN
bits : 1 - 1 (1 bit)
HW_LP_IDLE_X32 : HW_LP_IDLE_X32
bits : 16 - 27 (12 bit)
DDRCTRL port status register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_PORT_BUSY_0 : RD_PORT_BUSY_0
bits : 0 - 0 (1 bit)
RD_PORT_BUSY_1 : RD_PORT_BUSY_1
bits : 1 - 1 (1 bit)
WR_PORT_BUSY_0 : WR_PORT_BUSY_0
bits : 16 - 16 (1 bit)
WR_PORT_BUSY_1 : WR_PORT_BUSY_1
bits : 17 - 17 (1 bit)
DDRCTRL operating mode status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OPERATING_MODE : OPERATING_MODE
bits : 0 - 2 (3 bit)
SELFREF_TYPE : SELFREF_TYPE
bits : 4 - 5 (2 bit)
SELFREF_CAM_NOT_EMPTY : SELFREF_CAM_NOT_EMPTY
bits : 12 - 12 (1 bit)
DDRCTRL port common configuration register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO2CRITICAL_EN : GO2CRITICAL_EN
bits : 0 - 0 (1 bit)
PAGEMATCH_LIMIT : PAGEMATCH_LIMIT
bits : 4 - 4 (1 bit)
BL_EXP_MODE : BL_EXP_MODE
bits : 8 - 8 (1 bit)
DDRCTRL port 0 configuration read register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_PORT_PRIORITY : RD_PORT_PRIORITY
bits : 0 - 9 (10 bit)
RD_PORT_AGING_EN : RD_PORT_AGING_EN
bits : 12 - 12 (1 bit)
RD_PORT_URGENT_EN : RD_PORT_URGENT_EN
bits : 13 - 13 (1 bit)
RD_PORT_PAGEMATCH_EN : RD_PORT_PAGEMATCH_EN
bits : 14 - 14 (1 bit)
RDWR_ORDERED_EN : RDWR_ORDERED_EN
bits : 16 - 16 (1 bit)
DDRCTRL port 0 configuration write register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_PORT_PRIORITY : WR_PORT_PRIORITY
bits : 0 - 9 (10 bit)
WR_PORT_AGING_EN : WR_PORT_AGING_EN
bits : 12 - 12 (1 bit)
WR_PORT_URGENT_EN : WR_PORT_URGENT_EN
bits : 13 - 13 (1 bit)
WR_PORT_PAGEMATCH_EN : WR_PORT_PAGEMATCH_EN
bits : 14 - 14 (1 bit)
DDRCTRL port 0 control register
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_EN : PORT_EN
bits : 0 - 0 (1 bit)
DDRCTRL port 0 read Q0S configuration register 0
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQOS_MAP_LEVEL1 : RQOS_MAP_LEVEL1
bits : 0 - 3 (4 bit)
RQOS_MAP_LEVEL2 : RQOS_MAP_LEVEL2
bits : 8 - 11 (4 bit)
RQOS_MAP_REGION0 : RQOS_MAP_REGION0
bits : 16 - 17 (2 bit)
RQOS_MAP_REGION1 : RQOS_MAP_REGION1
bits : 20 - 21 (2 bit)
RQOS_MAP_REGION2 : RQOS_MAP_REGION2
bits : 24 - 25 (2 bit)
DDRCTRL port 0 read Q0S configuration register 1
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQOS_MAP_TIMEOUTB : RQOS_MAP_TIMEOUTB
bits : 0 - 10 (11 bit)
RQOS_MAP_TIMEOUTR : RQOS_MAP_TIMEOUTR
bits : 16 - 26 (11 bit)
DDRCTRL port 0 write Q0S configuration register 0
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS_MAP_LEVEL1 : WQOS_MAP_LEVEL1
bits : 0 - 3 (4 bit)
WQOS_MAP_LEVEL2 : WQOS_MAP_LEVEL2
bits : 8 - 11 (4 bit)
WQOS_MAP_REGION0 : WQOS_MAP_REGION0
bits : 16 - 17 (2 bit)
WQOS_MAP_REGION1 : WQOS_MAP_REGION1
bits : 20 - 21 (2 bit)
WQOS_MAP_REGION2 : WQOS_MAP_REGION2
bits : 24 - 25 (2 bit)
DDRCTRL port 0 write Q0S configuration register 1
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS_MAP_TIMEOUT1 : WQOS_MAP_TIMEOUT1
bits : 0 - 10 (11 bit)
WQOS_MAP_TIMEOUT2 : WQOS_MAP_TIMEOUT2
bits : 16 - 26 (11 bit)
DDRCTRL port 1 configuration read register
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_PORT_PRIORITY : RD_PORT_PRIORITY
bits : 0 - 9 (10 bit)
RD_PORT_AGING_EN : RD_PORT_AGING_EN
bits : 12 - 12 (1 bit)
RD_PORT_URGENT_EN : RD_PORT_URGENT_EN
bits : 13 - 13 (1 bit)
RD_PORT_PAGEMATCH_EN : RD_PORT_PAGEMATCH_EN
bits : 14 - 14 (1 bit)
RDWR_ORDERED_EN : RDWR_ORDERED_EN
bits : 16 - 16 (1 bit)
DDRCTRL port 1 configuration write register
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_PORT_PRIORITY : WR_PORT_PRIORITY
bits : 0 - 9 (10 bit)
WR_PORT_AGING_EN : WR_PORT_AGING_EN
bits : 12 - 12 (1 bit)
WR_PORT_URGENT_EN : WR_PORT_URGENT_EN
bits : 13 - 13 (1 bit)
WR_PORT_PAGEMATCH_EN : WR_PORT_PAGEMATCH_EN
bits : 14 - 14 (1 bit)
DDRCTRL refresh control register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER_BANK_REFRESH : PER_BANK_REFRESH
bits : 2 - 2 (1 bit)
REFRESH_BURST : REFRESH_BURST
bits : 4 - 8 (5 bit)
REFRESH_TO_X32 : REFRESH_TO_X32
bits : 12 - 16 (5 bit)
REFRESH_MARGIN : REFRESH_MARGIN
bits : 20 - 23 (4 bit)
DDRCTRL port 1 control register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORT_EN : PORT_EN
bits : 0 - 0 (1 bit)
DDRCTRL port 1 read Q0S configuration register 0
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQOS_MAP_LEVEL1 : RQOS_MAP_LEVEL1
bits : 0 - 3 (4 bit)
RQOS_MAP_LEVEL2 : RQOS_MAP_LEVEL2
bits : 8 - 11 (4 bit)
RQOS_MAP_REGION0 : RQOS_MAP_REGION0
bits : 16 - 17 (2 bit)
RQOS_MAP_REGION1 : RQOS_MAP_REGION1
bits : 20 - 21 (2 bit)
RQOS_MAP_REGION2 : RQOS_MAP_REGION2
bits : 24 - 25 (2 bit)
DDRCTRL port 1 read Q0S configuration register 1
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RQOS_MAP_TIMEOUTB : RQOS_MAP_TIMEOUTB
bits : 0 - 10 (11 bit)
RQOS_MAP_TIMEOUTR : RQOS_MAP_TIMEOUTR
bits : 16 - 26 (11 bit)
DDRCTRL port 1 write Q0S configuration register 0
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS_MAP_LEVEL1 : WQOS_MAP_LEVEL1
bits : 0 - 3 (4 bit)
WQOS_MAP_LEVEL2 : WQOS_MAP_LEVEL2
bits : 8 - 11 (4 bit)
WQOS_MAP_REGION0 : WQOS_MAP_REGION0
bits : 16 - 17 (2 bit)
WQOS_MAP_REGION1 : WQOS_MAP_REGION1
bits : 20 - 21 (2 bit)
WQOS_MAP_REGION2 : WQOS_MAP_REGION2
bits : 24 - 25 (2 bit)
DDRCTRL port 1 write Q0S configuration register 1
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WQOS_MAP_TIMEOUT1 : WQOS_MAP_TIMEOUT1
bits : 0 - 10 (11 bit)
WQOS_MAP_TIMEOUT2 : WQOS_MAP_TIMEOUT2
bits : 16 - 26 (11 bit)
DDRCTRL refresh control register 3
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS_AUTO_REFRESH : DIS_AUTO_REFRESH
bits : 0 - 0 (1 bit)
REFRESH_UPDATE_LEVEL : REFRESH_UPDATE_LEVEL
bits : 1 - 1 (1 bit)
DDRCTRL refresh timing register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T_RFC_MIN : T_RFC_MIN
bits : 0 - 9 (10 bit)
LPDDR3_TREFBW_EN : LPDDR3_TREFBW_EN
bits : 15 - 15 (1 bit)
T_RFC_NOM_X1_X32 : T_RFC_NOM_X1_X32
bits : 16 - 27 (12 bit)
T_RFC_NOM_X1_SEL : T_RFC_NOM_X1_SEL
bits : 31 - 31 (1 bit)
DDRCTRL CRC parity control register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFI_ALERT_ERR_INT_EN : DFI_ALERT_ERR_INT_EN
bits : 0 - 0 (1 bit)
DFI_ALERT_ERR_INT_CLR : DFI_ALERT_ERR_INT_CLR
bits : 1 - 1 (1 bit)
DFI_ALERT_ERR_CNT_CLR : DFI_ALERT_ERR_CNT_CLR
bits : 2 - 2 (1 bit)
DDRCTRL CRC parity status register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFI_ALERT_ERR_CNT : DFI_ALERT_ERR_CNT
bits : 0 - 15 (16 bit)
DFI_ALERT_ERR_INT : DFI_ALERT_ERR_INT
bits : 16 - 16 (1 bit)
DDRCTRL SDRAM initialization register 0
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE_CKE_X1024 : PRE_CKE_X1024
bits : 0 - 11 (12 bit)
POST_CKE_X1024 : POST_CKE_X1024
bits : 16 - 25 (10 bit)
SKIP_DRAM_INIT : SKIP_DRAM_INIT
bits : 30 - 31 (2 bit)
DDRCTRL SDRAM initialization register 1
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE_OCD_X32 : PRE_OCD_X32
bits : 0 - 3 (4 bit)
DRAM_RSTN_X1024 : DRAM_RSTN_X1024
bits : 16 - 24 (9 bit)
DDRCTRL SDRAM initialization register 2
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIN_STABLE_CLOCK_X1 : MIN_STABLE_CLOCK_X1
bits : 0 - 3 (4 bit)
IDLE_AFTER_RESET_X32 : IDLE_AFTER_RESET_X32
bits : 8 - 15 (8 bit)
DDRCTRL SDRAM initialization register 3
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMR : EMR
bits : 0 - 15 (16 bit)
MR : MR
bits : 16 - 31 (16 bit)
DDRCTRL SDRAM initialization register 4
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMR3 : EMR3
bits : 0 - 15 (16 bit)
EMR2 : EMR2
bits : 16 - 31 (16 bit)
DDRCTRL SDRAM initialization register 5
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAX_AUTO_INIT_X1024 : MAX_AUTO_INIT_X1024
bits : 0 - 9 (10 bit)
DEV_ZQINIT_X32 : DEV_ZQINIT_X32
bits : 16 - 23 (8 bit)
DDRCTRL DIMM control register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIMM_STAGGER_CS_EN : DIMM_STAGGER_CS_EN
bits : 0 - 0 (1 bit)
DIMM_ADDR_MIRR_EN : DIMM_ADDR_MIRR_EN
bits : 1 - 1 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.