\n
address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection :
This register specifies the parameters used by channel y.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM filter 0 control register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFEN
bits : 0 - 0 (1 bit)
JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
JSYNC : JSYNC
bits : 3 - 3 (1 bit)
JSCAN : JSCAN
bits : 4 - 4 (1 bit)
JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)
JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
RCONT : RCONT
bits : 18 - 18 (1 bit)
RSYNC : RSYNC
bits : 19 - 19 (1 bit)
RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
RCH : RCH
bits : 24 - 26 (3 bit)
FAST : FAST
bits : 29 - 29 (1 bit)
AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
DFSDM filter 0 control register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
REOCIE : REOCIE
bits : 1 - 1 (1 bit)
JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
SCDIE : SCDIE
bits : 5 - 5 (1 bit)
CKABIE : CKABIE
bits : 6 - 6 (1 bit)
EXCH : EXCH
bits : 8 - 15 (8 bit)
AWDCH : AWDCH
bits : 16 - 23 (8 bit)
DFSDM filter 0 interrupt and status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : JEOCF
bits : 0 - 0 (1 bit)
REOCF : REOCF
bits : 1 - 1 (1 bit)
JOVRF : JOVRF
bits : 2 - 2 (1 bit)
ROVRF : ROVRF
bits : 3 - 3 (1 bit)
AWDF : AWDF
bits : 4 - 4 (1 bit)
JCIP : JCIP
bits : 13 - 13 (1 bit)
RCIP : RCIP
bits : 14 - 14 (1 bit)
CKABF : CKABF
bits : 16 - 23 (8 bit)
SCDF : SCDF
bits : 24 - 31 (8 bit)
DFSDM filter 0 interrupt flag clear register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
DFSDM filter 0 injected channel group selection register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : JCHG
bits : 0 - 7 (8 bit)
DFSDM filter 0 control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : IOSR
bits : 0 - 7 (8 bit)
FOSR : FOSR
bits : 16 - 25 (10 bit)
FORD : FORD
bits : 29 - 31 (3 bit)
DFSDM filter 0 data register for injected group
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : JDATACH
bits : 0 - 2 (3 bit)
JDATA : JDATA
bits : 8 - 31 (24 bit)
DFSDM filter 0 data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : RDATACH
bits : 0 - 2 (3 bit)
RPEND : RPEND
bits : 4 - 4 (1 bit)
RDATA : RDATA
bits : 8 - 31 (24 bit)
DFSDM filter 0 analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : BKAWH
bits : 0 - 3 (4 bit)
AWHT : AWHT
bits : 8 - 31 (24 bit)
DFSDM filter 0 analog watchdog low threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : BKAWL
bits : 0 - 3 (4 bit)
AWLT : AWLT
bits : 8 - 31 (24 bit)
DFSDM filter 0 analog watchdog status register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : AWLTF
bits : 0 - 7 (8 bit)
AWHTF : AWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 0 analog watchdog clear flag register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 0 extremes detector maximum register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
EXMAX : EXMAX
bits : 8 - 31 (24 bit)
DFSDM filter 0 extremes detector minimum register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write
DFSDM filter 0 conversion timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
DFSDM channel 0 delay register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM filter 1 control register 1
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFEN
bits : 0 - 0 (1 bit)
JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
JSYNC : JSYNC
bits : 3 - 3 (1 bit)
JSCAN : JSCAN
bits : 4 - 4 (1 bit)
JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)
JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
RCONT : RCONT
bits : 18 - 18 (1 bit)
RSYNC : RSYNC
bits : 19 - 19 (1 bit)
RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
RCH : RCH
bits : 24 - 26 (3 bit)
FAST : FAST
bits : 29 - 29 (1 bit)
AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
DFSDM filter 1 control register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
REOCIE : REOCIE
bits : 1 - 1 (1 bit)
JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
SCDIE : SCDIE
bits : 5 - 5 (1 bit)
CKABIE : CKABIE
bits : 6 - 6 (1 bit)
EXCH : EXCH
bits : 8 - 15 (8 bit)
AWDCH : AWDCH
bits : 16 - 23 (8 bit)
DFSDM filter 1 interrupt and status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : JEOCF
bits : 0 - 0 (1 bit)
REOCF : REOCF
bits : 1 - 1 (1 bit)
JOVRF : JOVRF
bits : 2 - 2 (1 bit)
ROVRF : ROVRF
bits : 3 - 3 (1 bit)
AWDF : AWDF
bits : 4 - 4 (1 bit)
JCIP : JCIP
bits : 13 - 13 (1 bit)
RCIP : RCIP
bits : 14 - 14 (1 bit)
CKABF : CKABF
bits : 16 - 23 (8 bit)
SCDF : SCDF
bits : 24 - 31 (8 bit)
DFSDM filter 1 interrupt flag clear register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
DFSDM filter 1 injected channel group selection register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : JCHG
bits : 0 - 7 (8 bit)
DFSDM filter 1 control register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : IOSR
bits : 0 - 7 (8 bit)
FOSR : FOSR
bits : 16 - 25 (10 bit)
FORD : FORD
bits : 29 - 31 (3 bit)
DFSDM filter 1 data register for injected group
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : JDATACH
bits : 0 - 2 (3 bit)
JDATA : JDATA
bits : 8 - 31 (24 bit)
DFSDM filter 1 data register for the regular channel
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : RDATACH
bits : 0 - 2 (3 bit)
RPEND : RPEND
bits : 4 - 4 (1 bit)
RDATA : RDATA
bits : 8 - 31 (24 bit)
DFSDM filter 1 analog watchdog high threshold register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : BKAWH
bits : 0 - 3 (4 bit)
AWHT : AWHT
bits : 8 - 31 (24 bit)
DFSDM filter 1 analog watchdog low threshold register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : BKAWL
bits : 0 - 3 (4 bit)
AWLT : AWLT
bits : 8 - 31 (24 bit)
DFSDM filter 1 analog watchdog status register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : AWLTF
bits : 0 - 7 (8 bit)
AWHTF : AWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 1 analog watchdog clear flag register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 1 extremes detector maximum register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
EXMAX : EXMAX
bits : 8 - 31 (24 bit)
DFSDM filter 1 extremes detector minimum register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write
DFSDM filter 1 conversion timer register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
This register specifies the parameters used by channel y.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
DFSDM filter 2 control register 1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFEN
bits : 0 - 0 (1 bit)
JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
JSYNC : JSYNC
bits : 3 - 3 (1 bit)
JSCAN : JSCAN
bits : 4 - 4 (1 bit)
JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)
JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
RCONT : RCONT
bits : 18 - 18 (1 bit)
RSYNC : RSYNC
bits : 19 - 19 (1 bit)
RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
RCH : RCH
bits : 24 - 26 (3 bit)
FAST : FAST
bits : 29 - 29 (1 bit)
AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
DFSDM filter 2 control register 2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
REOCIE : REOCIE
bits : 1 - 1 (1 bit)
JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
SCDIE : SCDIE
bits : 5 - 5 (1 bit)
CKABIE : CKABIE
bits : 6 - 6 (1 bit)
EXCH : EXCH
bits : 8 - 15 (8 bit)
AWDCH : AWDCH
bits : 16 - 23 (8 bit)
DFSDM filter 2 interrupt and status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : JEOCF
bits : 0 - 0 (1 bit)
REOCF : REOCF
bits : 1 - 1 (1 bit)
JOVRF : JOVRF
bits : 2 - 2 (1 bit)
ROVRF : ROVRF
bits : 3 - 3 (1 bit)
AWDF : AWDF
bits : 4 - 4 (1 bit)
JCIP : JCIP
bits : 13 - 13 (1 bit)
RCIP : RCIP
bits : 14 - 14 (1 bit)
CKABF : CKABF
bits : 16 - 23 (8 bit)
SCDF : SCDF
bits : 24 - 31 (8 bit)
DFSDM filter 2 interrupt flag clear register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
DFSDM filter 2 injected channel group selection register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : JCHG
bits : 0 - 7 (8 bit)
DFSDM filter 2 control register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : IOSR
bits : 0 - 7 (8 bit)
FOSR : FOSR
bits : 16 - 25 (10 bit)
FORD : FORD
bits : 29 - 31 (3 bit)
DFSDM filter 2 data register for injected group
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : JDATACH
bits : 0 - 2 (3 bit)
JDATA : JDATA
bits : 8 - 31 (24 bit)
DFSDM filter 2 data register for the regular channel
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : RDATACH
bits : 0 - 2 (3 bit)
RPEND : RPEND
bits : 4 - 4 (1 bit)
RDATA : RDATA
bits : 8 - 31 (24 bit)
DFSDM filter 2 analog watchdog high threshold register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : BKAWH
bits : 0 - 3 (4 bit)
AWHT : AWHT
bits : 8 - 31 (24 bit)
DFSDM filter 2 analog watchdog low threshold register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : BKAWL
bits : 0 - 3 (4 bit)
AWLT : AWLT
bits : 8 - 31 (24 bit)
DFSDM filter 2 analog watchdog status register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : AWLTF
bits : 0 - 7 (8 bit)
AWHTF : AWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 2 analog watchdog clear flag register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 2 extremes detector maximum register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
EXMAX : EXMAX
bits : 8 - 31 (24 bit)
DFSDM filter 2 extremes detector minimum register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write
DFSDM filter 2 conversion timer register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
This register specifies the parameters used by channel y.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM filter 3 control register 1
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFEN
bits : 0 - 0 (1 bit)
JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
JSYNC : JSYNC
bits : 3 - 3 (1 bit)
JSCAN : JSCAN
bits : 4 - 4 (1 bit)
JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)
JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
RCONT : RCONT
bits : 18 - 18 (1 bit)
RSYNC : RSYNC
bits : 19 - 19 (1 bit)
RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
RCH : RCH
bits : 24 - 26 (3 bit)
FAST : FAST
bits : 29 - 29 (1 bit)
AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
DFSDM filter 3 control register 2
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
REOCIE : REOCIE
bits : 1 - 1 (1 bit)
JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
SCDIE : SCDIE
bits : 5 - 5 (1 bit)
CKABIE : CKABIE
bits : 6 - 6 (1 bit)
EXCH : EXCH
bits : 8 - 15 (8 bit)
AWDCH : AWDCH
bits : 16 - 23 (8 bit)
DFSDM filter 3 interrupt and status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : JEOCF
bits : 0 - 0 (1 bit)
REOCF : REOCF
bits : 1 - 1 (1 bit)
JOVRF : JOVRF
bits : 2 - 2 (1 bit)
ROVRF : ROVRF
bits : 3 - 3 (1 bit)
AWDF : AWDF
bits : 4 - 4 (1 bit)
JCIP : JCIP
bits : 13 - 13 (1 bit)
RCIP : RCIP
bits : 14 - 14 (1 bit)
CKABF : CKABF
bits : 16 - 23 (8 bit)
SCDF : SCDF
bits : 24 - 31 (8 bit)
DFSDM filter 3 interrupt flag clear register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
DFSDM filter 3 injected channel group selection register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : JCHG
bits : 0 - 7 (8 bit)
DFSDM filter 3 control register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : IOSR
bits : 0 - 7 (8 bit)
FOSR : FOSR
bits : 16 - 25 (10 bit)
FORD : FORD
bits : 29 - 31 (3 bit)
DFSDM filter 3 data register for injected group
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : JDATACH
bits : 0 - 2 (3 bit)
JDATA : JDATA
bits : 8 - 31 (24 bit)
DFSDM filter 3 data register for the regular channel
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : RDATACH
bits : 0 - 2 (3 bit)
RPEND : RPEND
bits : 4 - 4 (1 bit)
RDATA : RDATA
bits : 8 - 31 (24 bit)
DFSDM filter 3 analog watchdog high threshold register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : BKAWH
bits : 0 - 3 (4 bit)
AWHT : AWHT
bits : 8 - 31 (24 bit)
DFSDM filter 3 analog watchdog low threshold register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : BKAWL
bits : 0 - 3 (4 bit)
AWLT : AWLT
bits : 8 - 31 (24 bit)
DFSDM filter 3 analog watchdog status register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : AWLTF
bits : 0 - 7 (8 bit)
AWHTF : AWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 3 analog watchdog clear flag register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 3 extremes detector maximum register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
EXMAX : EXMAX
bits : 8 - 31 (24 bit)
DFSDM filter 3 extremes detector minimum register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write
DFSDM filter 3 conversion timer register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM filter 4 control register 1
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFEN
bits : 0 - 0 (1 bit)
JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
JSYNC : JSYNC
bits : 3 - 3 (1 bit)
JSCAN : JSCAN
bits : 4 - 4 (1 bit)
JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)
JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
RCONT : RCONT
bits : 18 - 18 (1 bit)
RSYNC : RSYNC
bits : 19 - 19 (1 bit)
RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
RCH : RCH
bits : 24 - 26 (3 bit)
FAST : FAST
bits : 29 - 29 (1 bit)
AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
DFSDM filter 4 control register 2
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
REOCIE : REOCIE
bits : 1 - 1 (1 bit)
JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
SCDIE : SCDIE
bits : 5 - 5 (1 bit)
CKABIE : CKABIE
bits : 6 - 6 (1 bit)
EXCH : EXCH
bits : 8 - 15 (8 bit)
AWDCH : AWDCH
bits : 16 - 23 (8 bit)
DFSDM filter 4 interrupt and status register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : JEOCF
bits : 0 - 0 (1 bit)
REOCF : REOCF
bits : 1 - 1 (1 bit)
JOVRF : JOVRF
bits : 2 - 2 (1 bit)
ROVRF : ROVRF
bits : 3 - 3 (1 bit)
AWDF : AWDF
bits : 4 - 4 (1 bit)
JCIP : JCIP
bits : 13 - 13 (1 bit)
RCIP : RCIP
bits : 14 - 14 (1 bit)
CKABF : CKABF
bits : 16 - 23 (8 bit)
SCDF : SCDF
bits : 24 - 31 (8 bit)
DFSDM filter 4 interrupt flag clear register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
DFSDM filter 4 injected channel group selection register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : JCHG
bits : 0 - 7 (8 bit)
DFSDM filter 4 control register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : IOSR
bits : 0 - 7 (8 bit)
FOSR : FOSR
bits : 16 - 25 (10 bit)
FORD : FORD
bits : 29 - 31 (3 bit)
DFSDM filter 4 data register for injected group
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : JDATACH
bits : 0 - 2 (3 bit)
JDATA : JDATA
bits : 8 - 31 (24 bit)
DFSDM filter 4 data register for the regular channel
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : RDATACH
bits : 0 - 2 (3 bit)
RPEND : RPEND
bits : 4 - 4 (1 bit)
RDATA : RDATA
bits : 8 - 31 (24 bit)
DFSDM filter 4 analog watchdog high threshold register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : BKAWH
bits : 0 - 3 (4 bit)
AWHT : AWHT
bits : 8 - 31 (24 bit)
DFSDM filter 4 analog watchdog low threshold register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : BKAWL
bits : 0 - 3 (4 bit)
AWLT : AWLT
bits : 8 - 31 (24 bit)
DFSDM filter 4 analog watchdog status register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : AWLTF
bits : 0 - 7 (8 bit)
AWHTF : AWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 4 analog watchdog clear flag register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 4 extremes detector maximum register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
EXMAX : EXMAX
bits : 8 - 31 (24 bit)
DFSDM filter 4 extremes detector minimum register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write
DFSDM filter 4 conversion timer register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
DFSDM channel 1 delay register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM filter 5 control register 1
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFEN
bits : 0 - 0 (1 bit)
JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)
JSYNC : JSYNC
bits : 3 - 3 (1 bit)
JSCAN : JSCAN
bits : 4 - 4 (1 bit)
JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)
JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)
JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)
RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)
RCONT : RCONT
bits : 18 - 18 (1 bit)
RSYNC : RSYNC
bits : 19 - 19 (1 bit)
RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)
RCH : RCH
bits : 24 - 26 (3 bit)
FAST : FAST
bits : 29 - 29 (1 bit)
AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)
DFSDM filter 5 control register 2
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)
REOCIE : REOCIE
bits : 1 - 1 (1 bit)
JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)
ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)
AWDIE : AWDIE
bits : 4 - 4 (1 bit)
SCDIE : SCDIE
bits : 5 - 5 (1 bit)
CKABIE : CKABIE
bits : 6 - 6 (1 bit)
EXCH : EXCH
bits : 8 - 15 (8 bit)
AWDCH : AWDCH
bits : 16 - 23 (8 bit)
DFSDM filter 5 interrupt and status register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : JEOCF
bits : 0 - 0 (1 bit)
REOCF : REOCF
bits : 1 - 1 (1 bit)
JOVRF : JOVRF
bits : 2 - 2 (1 bit)
ROVRF : ROVRF
bits : 3 - 3 (1 bit)
AWDF : AWDF
bits : 4 - 4 (1 bit)
JCIP : JCIP
bits : 13 - 13 (1 bit)
RCIP : RCIP
bits : 14 - 14 (1 bit)
CKABF : CKABF
bits : 16 - 23 (8 bit)
SCDF : SCDF
bits : 24 - 31 (8 bit)
DFSDM filter 5 interrupt flag clear register
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)
CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)
CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)
CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)
DFSDM filter 5 injected channel group selection register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : JCHG
bits : 0 - 7 (8 bit)
DFSDM filter 5 control register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : IOSR
bits : 0 - 7 (8 bit)
FOSR : FOSR
bits : 16 - 25 (10 bit)
FORD : FORD
bits : 29 - 31 (3 bit)
DFSDM filter 5 data register for injected group
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : JDATACH
bits : 0 - 2 (3 bit)
JDATA : JDATA
bits : 8 - 31 (24 bit)
DFSDM filter 5 data register for the regular channel
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : RDATACH
bits : 0 - 2 (3 bit)
RPEND : RPEND
bits : 4 - 4 (1 bit)
RDATA : RDATA
bits : 8 - 31 (24 bit)
DFSDM filter 5 analog watchdog high threshold register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : BKAWH
bits : 0 - 3 (4 bit)
AWHT : AWHT
bits : 8 - 31 (24 bit)
DFSDM filter 5 analog watchdog low threshold register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : BKAWL
bits : 0 - 3 (4 bit)
AWLT : AWLT
bits : 8 - 31 (24 bit)
DFSDM filter 5 analog watchdog status register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : AWLTF
bits : 0 - 7 (8 bit)
AWHTF : AWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 5 analog watchdog clear flag register
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)
CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)
DFSDM filter 5 extremes detector maximum register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)
EXMAX : EXMAX
bits : 8 - 31 (24 bit)
DFSDM filter 5 extremes detector minimum register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write
DFSDM filter 5 conversion timer register
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)
This register specifies the parameters used by channel y.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
This register specifies the parameters used by channel y.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register specifies the parameters used by channel y.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel 2 delay register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
This register specifies the parameters used by channel y.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register specifies the parameters used by channel y.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel 3 delay register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
This register specifies the hardware configuration of DFSDM peripheral.
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NBT : NBT
bits : 0 - 7 (8 bit)
NBF : NBF
bits : 8 - 15 (8 bit)
This register specifies the version of DFSDM peripheral.
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
This register specifies the identification of DFSDM peripheral.
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
This register specifies the size allocated to DFSDM registers.
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register specifies the parameters used by channel y.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register specifies the parameters used by channel y.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel 4 delay register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
This register specifies the parameters used by channel y.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register specifies the parameters used by channel y.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel 5 delay register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register specifies the parameters used by channel y.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register specifies the parameters used by channel y.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel 6 delay register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
This register specifies the parameters used by channel y.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
This register specifies the parameters used by channel y.
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel 7 delay register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
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