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DFSDM1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection :

Registers

DFSDM_CH0CFGR1

DFSDM_CH0DATINR

DFSDM_FLT0CR1

DFSDM_FLT0CR2

DFSDM_FLT0ISR

DFSDM_FLT0ICR

DFSDM_FLT0JCHGR

DFSDM_FLT0FCR

DFSDM_FLT0JDATAR

DFSDM_FLT0RDATAR

DFSDM_FLT0AWHTR

DFSDM_FLT0AWLTR

DFSDM_FLT0AWSR

DFSDM_FLT0AWCFR

DFSDM_FLT0EXMAX

DFSDM_FLT0EXMIN

DFSDM_FLT0CNVTIMR

DFSDM_CH0DLYR

DFSDM_FLT1CR1

DFSDM_FLT1CR2

DFSDM_FLT1ISR

DFSDM_FLT1ICR

DFSDM_FLT1JCHGR

DFSDM_FLT1FCR

DFSDM_FLT1JDATAR

DFSDM_FLT1RDATAR

DFSDM_FLT1AWHTR

DFSDM_FLT1AWLTR

DFSDM_FLT1AWSR

DFSDM_FLT1AWCFR

DFSDM_FLT1EXMAX

DFSDM_FLT1EXMIN

DFSDM_FLT1CNVTIMR

DFSDM_CH1CFGR1

DFSDM_FLT2CR1

DFSDM_FLT2CR2

DFSDM_FLT2ISR

DFSDM_FLT2ICR

DFSDM_FLT2JCHGR

DFSDM_FLT2FCR

DFSDM_FLT2JDATAR

DFSDM_FLT2RDATAR

DFSDM_FLT2AWHTR

DFSDM_FLT2AWLTR

DFSDM_FLT2AWSR

DFSDM_FLT2AWCFR

DFSDM_FLT2EXMAX

DFSDM_FLT2EXMIN

DFSDM_FLT2CNVTIMR

DFSDM_CH1CFGR2

DFSDM_CH1AWSCDR

DFSDM_FLT3CR1

DFSDM_FLT3CR2

DFSDM_FLT3ISR

DFSDM_FLT3ICR

DFSDM_FLT3JCHGR

DFSDM_FLT3FCR

DFSDM_FLT3JDATAR

DFSDM_FLT3RDATAR

DFSDM_FLT3AWHTR

DFSDM_FLT3AWLTR

DFSDM_FLT3AWSR

DFSDM_FLT3AWCFR

DFSDM_FLT3EXMAX

DFSDM_FLT3EXMIN

DFSDM_FLT3CNVTIMR

DFSDM_CH1WDATR

DFSDM_CH1DATINR

DFSDM_FLT4CR1

DFSDM_FLT4CR2

DFSDM_FLT4ISR

DFSDM_FLT4ICR

DFSDM_FLT4JCHGR

DFSDM_FLT4FCR

DFSDM_FLT4JDATAR

DFSDM_FLT4RDATAR

DFSDM_FLT4AWHTR

DFSDM_FLT4AWLTR

DFSDM_FLT4AWSR

DFSDM_FLT4AWCFR

DFSDM_FLT4EXMAX

DFSDM_FLT4EXMIN

DFSDM_FLT4CNVTIMR

DFSDM_CH1DLYR

DFSDM_FLT5CR1

DFSDM_FLT5CR2

DFSDM_FLT5ISR

DFSDM_FLT5ICR

DFSDM_FLT5JCHGR

DFSDM_FLT5FCR

DFSDM_FLT5JDATAR

DFSDM_FLT5RDATAR

DFSDM_FLT5AWHTR

DFSDM_FLT5AWLTR

DFSDM_FLT5AWSR

DFSDM_FLT5AWCFR

DFSDM_FLT5EXMAX

DFSDM_FLT5EXMIN

DFSDM_FLT5CNVTIMR

DFSDM_CH0CFGR2

DFSDM_CH2CFGR1

DFSDM_CH2CFGR2

DFSDM_CH2AWSCDR

DFSDM_CH2WDATR

DFSDM_CH2DATINR

DFSDM_CH2DLYR

DFSDM_CH3CFGR1

DFSDM_CH3CFGR2

DFSDM_CH3AWSCDR

DFSDM_CH3WDATR

DFSDM_CH3DATINR

DFSDM_CH3DLYR

DFSDM_HWCFGR

DFSDM_VERR

DFSDM_IPIDR

DFSDM_SIDR

DFSDM_CH0AWSCDR

DFSDM_CH4CFGR1

DFSDM_CH4CFGR2

DFSDM_CH4AWSCDR

DFSDM_CH4WDATR

DFSDM_CH4DATINR

DFSDM_CH4DLYR

DFSDM_CH5CFGR1

DFSDM_CH5CFGR2

DFSDM_CH5AWSCDR

DFSDM_CH5WDATR

DFSDM_CH5DATINR

DFSDM_CH5DLYR

DFSDM_CH0WDATR

DFSDM_CH6CFGR1

DFSDM_CH6CFGR2

DFSDM_CH6AWSCDR

DFSDM_CH6WDATR

DFSDM_CH6DATINR

DFSDM_CH6DLYR

DFSDM_CH7CFGR1

DFSDM_CH7CFGR2

DFSDM_CH7AWSCDR

DFSDM_CH7WDATR

DFSDM_CH7DATINR

DFSDM_CH7DLYR


DFSDM_CH0CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0CFGR1 DFSDM_CH0CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH0DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0DATINR DFSDM_CH0DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_FLT0CR1

DFSDM filter 0 control register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CR1 DFSDM_FLT0CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)

JSYNC : JSYNC
bits : 3 - 3 (1 bit)

JSCAN : JSCAN
bits : 4 - 4 (1 bit)

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)

JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)

RCONT : RCONT
bits : 18 - 18 (1 bit)

RSYNC : RSYNC
bits : 19 - 19 (1 bit)

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)

RCH : RCH
bits : 24 - 26 (3 bit)

FAST : FAST
bits : 29 - 29 (1 bit)

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)


DFSDM_FLT0CR2

DFSDM filter 0 control register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CR2 DFSDM_FLT0CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)

REOCIE : REOCIE
bits : 1 - 1 (1 bit)

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)

AWDIE : AWDIE
bits : 4 - 4 (1 bit)

SCDIE : SCDIE
bits : 5 - 5 (1 bit)

CKABIE : CKABIE
bits : 6 - 6 (1 bit)

EXCH : EXCH
bits : 8 - 15 (8 bit)

AWDCH : AWDCH
bits : 16 - 23 (8 bit)


DFSDM_FLT0ISR

DFSDM filter 0 interrupt and status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0ISR DFSDM_FLT0ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)

REOCF : REOCF
bits : 1 - 1 (1 bit)

JOVRF : JOVRF
bits : 2 - 2 (1 bit)

ROVRF : ROVRF
bits : 3 - 3 (1 bit)

AWDF : AWDF
bits : 4 - 4 (1 bit)

JCIP : JCIP
bits : 13 - 13 (1 bit)

RCIP : RCIP
bits : 14 - 14 (1 bit)

CKABF : CKABF
bits : 16 - 23 (8 bit)

SCDF : SCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT0ICR

DFSDM filter 0 interrupt flag clear register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0ICR DFSDM_FLT0ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT0JCHGR

DFSDM filter 0 injected channel group selection register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0JCHGR DFSDM_FLT0JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)


DFSDM_FLT0FCR

DFSDM filter 0 control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0FCR DFSDM_FLT0FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)

FOSR : FOSR
bits : 16 - 25 (10 bit)

FORD : FORD
bits : 29 - 31 (3 bit)


DFSDM_FLT0JDATAR

DFSDM filter 0 data register for injected group
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0JDATAR DFSDM_FLT0JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)

JDATA : JDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT0RDATAR

DFSDM filter 0 data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0RDATAR DFSDM_FLT0RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)

RPEND : RPEND
bits : 4 - 4 (1 bit)

RDATA : RDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT0AWHTR

DFSDM filter 0 analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWHTR DFSDM_FLT0AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)

AWHT : AWHT
bits : 8 - 31 (24 bit)


DFSDM_FLT0AWLTR

DFSDM filter 0 analog watchdog low threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWLTR DFSDM_FLT0AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)

AWLT : AWLT
bits : 8 - 31 (24 bit)


DFSDM_FLT0AWSR

DFSDM filter 0 analog watchdog status register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWSR DFSDM_FLT0AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)

AWHTF : AWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT0AWCFR

DFSDM filter 0 analog watchdog clear flag register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0AWCFR DFSDM_FLT0AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT0EXMAX

DFSDM filter 0 extremes detector maximum register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0EXMAX DFSDM_FLT0EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)

EXMAX : EXMAX
bits : 8 - 31 (24 bit)


DFSDM_FLT0EXMIN

DFSDM filter 0 extremes detector minimum register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0EXMIN DFSDM_FLT0EXMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT0CNVTIMR

DFSDM filter 0 conversion timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT0CNVTIMR DFSDM_FLT0CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)


DFSDM_CH0DLYR

DFSDM channel 0 delay register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0DLYR DFSDM_CH0DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_FLT1CR1

DFSDM filter 1 control register 1
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CR1 DFSDM_FLT1CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)

JSYNC : JSYNC
bits : 3 - 3 (1 bit)

JSCAN : JSCAN
bits : 4 - 4 (1 bit)

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)

JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)

RCONT : RCONT
bits : 18 - 18 (1 bit)

RSYNC : RSYNC
bits : 19 - 19 (1 bit)

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)

RCH : RCH
bits : 24 - 26 (3 bit)

FAST : FAST
bits : 29 - 29 (1 bit)

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)


DFSDM_FLT1CR2

DFSDM filter 1 control register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CR2 DFSDM_FLT1CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)

REOCIE : REOCIE
bits : 1 - 1 (1 bit)

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)

AWDIE : AWDIE
bits : 4 - 4 (1 bit)

SCDIE : SCDIE
bits : 5 - 5 (1 bit)

CKABIE : CKABIE
bits : 6 - 6 (1 bit)

EXCH : EXCH
bits : 8 - 15 (8 bit)

AWDCH : AWDCH
bits : 16 - 23 (8 bit)


DFSDM_FLT1ISR

DFSDM filter 1 interrupt and status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1ISR DFSDM_FLT1ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)

REOCF : REOCF
bits : 1 - 1 (1 bit)

JOVRF : JOVRF
bits : 2 - 2 (1 bit)

ROVRF : ROVRF
bits : 3 - 3 (1 bit)

AWDF : AWDF
bits : 4 - 4 (1 bit)

JCIP : JCIP
bits : 13 - 13 (1 bit)

RCIP : RCIP
bits : 14 - 14 (1 bit)

CKABF : CKABF
bits : 16 - 23 (8 bit)

SCDF : SCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT1ICR

DFSDM filter 1 interrupt flag clear register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1ICR DFSDM_FLT1ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT1JCHGR

DFSDM filter 1 injected channel group selection register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1JCHGR DFSDM_FLT1JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)


DFSDM_FLT1FCR

DFSDM filter 1 control register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1FCR DFSDM_FLT1FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)

FOSR : FOSR
bits : 16 - 25 (10 bit)

FORD : FORD
bits : 29 - 31 (3 bit)


DFSDM_FLT1JDATAR

DFSDM filter 1 data register for injected group
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1JDATAR DFSDM_FLT1JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)

JDATA : JDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT1RDATAR

DFSDM filter 1 data register for the regular channel
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1RDATAR DFSDM_FLT1RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)

RPEND : RPEND
bits : 4 - 4 (1 bit)

RDATA : RDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT1AWHTR

DFSDM filter 1 analog watchdog high threshold register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWHTR DFSDM_FLT1AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)

AWHT : AWHT
bits : 8 - 31 (24 bit)


DFSDM_FLT1AWLTR

DFSDM filter 1 analog watchdog low threshold register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWLTR DFSDM_FLT1AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)

AWLT : AWLT
bits : 8 - 31 (24 bit)


DFSDM_FLT1AWSR

DFSDM filter 1 analog watchdog status register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWSR DFSDM_FLT1AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)

AWHTF : AWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT1AWCFR

DFSDM filter 1 analog watchdog clear flag register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1AWCFR DFSDM_FLT1AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT1EXMAX

DFSDM filter 1 extremes detector maximum register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1EXMAX DFSDM_FLT1EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)

EXMAX : EXMAX
bits : 8 - 31 (24 bit)


DFSDM_FLT1EXMIN

DFSDM filter 1 extremes detector minimum register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1EXMIN DFSDM_FLT1EXMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT1CNVTIMR

DFSDM filter 1 conversion timer register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT1CNVTIMR DFSDM_FLT1CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)


DFSDM_CH1CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1CFGR1 DFSDM_CH1CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_FLT2CR1

DFSDM filter 2 control register 1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CR1 DFSDM_FLT2CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)

JSYNC : JSYNC
bits : 3 - 3 (1 bit)

JSCAN : JSCAN
bits : 4 - 4 (1 bit)

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)

JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)

RCONT : RCONT
bits : 18 - 18 (1 bit)

RSYNC : RSYNC
bits : 19 - 19 (1 bit)

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)

RCH : RCH
bits : 24 - 26 (3 bit)

FAST : FAST
bits : 29 - 29 (1 bit)

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)


DFSDM_FLT2CR2

DFSDM filter 2 control register 2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CR2 DFSDM_FLT2CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)

REOCIE : REOCIE
bits : 1 - 1 (1 bit)

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)

AWDIE : AWDIE
bits : 4 - 4 (1 bit)

SCDIE : SCDIE
bits : 5 - 5 (1 bit)

CKABIE : CKABIE
bits : 6 - 6 (1 bit)

EXCH : EXCH
bits : 8 - 15 (8 bit)

AWDCH : AWDCH
bits : 16 - 23 (8 bit)


DFSDM_FLT2ISR

DFSDM filter 2 interrupt and status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2ISR DFSDM_FLT2ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)

REOCF : REOCF
bits : 1 - 1 (1 bit)

JOVRF : JOVRF
bits : 2 - 2 (1 bit)

ROVRF : ROVRF
bits : 3 - 3 (1 bit)

AWDF : AWDF
bits : 4 - 4 (1 bit)

JCIP : JCIP
bits : 13 - 13 (1 bit)

RCIP : RCIP
bits : 14 - 14 (1 bit)

CKABF : CKABF
bits : 16 - 23 (8 bit)

SCDF : SCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT2ICR

DFSDM filter 2 interrupt flag clear register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2ICR DFSDM_FLT2ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT2JCHGR

DFSDM filter 2 injected channel group selection register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2JCHGR DFSDM_FLT2JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)


DFSDM_FLT2FCR

DFSDM filter 2 control register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2FCR DFSDM_FLT2FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)

FOSR : FOSR
bits : 16 - 25 (10 bit)

FORD : FORD
bits : 29 - 31 (3 bit)


DFSDM_FLT2JDATAR

DFSDM filter 2 data register for injected group
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2JDATAR DFSDM_FLT2JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)

JDATA : JDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT2RDATAR

DFSDM filter 2 data register for the regular channel
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2RDATAR DFSDM_FLT2RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)

RPEND : RPEND
bits : 4 - 4 (1 bit)

RDATA : RDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT2AWHTR

DFSDM filter 2 analog watchdog high threshold register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWHTR DFSDM_FLT2AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)

AWHT : AWHT
bits : 8 - 31 (24 bit)


DFSDM_FLT2AWLTR

DFSDM filter 2 analog watchdog low threshold register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWLTR DFSDM_FLT2AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)

AWLT : AWLT
bits : 8 - 31 (24 bit)


DFSDM_FLT2AWSR

DFSDM filter 2 analog watchdog status register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWSR DFSDM_FLT2AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)

AWHTF : AWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT2AWCFR

DFSDM filter 2 analog watchdog clear flag register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2AWCFR DFSDM_FLT2AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT2EXMAX

DFSDM filter 2 extremes detector maximum register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2EXMAX DFSDM_FLT2EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)

EXMAX : EXMAX
bits : 8 - 31 (24 bit)


DFSDM_FLT2EXMIN

DFSDM filter 2 extremes detector minimum register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2EXMIN DFSDM_FLT2EXMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT2CNVTIMR

DFSDM filter 2 conversion timer register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT2CNVTIMR DFSDM_FLT2CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)


DFSDM_CH1CFGR2

This register specifies the parameters used by channel y.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1CFGR2 DFSDM_CH1CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH1AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1AWSCDR DFSDM_CH1AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_FLT3CR1

DFSDM filter 3 control register 1
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CR1 DFSDM_FLT3CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)

JSYNC : JSYNC
bits : 3 - 3 (1 bit)

JSCAN : JSCAN
bits : 4 - 4 (1 bit)

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)

JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)

RCONT : RCONT
bits : 18 - 18 (1 bit)

RSYNC : RSYNC
bits : 19 - 19 (1 bit)

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)

RCH : RCH
bits : 24 - 26 (3 bit)

FAST : FAST
bits : 29 - 29 (1 bit)

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)


DFSDM_FLT3CR2

DFSDM filter 3 control register 2
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CR2 DFSDM_FLT3CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)

REOCIE : REOCIE
bits : 1 - 1 (1 bit)

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)

AWDIE : AWDIE
bits : 4 - 4 (1 bit)

SCDIE : SCDIE
bits : 5 - 5 (1 bit)

CKABIE : CKABIE
bits : 6 - 6 (1 bit)

EXCH : EXCH
bits : 8 - 15 (8 bit)

AWDCH : AWDCH
bits : 16 - 23 (8 bit)


DFSDM_FLT3ISR

DFSDM filter 3 interrupt and status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3ISR DFSDM_FLT3ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)

REOCF : REOCF
bits : 1 - 1 (1 bit)

JOVRF : JOVRF
bits : 2 - 2 (1 bit)

ROVRF : ROVRF
bits : 3 - 3 (1 bit)

AWDF : AWDF
bits : 4 - 4 (1 bit)

JCIP : JCIP
bits : 13 - 13 (1 bit)

RCIP : RCIP
bits : 14 - 14 (1 bit)

CKABF : CKABF
bits : 16 - 23 (8 bit)

SCDF : SCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT3ICR

DFSDM filter 3 interrupt flag clear register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3ICR DFSDM_FLT3ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT3JCHGR

DFSDM filter 3 injected channel group selection register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3JCHGR DFSDM_FLT3JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)


DFSDM_FLT3FCR

DFSDM filter 3 control register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3FCR DFSDM_FLT3FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)

FOSR : FOSR
bits : 16 - 25 (10 bit)

FORD : FORD
bits : 29 - 31 (3 bit)


DFSDM_FLT3JDATAR

DFSDM filter 3 data register for injected group
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3JDATAR DFSDM_FLT3JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)

JDATA : JDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT3RDATAR

DFSDM filter 3 data register for the regular channel
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3RDATAR DFSDM_FLT3RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)

RPEND : RPEND
bits : 4 - 4 (1 bit)

RDATA : RDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT3AWHTR

DFSDM filter 3 analog watchdog high threshold register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWHTR DFSDM_FLT3AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)

AWHT : AWHT
bits : 8 - 31 (24 bit)


DFSDM_FLT3AWLTR

DFSDM filter 3 analog watchdog low threshold register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWLTR DFSDM_FLT3AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)

AWLT : AWLT
bits : 8 - 31 (24 bit)


DFSDM_FLT3AWSR

DFSDM filter 3 analog watchdog status register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWSR DFSDM_FLT3AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)

AWHTF : AWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT3AWCFR

DFSDM filter 3 analog watchdog clear flag register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3AWCFR DFSDM_FLT3AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT3EXMAX

DFSDM filter 3 extremes detector maximum register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3EXMAX DFSDM_FLT3EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)

EXMAX : EXMAX
bits : 8 - 31 (24 bit)


DFSDM_FLT3EXMIN

DFSDM filter 3 extremes detector minimum register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3EXMIN DFSDM_FLT3EXMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT3CNVTIMR

DFSDM filter 3 conversion timer register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT3CNVTIMR DFSDM_FLT3CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)


DFSDM_CH1WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1WDATR DFSDM_CH1WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH1DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1DATINR DFSDM_CH1DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_FLT4CR1

DFSDM filter 4 control register 1
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4CR1 DFSDM_FLT4CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)

JSYNC : JSYNC
bits : 3 - 3 (1 bit)

JSCAN : JSCAN
bits : 4 - 4 (1 bit)

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)

JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)

RCONT : RCONT
bits : 18 - 18 (1 bit)

RSYNC : RSYNC
bits : 19 - 19 (1 bit)

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)

RCH : RCH
bits : 24 - 26 (3 bit)

FAST : FAST
bits : 29 - 29 (1 bit)

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)


DFSDM_FLT4CR2

DFSDM filter 4 control register 2
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4CR2 DFSDM_FLT4CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)

REOCIE : REOCIE
bits : 1 - 1 (1 bit)

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)

AWDIE : AWDIE
bits : 4 - 4 (1 bit)

SCDIE : SCDIE
bits : 5 - 5 (1 bit)

CKABIE : CKABIE
bits : 6 - 6 (1 bit)

EXCH : EXCH
bits : 8 - 15 (8 bit)

AWDCH : AWDCH
bits : 16 - 23 (8 bit)


DFSDM_FLT4ISR

DFSDM filter 4 interrupt and status register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4ISR DFSDM_FLT4ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)

REOCF : REOCF
bits : 1 - 1 (1 bit)

JOVRF : JOVRF
bits : 2 - 2 (1 bit)

ROVRF : ROVRF
bits : 3 - 3 (1 bit)

AWDF : AWDF
bits : 4 - 4 (1 bit)

JCIP : JCIP
bits : 13 - 13 (1 bit)

RCIP : RCIP
bits : 14 - 14 (1 bit)

CKABF : CKABF
bits : 16 - 23 (8 bit)

SCDF : SCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT4ICR

DFSDM filter 4 interrupt flag clear register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4ICR DFSDM_FLT4ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT4JCHGR

DFSDM filter 4 injected channel group selection register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4JCHGR DFSDM_FLT4JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)


DFSDM_FLT4FCR

DFSDM filter 4 control register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4FCR DFSDM_FLT4FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)

FOSR : FOSR
bits : 16 - 25 (10 bit)

FORD : FORD
bits : 29 - 31 (3 bit)


DFSDM_FLT4JDATAR

DFSDM filter 4 data register for injected group
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4JDATAR DFSDM_FLT4JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)

JDATA : JDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT4RDATAR

DFSDM filter 4 data register for the regular channel
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4RDATAR DFSDM_FLT4RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)

RPEND : RPEND
bits : 4 - 4 (1 bit)

RDATA : RDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT4AWHTR

DFSDM filter 4 analog watchdog high threshold register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4AWHTR DFSDM_FLT4AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)

AWHT : AWHT
bits : 8 - 31 (24 bit)


DFSDM_FLT4AWLTR

DFSDM filter 4 analog watchdog low threshold register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4AWLTR DFSDM_FLT4AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)

AWLT : AWLT
bits : 8 - 31 (24 bit)


DFSDM_FLT4AWSR

DFSDM filter 4 analog watchdog status register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4AWSR DFSDM_FLT4AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)

AWHTF : AWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT4AWCFR

DFSDM filter 4 analog watchdog clear flag register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4AWCFR DFSDM_FLT4AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT4EXMAX

DFSDM filter 4 extremes detector maximum register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4EXMAX DFSDM_FLT4EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)

EXMAX : EXMAX
bits : 8 - 31 (24 bit)


DFSDM_FLT4EXMIN

DFSDM filter 4 extremes detector minimum register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4EXMIN DFSDM_FLT4EXMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT4CNVTIMR

DFSDM filter 4 conversion timer register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT4CNVTIMR DFSDM_FLT4CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)


DFSDM_CH1DLYR

DFSDM channel 1 delay register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH1DLYR DFSDM_CH1DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_FLT5CR1

DFSDM filter 5 control register 1
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5CR1 DFSDM_FLT5CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFEN
bits : 0 - 0 (1 bit)

JSWSTART : JSWSTART
bits : 1 - 1 (1 bit)

JSYNC : JSYNC
bits : 3 - 3 (1 bit)

JSCAN : JSCAN
bits : 4 - 4 (1 bit)

JDMAEN : JDMAEN
bits : 5 - 5 (1 bit)

JEXTSEL : JEXTSEL
bits : 8 - 12 (5 bit)

JEXTEN : JEXTEN
bits : 13 - 14 (2 bit)

RSWSTART : RSWSTART
bits : 17 - 17 (1 bit)

RCONT : RCONT
bits : 18 - 18 (1 bit)

RSYNC : RSYNC
bits : 19 - 19 (1 bit)

RDMAEN : RDMAEN
bits : 21 - 21 (1 bit)

RCH : RCH
bits : 24 - 26 (3 bit)

FAST : FAST
bits : 29 - 29 (1 bit)

AWFSEL : AWFSEL
bits : 30 - 30 (1 bit)


DFSDM_FLT5CR2

DFSDM filter 5 control register 2
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5CR2 DFSDM_FLT5CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : JEOCIE
bits : 0 - 0 (1 bit)

REOCIE : REOCIE
bits : 1 - 1 (1 bit)

JOVRIE : JOVRIE
bits : 2 - 2 (1 bit)

ROVRIE : ROVRIE
bits : 3 - 3 (1 bit)

AWDIE : AWDIE
bits : 4 - 4 (1 bit)

SCDIE : SCDIE
bits : 5 - 5 (1 bit)

CKABIE : CKABIE
bits : 6 - 6 (1 bit)

EXCH : EXCH
bits : 8 - 15 (8 bit)

AWDCH : AWDCH
bits : 16 - 23 (8 bit)


DFSDM_FLT5ISR

DFSDM filter 5 interrupt and status register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5ISR DFSDM_FLT5ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : JEOCF
bits : 0 - 0 (1 bit)

REOCF : REOCF
bits : 1 - 1 (1 bit)

JOVRF : JOVRF
bits : 2 - 2 (1 bit)

ROVRF : ROVRF
bits : 3 - 3 (1 bit)

AWDF : AWDF
bits : 4 - 4 (1 bit)

JCIP : JCIP
bits : 13 - 13 (1 bit)

RCIP : RCIP
bits : 14 - 14 (1 bit)

CKABF : CKABF
bits : 16 - 23 (8 bit)

SCDF : SCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT5ICR

DFSDM filter 5 interrupt flag clear register
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5ICR DFSDM_FLT5ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : CLRJOVRF
bits : 2 - 2 (1 bit)

CLRROVRF : CLRROVRF
bits : 3 - 3 (1 bit)

CLRCKABF : CLRCKABF
bits : 16 - 23 (8 bit)

CLRSCDF : CLRSCDF
bits : 24 - 31 (8 bit)


DFSDM_FLT5JCHGR

DFSDM filter 5 injected channel group selection register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5JCHGR DFSDM_FLT5JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : JCHG
bits : 0 - 7 (8 bit)


DFSDM_FLT5FCR

DFSDM filter 5 control register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5FCR DFSDM_FLT5FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : IOSR
bits : 0 - 7 (8 bit)

FOSR : FOSR
bits : 16 - 25 (10 bit)

FORD : FORD
bits : 29 - 31 (3 bit)


DFSDM_FLT5JDATAR

DFSDM filter 5 data register for injected group
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5JDATAR DFSDM_FLT5JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : JDATACH
bits : 0 - 2 (3 bit)

JDATA : JDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT5RDATAR

DFSDM filter 5 data register for the regular channel
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5RDATAR DFSDM_FLT5RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : RDATACH
bits : 0 - 2 (3 bit)

RPEND : RPEND
bits : 4 - 4 (1 bit)

RDATA : RDATA
bits : 8 - 31 (24 bit)


DFSDM_FLT5AWHTR

DFSDM filter 5 analog watchdog high threshold register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5AWHTR DFSDM_FLT5AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : BKAWH
bits : 0 - 3 (4 bit)

AWHT : AWHT
bits : 8 - 31 (24 bit)


DFSDM_FLT5AWLTR

DFSDM filter 5 analog watchdog low threshold register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5AWLTR DFSDM_FLT5AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : BKAWL
bits : 0 - 3 (4 bit)

AWLT : AWLT
bits : 8 - 31 (24 bit)


DFSDM_FLT5AWSR

DFSDM filter 5 analog watchdog status register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5AWSR DFSDM_FLT5AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : AWLTF
bits : 0 - 7 (8 bit)

AWHTF : AWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT5AWCFR

DFSDM filter 5 analog watchdog clear flag register
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5AWCFR DFSDM_FLT5AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : CLRAWLTF
bits : 0 - 7 (8 bit)

CLRAWHTF : CLRAWHTF
bits : 8 - 15 (8 bit)


DFSDM_FLT5EXMAX

DFSDM filter 5 extremes detector maximum register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5EXMAX DFSDM_FLT5EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : EXMAXCH
bits : 0 - 2 (3 bit)

EXMAX : EXMAX
bits : 8 - 31 (24 bit)


DFSDM_FLT5EXMIN

DFSDM filter 5 extremes detector minimum register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5EXMIN DFSDM_FLT5EXMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : EXMINCH
bits : 0 - 2 (3 bit)
access : read-only

EXMIN : EXMIN
bits : 8 - 31 (24 bit)
access : read-write


DFSDM_FLT5CNVTIMR

DFSDM filter 5 conversion timer register
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_FLT5CNVTIMR DFSDM_FLT5CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : CNVCNT
bits : 4 - 31 (28 bit)


DFSDM_CH0CFGR2

This register specifies the parameters used by channel y.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0CFGR2 DFSDM_CH0CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH2CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2CFGR1 DFSDM_CH2CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH2CFGR2

This register specifies the parameters used by channel y.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2CFGR2 DFSDM_CH2CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH2AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2AWSCDR DFSDM_CH2AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH2WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2WDATR DFSDM_CH2WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH2DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2DATINR DFSDM_CH2DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_CH2DLYR

DFSDM channel 2 delay register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH2DLYR DFSDM_CH2DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_CH3CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3CFGR1 DFSDM_CH3CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH3CFGR2

This register specifies the parameters used by channel y.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3CFGR2 DFSDM_CH3CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH3AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3AWSCDR DFSDM_CH3AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH3WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3WDATR DFSDM_CH3WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH3DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3DATINR DFSDM_CH3DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_CH3DLYR

DFSDM channel 3 delay register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH3DLYR DFSDM_CH3DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_HWCFGR

This register specifies the hardware configuration of DFSDM peripheral.
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_HWCFGR DFSDM_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBT NBF

NBT : NBT
bits : 0 - 7 (8 bit)

NBF : NBF
bits : 8 - 15 (8 bit)


DFSDM_VERR

This register specifies the version of DFSDM peripheral.
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_VERR DFSDM_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


DFSDM_IPIDR

This register specifies the identification of DFSDM peripheral.
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_IPIDR DFSDM_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


DFSDM_SIDR

This register specifies the size allocated to DFSDM registers.
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_SIDR DFSDM_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


DFSDM_CH0AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0AWSCDR DFSDM_CH0AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH4CFGR1

This register specifies the parameters used by channel y.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4CFGR1 DFSDM_CH4CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH4CFGR2

This register specifies the parameters used by channel y.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4CFGR2 DFSDM_CH4CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH4AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4AWSCDR DFSDM_CH4AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH4WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4WDATR DFSDM_CH4WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH4DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4DATINR DFSDM_CH4DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_CH4DLYR

DFSDM channel 4 delay register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH4DLYR DFSDM_CH4DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_CH5CFGR1

This register specifies the parameters used by channel y.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5CFGR1 DFSDM_CH5CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH5CFGR2

This register specifies the parameters used by channel y.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5CFGR2 DFSDM_CH5CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH5AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5AWSCDR DFSDM_CH5AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH5WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5WDATR DFSDM_CH5WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH5DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5DATINR DFSDM_CH5DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_CH5DLYR

DFSDM channel 5 delay register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH5DLYR DFSDM_CH5DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_CH0WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH0WDATR DFSDM_CH0WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH6CFGR1

This register specifies the parameters used by channel y.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6CFGR1 DFSDM_CH6CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH6CFGR2

This register specifies the parameters used by channel y.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6CFGR2 DFSDM_CH6CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH6AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6AWSCDR DFSDM_CH6AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH6WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6WDATR DFSDM_CH6WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH6DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6DATINR DFSDM_CH6DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_CH6DLYR

DFSDM channel 6 delay register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH6DLYR DFSDM_CH6DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)


DFSDM_CH7CFGR1

This register specifies the parameters used by channel y.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7CFGR1 DFSDM_CH7CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : SITP
bits : 0 - 1 (2 bit)

SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)

SCDEN : SCDEN
bits : 5 - 5 (1 bit)

CKABEN : CKABEN
bits : 6 - 6 (1 bit)

CHEN : CHEN
bits : 7 - 7 (1 bit)

CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)

DATMPX : DATMPX
bits : 12 - 13 (2 bit)

DATPACK : DATPACK
bits : 14 - 15 (2 bit)

CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)

CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)

DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)


DFSDM_CH7CFGR2

This register specifies the parameters used by channel y.
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7CFGR2 DFSDM_CH7CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : DTRBS
bits : 3 - 7 (5 bit)

OFFSET : OFFSET
bits : 8 - 31 (24 bit)


DFSDM_CH7AWSCDR

Short-circuit detector and analog watchdog settings for channel y.
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7AWSCDR DFSDM_CH7AWSCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : SCDT
bits : 0 - 7 (8 bit)

BKSCD : BKSCD
bits : 12 - 15 (4 bit)

AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)

AWFORD : AWFORD
bits : 22 - 23 (2 bit)


DFSDM_CH7WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7WDATR DFSDM_CH7WDATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : WDATA
bits : 0 - 15 (16 bit)


DFSDM_CH7DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7DATINR DFSDM_CH7DATINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : INDAT0
bits : 0 - 15 (16 bit)

INDAT1 : INDAT1
bits : 16 - 31 (16 bit)


DFSDM_CH7DLYR

DFSDM channel 7 delay register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CH7DLYR DFSDM_CH7DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLSSKP

PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)



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