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DMA1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DMA_LISR

DMA_S0CR

DMA_S0NDTR

DMA_S0PAR

DMA_S0M0AR

DMA_S0M1AR

DMA_S0FCR

DMA_S1CR

DMA_S1NDTR

DMA_S1PAR

DMA_S1M0AR

DMA_S1M1AR

DMA_S1FCR

DMA_HWCFGR2

DMA_HWCFGR1

DMA_VERR

DMA_IPDR

DMA_SIDR

DMA_HISR

DMA_S2CR

DMA_S2NDTR

DMA_S2PAR

DMA_S2M0AR

DMA_S2M1AR

DMA_S2FCR

DMA_S3CR

DMA_S3NDTR

DMA_S3PAR

DMA_S3M0AR

DMA_S3M1AR

DMA_S3FCR

DMA_S4CR

DMA_S4NDTR

DMA_S4PAR

DMA_S4M0AR

DMA_LIFCR

DMA_S4M1AR

DMA_S4FCR

DMA_S5CR

DMA_S5NDTR

DMA_S5PAR

DMA_S5M0AR

DMA_S5M1AR

DMA_S5FCR

DMA_S6CR

DMA_S6NDTR

DMA_S6PAR

DMA_S6M0AR

DMA_S6M1AR

DMA_S6FCR

DMA_S7CR

DMA_S7NDTR

DMA_HIFCR

DMA_S7PAR

DMA_S7M0AR

DMA_S7M1AR

DMA_S7FCR


DMA_LISR

DMA low interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_LISR DMA_LISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEIF0 DMEIF0 TEIF0 HTIF0 TCIF0 FEIF1 DMEIF1 TEIF1 HTIF1 TCIF1 FEIF2 DMEIF2 TEIF2 HTIF2 TCIF2 FEIF3 DMEIF3 TEIF3 HTIF3 TCIF3

FEIF0 : FEIF0
bits : 0 - 0 (1 bit)

DMEIF0 : DMEIF0
bits : 2 - 2 (1 bit)

TEIF0 : TEIF0
bits : 3 - 3 (1 bit)

HTIF0 : HTIF0
bits : 4 - 4 (1 bit)

TCIF0 : TCIF0
bits : 5 - 5 (1 bit)

FEIF1 : FEIF1
bits : 6 - 6 (1 bit)

DMEIF1 : DMEIF1
bits : 8 - 8 (1 bit)

TEIF1 : TEIF1
bits : 9 - 9 (1 bit)

HTIF1 : HTIF1
bits : 10 - 10 (1 bit)

TCIF1 : TCIF1
bits : 11 - 11 (1 bit)

FEIF2 : FEIF2
bits : 16 - 16 (1 bit)

DMEIF2 : DMEIF2
bits : 18 - 18 (1 bit)

TEIF2 : TEIF2
bits : 19 - 19 (1 bit)

HTIF2 : HTIF2
bits : 20 - 20 (1 bit)

TCIF2 : TCIF2
bits : 21 - 21 (1 bit)

FEIF3 : FEIF3
bits : 22 - 22 (1 bit)

DMEIF3 : DMEIF3
bits : 24 - 24 (1 bit)

TEIF3 : TEIF3
bits : 25 - 25 (1 bit)

HTIF3 : HTIF3
bits : 26 - 26 (1 bit)

TCIF3 : TCIF3
bits : 27 - 27 (1 bit)


DMA_S0CR

This register is used to configure the concerned stream.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S0CR DMA_S0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S0NDTR

DMA stream 0 number of data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S0NDTR DMA_S0NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S0PAR

DMA stream 0 peripheral address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S0PAR DMA_S0PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S0M0AR

DMA stream 0 memory 0 address register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S0M0AR DMA_S0M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S0M1AR

DMA stream 0 memory 1 address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S0M1AR DMA_S0M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S0FCR

DMA stream 0 FIFO control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S0FCR DMA_S0FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_S1CR

This register is used to configure the concerned stream.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S1CR DMA_S1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S1NDTR

DMA stream 1 number of data register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S1NDTR DMA_S1NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S1PAR

DMA stream 1 peripheral address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S1PAR DMA_S1PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S1M0AR

DMA stream 1 memory 0 address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S1M0AR DMA_S1M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S1M1AR

DMA stream 1 memory 1 address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S1M1AR DMA_S1M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S1FCR

DMA stream 1 FIFO control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S1FCR DMA_S1FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_HWCFGR2

DMA hardware configuration 2register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_HWCFGR2 DMA_HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_SIZE WRITE_BUFFERABLE CHSEL_WIDTH

FIFO_SIZE : FIFO_SIZE
bits : 0 - 1 (2 bit)

WRITE_BUFFERABLE : WRITE_BUFFERABLE
bits : 4 - 4 (1 bit)

CHSEL_WIDTH : CHSEL_WIDTH
bits : 8 - 10 (3 bit)


DMA_HWCFGR1

DMA hardware configuration 1 register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_HWCFGR1 DMA_HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_DEF0 DMA_DEF1 DMA_DEF2 DMA_DEF3 DMA_DEF4 DMA_DEF5 DMA_DEF6 DMA_DEF7

DMA_DEF0 : DMA_DEF0
bits : 0 - 1 (2 bit)

DMA_DEF1 : DMA_DEF1
bits : 4 - 5 (2 bit)

DMA_DEF2 : DMA_DEF2
bits : 8 - 9 (2 bit)

DMA_DEF3 : DMA_DEF3
bits : 12 - 13 (2 bit)

DMA_DEF4 : DMA_DEF4
bits : 16 - 17 (2 bit)

DMA_DEF5 : DMA_DEF5
bits : 20 - 21 (2 bit)

DMA_DEF6 : DMA_DEF6
bits : 24 - 25 (2 bit)

DMA_DEF7 : DMA_DEF7
bits : 28 - 29 (2 bit)


DMA_VERR

This register identifies the version of the IP.
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_VERR DMA_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


DMA_IPDR

DMA IP identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_IPDR DMA_IPDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


DMA_SIDR

DMA size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_SIDR DMA_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


DMA_HISR

DMA high interrupt status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_HISR DMA_HISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEIF4 DMEIF4 TEIF4 HTIF4 TCIF4 FEIF5 DMEIF5 TEIF5 HTIF5 TCIF5 FEIF6 DMEIF6 TEIF6 HTIF6 TCIF6 FEIF7 DMEIF7 TEIF7 HTIF7 TCIF7

FEIF4 : FEIF4
bits : 0 - 0 (1 bit)

DMEIF4 : DMEIF4
bits : 2 - 2 (1 bit)

TEIF4 : TEIF4
bits : 3 - 3 (1 bit)

HTIF4 : HTIF4
bits : 4 - 4 (1 bit)

TCIF4 : TCIF4
bits : 5 - 5 (1 bit)

FEIF5 : FEIF5
bits : 6 - 6 (1 bit)

DMEIF5 : DMEIF5
bits : 8 - 8 (1 bit)

TEIF5 : TEIF5
bits : 9 - 9 (1 bit)

HTIF5 : HTIF5
bits : 10 - 10 (1 bit)

TCIF5 : TCIF5
bits : 11 - 11 (1 bit)

FEIF6 : FEIF6
bits : 16 - 16 (1 bit)

DMEIF6 : DMEIF6
bits : 18 - 18 (1 bit)

TEIF6 : TEIF6
bits : 19 - 19 (1 bit)

HTIF6 : HTIF6
bits : 20 - 20 (1 bit)

TCIF6 : TCIF6
bits : 21 - 21 (1 bit)

FEIF7 : FEIF7
bits : 22 - 22 (1 bit)

DMEIF7 : DMEIF7
bits : 24 - 24 (1 bit)

TEIF7 : TEIF7
bits : 25 - 25 (1 bit)

HTIF7 : HTIF7
bits : 26 - 26 (1 bit)

TCIF7 : TCIF7
bits : 27 - 27 (1 bit)


DMA_S2CR

This register is used to configure the concerned stream.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S2CR DMA_S2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S2NDTR

DMA stream 2 number of data register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S2NDTR DMA_S2NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S2PAR

DMA stream 2 peripheral address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S2PAR DMA_S2PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S2M0AR

DMA stream 2 memory 0 address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S2M0AR DMA_S2M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S2M1AR

DMA stream 2 memory 1 address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S2M1AR DMA_S2M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S2FCR

DMA stream 2 FIFO control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S2FCR DMA_S2FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_S3CR

This register is used to configure the concerned stream.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S3CR DMA_S3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S3NDTR

DMA stream 3 number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S3NDTR DMA_S3NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S3PAR

DMA stream 3 peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S3PAR DMA_S3PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S3M0AR

DMA stream 3 memory 0 address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S3M0AR DMA_S3M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S3M1AR

DMA stream 3 memory 1 address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S3M1AR DMA_S3M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S3FCR

DMA stream 3 FIFO control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S3FCR DMA_S3FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_S4CR

This register is used to configure the concerned stream.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S4CR DMA_S4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S4NDTR

DMA stream 4 number of data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S4NDTR DMA_S4NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S4PAR

DMA stream 4 peripheral address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S4PAR DMA_S4PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S4M0AR

DMA stream 4 memory 0 address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S4M0AR DMA_S4M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_LIFCR

DMA low interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMA_LIFCR DMA_LIFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFEIF0 CDMEIF0 CTEIF0 CHTIF0 CTCIF0 CFEIF1 CDMEIF1 CTEIF1 CHTIF1 CTCIF1 CFEIF2 CDMEIF2 CTEIF2 CHTIF2 CTCIF2 CFEIF3 CDMEIF3 CTEIF3 CHTIF3 CTCIF3

CFEIF0 : CFEIF0
bits : 0 - 0 (1 bit)

CDMEIF0 : CDMEIF0
bits : 2 - 2 (1 bit)

CTEIF0 : CTEIF0
bits : 3 - 3 (1 bit)

CHTIF0 : CHTIF0
bits : 4 - 4 (1 bit)

CTCIF0 : CTCIF0
bits : 5 - 5 (1 bit)

CFEIF1 : CFEIF1
bits : 6 - 6 (1 bit)

CDMEIF1 : CDMEIF1
bits : 8 - 8 (1 bit)

CTEIF1 : CTEIF1
bits : 9 - 9 (1 bit)

CHTIF1 : CHTIF1
bits : 10 - 10 (1 bit)

CTCIF1 : CTCIF1
bits : 11 - 11 (1 bit)

CFEIF2 : CFEIF2
bits : 16 - 16 (1 bit)

CDMEIF2 : CDMEIF2
bits : 18 - 18 (1 bit)

CTEIF2 : CTEIF2
bits : 19 - 19 (1 bit)

CHTIF2 : CHTIF2
bits : 20 - 20 (1 bit)

CTCIF2 : CTCIF2
bits : 21 - 21 (1 bit)

CFEIF3 : CFEIF3
bits : 22 - 22 (1 bit)

CDMEIF3 : CDMEIF3
bits : 24 - 24 (1 bit)

CTEIF3 : CTEIF3
bits : 25 - 25 (1 bit)

CHTIF3 : CHTIF3
bits : 26 - 26 (1 bit)

CTCIF3 : CTCIF3
bits : 27 - 27 (1 bit)


DMA_S4M1AR

DMA stream 4 memory 1 address register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S4M1AR DMA_S4M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S4FCR

DMA stream 4 FIFO control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S4FCR DMA_S4FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_S5CR

This register is used to configure the concerned stream.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S5CR DMA_S5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S5NDTR

DMA stream 5 number of data register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S5NDTR DMA_S5NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S5PAR

DMA stream 5 peripheral address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S5PAR DMA_S5PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S5M0AR

DMA stream 5 memory 0 address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S5M0AR DMA_S5M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S5M1AR

DMA stream 5 memory 1 address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S5M1AR DMA_S5M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S5FCR

DMA stream 5 FIFO control register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S5FCR DMA_S5FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_S6CR

This register is used to configure the concerned stream.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S6CR DMA_S6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S6NDTR

DMA stream 6 number of data register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S6NDTR DMA_S6NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_S6PAR

DMA stream 6 peripheral address register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S6PAR DMA_S6PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S6M0AR

DMA stream 6 memory 0 address register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S6M0AR DMA_S6M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S6M1AR

DMA stream 6 memory 1 address register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S6M1AR DMA_S6M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S6FCR

DMA stream 6 FIFO control register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S6FCR DMA_S6FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write


DMA_S7CR

This register is used to configure the concerned stream.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S7CR DMA_S7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMEIE TEIE HTIE TCIE PFCTRL DIR CIRC PINC MINC PSIZE MSIZE PINCOS PL DBM CT PBURST MBURST

EN : EN
bits : 0 - 0 (1 bit)

DMEIE : DMEIE
bits : 1 - 1 (1 bit)

TEIE : TEIE
bits : 2 - 2 (1 bit)

HTIE : HTIE
bits : 3 - 3 (1 bit)

TCIE : TCIE
bits : 4 - 4 (1 bit)

PFCTRL : PFCTRL
bits : 5 - 5 (1 bit)

DIR : DIR
bits : 6 - 7 (2 bit)

CIRC : CIRC
bits : 8 - 8 (1 bit)

PINC : PINC
bits : 9 - 9 (1 bit)

MINC : MINC
bits : 10 - 10 (1 bit)

PSIZE : PSIZE
bits : 11 - 12 (2 bit)

MSIZE : MSIZE
bits : 13 - 14 (2 bit)

PINCOS : PINCOS
bits : 15 - 15 (1 bit)

PL : PL
bits : 16 - 17 (2 bit)

DBM : DBM
bits : 18 - 18 (1 bit)

CT : CT
bits : 19 - 19 (1 bit)

PBURST : PBURST
bits : 21 - 22 (2 bit)

MBURST : MBURST
bits : 23 - 24 (2 bit)


DMA_S7NDTR

DMA stream 7 number of data register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S7NDTR DMA_S7NDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 15 (16 bit)


DMA_HIFCR

DMA high interrupt flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMA_HIFCR DMA_HIFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFEIF4 CDMEIF4 CTEIF4 CHTIF4 CTCIF4 CFEIF5 CDMEIF5 CTEIF5 CHTIF5 CTCIF5 CFEIF6 CDMEIF6 CTEIF6 CHTIF6 CTCIF6 CFEIF7 CDMEIF7 CTEIF7 CHTIF7 CTCIF7

CFEIF4 : CFEIF4
bits : 0 - 0 (1 bit)

CDMEIF4 : CDMEIF4
bits : 2 - 2 (1 bit)

CTEIF4 : CTEIF4
bits : 3 - 3 (1 bit)

CHTIF4 : CHTIF4
bits : 4 - 4 (1 bit)

CTCIF4 : CTCIF4
bits : 5 - 5 (1 bit)

CFEIF5 : CFEIF5
bits : 6 - 6 (1 bit)

CDMEIF5 : CDMEIF5
bits : 8 - 8 (1 bit)

CTEIF5 : CTEIF5
bits : 9 - 9 (1 bit)

CHTIF5 : CHTIF5
bits : 10 - 10 (1 bit)

CTCIF5 : CTCIF5
bits : 11 - 11 (1 bit)

CFEIF6 : CFEIF6
bits : 16 - 16 (1 bit)

CDMEIF6 : CDMEIF6
bits : 18 - 18 (1 bit)

CTEIF6 : CTEIF6
bits : 19 - 19 (1 bit)

CHTIF6 : CHTIF6
bits : 20 - 20 (1 bit)

CTCIF6 : CTCIF6
bits : 21 - 21 (1 bit)

CFEIF7 : CFEIF7
bits : 22 - 22 (1 bit)

CDMEIF7 : CDMEIF7
bits : 24 - 24 (1 bit)

CTEIF7 : CTEIF7
bits : 25 - 25 (1 bit)

CHTIF7 : CHTIF7
bits : 26 - 26 (1 bit)

CTCIF7 : CTCIF7
bits : 27 - 27 (1 bit)


DMA_S7PAR

DMA stream 7 peripheral address register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S7PAR DMA_S7PAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR

PAR : PAR
bits : 0 - 31 (32 bit)


DMA_S7M0AR

DMA stream 7 memory 0 address register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S7M0AR DMA_S7M0AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A

M0A : M0A
bits : 0 - 31 (32 bit)


DMA_S7M1AR

DMA stream 7 memory 1 address register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S7M1AR DMA_S7M1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A

M1A : M1A
bits : 0 - 31 (32 bit)


DMA_S7FCR

DMA stream 7 FIFO control register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_S7FCR DMA_S7FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTH DMDIS FS FEIE

FTH : FTH
bits : 0 - 1 (2 bit)
access : read-write

DMDIS : DMDIS
bits : 2 - 2 (1 bit)
access : read-write

FS : FS
bits : 3 - 5 (3 bit)
access : read-only

FEIE : FEIE
bits : 7 - 7 (1 bit)
access : read-write



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