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DTS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DTS_CFGR1 (CFGR1)

DTS_RAMPVALR (RAMPVALR)

DTS_ITR1 (ITR1)

DTS_DR (DR)

DTS_SR (SR)

DTS_ITENR (ITENR)

DTS_ICIFR (ICIFR)

DTS_OR (OR)

DTS_T0VALR1 (T0VALR1)


DTS_CFGR1 (CFGR1)

DTS_CFGR1 is the configuration register for temperature sensor 1.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS_CFGR1 DTS_CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_EN TS1_START TS1_INTRIG_SEL TS1_SMP_TIME REFCLK_SEL Q_MEAS_opt HSREF_CLK_DIV

TS1_EN : TS1_EN
bits : 0 - 0 (1 bit)

TS1_START : TS1_START
bits : 4 - 4 (1 bit)

TS1_INTRIG_SEL : TS1_INTRIG_SEL
bits : 8 - 11 (4 bit)

TS1_SMP_TIME : TS1_SMP_TIME
bits : 16 - 19 (4 bit)

REFCLK_SEL : REFCLK_SEL
bits : 20 - 20 (1 bit)

Q_MEAS_opt : Q_MEAS_opt
bits : 21 - 21 (1 bit)

HSREF_CLK_DIV : HSREF_CLK_DIV
bits : 24 - 30 (7 bit)


DTS_RAMPVALR (RAMPVALR)

The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTS_RAMPVALR DTS_RAMPVALR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_RAMP_COEFF

TS1_RAMP_COEFF : TS1_RAMP_COEFF
bits : 0 - 15 (16 bit)


DTS_ITR1 (ITR1)

DTS_ITR1 contains the threshold values for sensor 1.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS_ITR1 DTS_ITR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_LITTHD TS1_HITTHD

TS1_LITTHD : TS1_LITTHD
bits : 0 - 15 (16 bit)

TS1_HITTHD : TS1_HITTHD
bits : 16 - 31 (16 bit)


DTS_DR (DR)

The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS_DR DTS_DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_MFREQ

TS1_MFREQ : TS1_MFREQ
bits : 0 - 15 (16 bit)


DTS_SR (SR)

Temperature sensor status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTS_SR DTS_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_ITEF TS1_ITLF TS1_ITHF TS1_AITEF TS1_AITLF TS1_AITHF TS1_RDY

TS1_ITEF : TS1_ITEF
bits : 0 - 0 (1 bit)

TS1_ITLF : TS1_ITLF
bits : 1 - 1 (1 bit)

TS1_ITHF : TS1_ITHF
bits : 2 - 2 (1 bit)

TS1_AITEF : TS1_AITEF
bits : 4 - 4 (1 bit)

TS1_AITLF : TS1_AITLF
bits : 5 - 5 (1 bit)

TS1_AITHF : TS1_AITHF
bits : 6 - 6 (1 bit)

TS1_RDY : TS1_RDY
bits : 15 - 15 (1 bit)


DTS_ITENR (ITENR)

Temperature sensor interrupt enable register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS_ITENR DTS_ITENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_ITEEN TS1_ITLEN TS1_ITHEN TS1_AITEEN TS1_AITLEN TS1_AITHEN

TS1_ITEEN : TS1_ITEEN
bits : 0 - 0 (1 bit)

TS1_ITLEN : TS1_ITLEN
bits : 1 - 1 (1 bit)

TS1_ITHEN : TS1_ITHEN
bits : 2 - 2 (1 bit)

TS1_AITEEN : TS1_AITEEN
bits : 4 - 4 (1 bit)

TS1_AITLEN : TS1_AITLEN
bits : 5 - 5 (1 bit)

TS1_AITHEN : TS1_AITHEN
bits : 6 - 6 (1 bit)


DTS_ICIFR (ICIFR)

DTS_ICIFR is the control register for the interrupt flags.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS_ICIFR DTS_ICIFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_CITEF TS1_CITLF TS1_CITHF TS1_CAITEF TS1_CAITLF TS1_CAITHF

TS1_CITEF : TS1_CITEF
bits : 0 - 0 (1 bit)

TS1_CITLF : TS1_CITLF
bits : 1 - 1 (1 bit)

TS1_CITHF : TS1_CITHF
bits : 2 - 2 (1 bit)

TS1_CAITEF : TS1_CAITEF
bits : 4 - 4 (1 bit)

TS1_CAITLF : TS1_CAITLF
bits : 5 - 5 (1 bit)

TS1_CAITHF : TS1_CAITHF
bits : 6 - 6 (1 bit)


DTS_OR (OR)

The DTS_OR contains general-purpose option bits.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTS_OR DTS_OR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS_Op0 TS_Op1 TS_Op2 TS_Op3 TS_Op4 TS_Op5 TS_Op6 TS_Op7 TS_Op8 TS_Op9 TS_Op10 TS_Op11 TS_Op12 TS_Op13 TS_Op14 TS_Op15 TS_Op16 TS_Op17 TS_Op18 TS_Op19 TS_Op20 TS_Op21 TS_Op22 TS_Op23 TS_Op24 TS_Op25 TS_Op26 TS_Op27 TS_Op28 TS_Op29 TS_Op30 TS_Op31

TS_Op0 : TS_Op0
bits : 0 - 0 (1 bit)

TS_Op1 : TS_Op1
bits : 1 - 1 (1 bit)

TS_Op2 : TS_Op2
bits : 2 - 2 (1 bit)

TS_Op3 : TS_Op3
bits : 3 - 3 (1 bit)

TS_Op4 : TS_Op4
bits : 4 - 4 (1 bit)

TS_Op5 : TS_Op5
bits : 5 - 5 (1 bit)

TS_Op6 : TS_Op6
bits : 6 - 6 (1 bit)

TS_Op7 : TS_Op7
bits : 7 - 7 (1 bit)

TS_Op8 : TS_Op8
bits : 8 - 8 (1 bit)

TS_Op9 : TS_Op9
bits : 9 - 9 (1 bit)

TS_Op10 : TS_Op10
bits : 10 - 10 (1 bit)

TS_Op11 : TS_Op11
bits : 11 - 11 (1 bit)

TS_Op12 : TS_Op12
bits : 12 - 12 (1 bit)

TS_Op13 : TS_Op13
bits : 13 - 13 (1 bit)

TS_Op14 : TS_Op14
bits : 14 - 14 (1 bit)

TS_Op15 : TS_Op15
bits : 15 - 15 (1 bit)

TS_Op16 : TS_Op16
bits : 16 - 16 (1 bit)

TS_Op17 : TS_Op17
bits : 17 - 17 (1 bit)

TS_Op18 : TS_Op18
bits : 18 - 18 (1 bit)

TS_Op19 : TS_Op19
bits : 19 - 19 (1 bit)

TS_Op20 : TS_Op20
bits : 20 - 20 (1 bit)

TS_Op21 : TS_Op21
bits : 21 - 21 (1 bit)

TS_Op22 : TS_Op22
bits : 22 - 22 (1 bit)

TS_Op23 : TS_Op23
bits : 23 - 23 (1 bit)

TS_Op24 : TS_Op24
bits : 24 - 24 (1 bit)

TS_Op25 : TS_Op25
bits : 25 - 25 (1 bit)

TS_Op26 : TS_Op26
bits : 26 - 26 (1 bit)

TS_Op27 : TS_Op27
bits : 27 - 27 (1 bit)

TS_Op28 : TS_Op28
bits : 28 - 28 (1 bit)

TS_Op29 : TS_Op29
bits : 29 - 29 (1 bit)

TS_Op30 : TS_Op30
bits : 30 - 30 (1 bit)

TS_Op31 : TS_Op31
bits : 31 - 31 (1 bit)


DTS_T0VALR1 (T0VALR1)

DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTS_T0VALR1 DTS_T0VALR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS1_FMT0 TS1_T0

TS1_FMT0 : TS1_FMT0
bits : 0 - 15 (16 bit)

TS1_T0 : TS1_T0
bits : 16 - 17 (2 bit)



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