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Ethernet

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ETH_MTLOMR

ETH_MTLTxQ0OMR

ETH_MTLTxQ0UR

ETH_MTLTxQ0DR

ETH_MTLTxQ0ESR

ETH_MTLQ0ICSR

ETH_MTLRxQ0OMR

ETH_MTLRxQ0MPOCR

ETH_MTLRxQ0DR

ETH_MTLRxQ0CR

ETH_MTLTxQ1OMR

ETH_MTLTxQ1UR

ETH_MTLTxQ1DR

ETH_MTLTxQ1ECR

ETH_MTLTxQ1ESR

ETH_MTLTxQ1QWR

ETH_MTLTxQ1SSCR

ETH_MTLTxQ1HCR

ETH_MTLTxQ1LCR

ETH_MTLQ1ICSR

ETH_MTLRxQ1OMR

ETH_MTLRxQ1MPOCR

ETH_MTLRxQ1DR

ETH_MTLRxQ1CR

ETH_MTLISR


ETH_MTLOMR

The Operating Mode register establishes the Transmit and Receive operating modes and commands.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLOMR ETH_MTLOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTXSTS RAA SCHALG CNTPRST CNTCLR

DTXSTS : DTXSTS
bits : 1 - 1 (1 bit)
access : read-write

RAA : RAA
bits : 2 - 2 (1 bit)
access : read-write

SCHALG : SCHALG
bits : 5 - 6 (2 bit)
access : read-write

CNTPRST : CNTPRST
bits : 8 - 8 (1 bit)
access : read-write

CNTCLR : CNTCLR
bits : 9 - 9 (1 bit)
access : read-write


ETH_MTLTxQ0OMR

Tx queue 0 operating mode Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ0OMR ETH_MTLTxQ0OMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTQ TSF TXQEN TTC TQS

FTQ : FTQ
bits : 0 - 0 (1 bit)
access : read-write

TSF : TSF
bits : 1 - 1 (1 bit)
access : read-write

TXQEN : TXQEN
bits : 2 - 3 (2 bit)
access : read-write

TTC : TTC
bits : 4 - 5 (2 bit)
access : read-write

TQS : TQS
bits : 16 - 24 (9 bit)
access : read-write


ETH_MTLTxQ0UR

Tx queue 0 underflow register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ0UR ETH_MTLTxQ0UR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFFRMCNT UFCNTOVF

UFFRMCNT : UFFRMCNT
bits : 0 - 10 (11 bit)
access : read-only

UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only


ETH_MTLTxQ0DR

Tx queue 0 underflow register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ0DR ETH_MTLTxQ0DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXQPAUSED TRCSTS TWCSTS TXQSTS TXSTSFSTS PTXQ STXSTSF

TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)
access : read-only

TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)
access : read-only

TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)
access : read-only

TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)
access : read-only

TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)
access : read-only

PTXQ : PTXQ
bits : 16 - 18 (3 bit)
access : read-only

STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)
access : read-only


ETH_MTLTxQ0ESR

Tx queue x ETS status Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ0ESR ETH_MTLTxQ0ESR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABS

ABS : ABS
bits : 0 - 23 (24 bit)
access : read-only


ETH_MTLQ0ICSR

Queue 0 interrupt control status Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLQ0ICSR ETH_MTLQ0ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXUNFIS ABPSIS TXUIE ABPSIE RXOVFIS RXOIE

TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)
access : read-only

ABPSIS : ABPSIS
bits : 1 - 1 (1 bit)
access : read-write

TXUIE : TXUIE
bits : 8 - 8 (1 bit)
access : read-write

ABPSIE : ABPSIE
bits : 9 - 9 (1 bit)
access : read-write

RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)
access : read-write

RXOIE : RXOIE
bits : 24 - 24 (1 bit)
access : read-write


ETH_MTLRxQ0OMR

Rx queue 0 operating mode register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ0OMR ETH_MTLRxQ0OMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC FUP FEP RSF DIS_TCP_EF EHFC RFA RFD RQS

RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write

FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write

FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write

RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write

DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write

EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write

RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write

RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write

RQS : RQS
bits : 20 - 23 (4 bit)
access : read-only


ETH_MTLRxQ0MPOCR

Rx queue 0 missed packet and overflow counter register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ0MPOCR ETH_MTLRxQ0MPOCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFPKTCNT OVFCNTOVF MISPKTCNT MISCNTOVF

OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)
access : read-only

OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only

MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)
access : read-only

MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)
access : read-only


ETH_MTLRxQ0DR

Rx queue i debug register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ0DR ETH_MTLRxQ0DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWCSTS RRCSTS RXQSTS PRXQ

RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)
access : read-only

RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)
access : read-only

RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)
access : read-only

PRXQ : PRXQ
bits : 16 - 29 (14 bit)
access : read-only


ETH_MTLRxQ0CR

Rx queue 0 control register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ0CR ETH_MTLRxQ0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXQ_WEGT RXQ_FRM_ARBIT

RXQ_WEGT : RXQ_WEGT
bits : 0 - 2 (3 bit)
access : read-only

RXQ_FRM_ARBIT : RXQ_FRM_ARBIT
bits : 3 - 3 (1 bit)
access : read-only


ETH_MTLTxQ1OMR

Tx queue 1 operating mode Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1OMR ETH_MTLTxQ1OMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTQ TSF TXQEN TTC TQS

FTQ : FTQ
bits : 0 - 0 (1 bit)
access : read-write

TSF : TSF
bits : 1 - 1 (1 bit)
access : read-write

TXQEN : TXQEN
bits : 2 - 3 (2 bit)
access : read-write

TTC : TTC
bits : 4 - 5 (2 bit)
access : read-write

TQS : TQS
bits : 16 - 24 (9 bit)
access : read-write


ETH_MTLTxQ1UR

Tx queue 1 underflow register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1UR ETH_MTLTxQ1UR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFFRMCNT UFCNTOVF

UFFRMCNT : UFFRMCNT
bits : 0 - 10 (11 bit)
access : read-only

UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only


ETH_MTLTxQ1DR

Tx queue 1 underflow register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1DR ETH_MTLTxQ1DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXQPAUSED TRCSTS TWCSTS TXQSTS TXSTSFSTS PTXQ STXSTSF

TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)
access : read-only

TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)
access : read-only

TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)
access : read-only

TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)
access : read-only

TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)
access : read-only

PTXQ : PTXQ
bits : 16 - 18 (3 bit)
access : read-only

STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)
access : read-only


ETH_MTLTxQ1ECR

The Queue ETS Control register controls the enhanced transmission selection operation.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1ECR ETH_MTLTxQ1ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVALG CC SLC

AVALG : AVALG
bits : 2 - 2 (1 bit)
access : read-write

CC : CC
bits : 3 - 3 (1 bit)
access : read-write

SLC : SLC
bits : 4 - 6 (3 bit)
access : read-write


ETH_MTLTxQ1ESR

Tx queue x ETS status Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1ESR ETH_MTLTxQ1ESR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABS

ABS : ABS
bits : 0 - 23 (24 bit)
access : read-only


ETH_MTLTxQ1QWR

This register provides the average traffic transmitted on queue 1.
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1QWR ETH_MTLTxQ1QWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISCQW

ISCQW : ISCQW
bits : 0 - 20 (21 bit)
access : read-write


ETH_MTLTxQ1SSCR

The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1SSCR ETH_MTLTxQ1SSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSC

SSC : SSC
bits : 0 - 13 (14 bit)
access : read-write


ETH_MTLTxQ1HCR

The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue.
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1HCR ETH_MTLTxQ1HCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HC

HC : HC
bits : 0 - 28 (29 bit)
access : read-write


ETH_MTLTxQ1LCR

The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue.
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLTxQ1LCR ETH_MTLTxQ1LCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LC

LC : LC
bits : 0 - 28 (29 bit)
access : read-write


ETH_MTLQ1ICSR

Queue 1 interrupt control status Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLQ1ICSR ETH_MTLQ1ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXUNFIS ABPSIS TXUIE ABPSIE RXOVFIS RXOIE

TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)
access : read-only

ABPSIS : ABPSIS
bits : 1 - 1 (1 bit)
access : read-write

TXUIE : TXUIE
bits : 8 - 8 (1 bit)
access : read-write

ABPSIE : ABPSIE
bits : 9 - 9 (1 bit)
access : read-write

RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)
access : read-write

RXOIE : RXOIE
bits : 24 - 24 (1 bit)
access : read-write


ETH_MTLRxQ1OMR

Rx queue 1 operating mode register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ1OMR ETH_MTLRxQ1OMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC FUP FEP RSF DIS_TCP_EF EHFC RFA RFD RQS

RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write

FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write

FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write

RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write

DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write

EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write

RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write

RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write

RQS : RQS
bits : 20 - 23 (4 bit)
access : read-only


ETH_MTLRxQ1MPOCR

Rx queue 1 missed packet and overflow counter register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ1MPOCR ETH_MTLRxQ1MPOCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVFPKTCNT OVFCNTOVF MISPKTCNT MISCNTOVF

OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)
access : read-only

OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only

MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)
access : read-only

MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)
access : read-only


ETH_MTLRxQ1DR

Rx queue i debug register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ1DR ETH_MTLRxQ1DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWCSTS RRCSTS RXQSTS PRXQ

RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)
access : read-only

RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)
access : read-only

RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)
access : read-only

PRXQ : PRXQ
bits : 16 - 29 (14 bit)
access : read-only


ETH_MTLRxQ1CR

Rx queue 1 control register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLRxQ1CR ETH_MTLRxQ1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXQ_WEGT RXQ_FRM_ARBIT

RXQ_WEGT : RXQ_WEGT
bits : 0 - 2 (3 bit)
access : read-only

RXQ_FRM_ARBIT : RXQ_FRM_ARBIT
bits : 3 - 3 (1 bit)
access : read-only


ETH_MTLISR

The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_MTLISR ETH_MTLISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q0IS Q1IS

Q0IS : Q0IS
bits : 0 - 0 (1 bit)
access : read-only

Q1IS : Q1IS
bits : 1 - 1 (1 bit)
access : read-only



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