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Ethernet

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ETH_DMAMR

ETH_DMAC0CR

ETH_DMAC0TxCR

ETH_DMAC0RxCR

ETH_DMAC0TxDLAR

ETH_DMAC0RxDLAR

ETH_DMAC0TxDTPR

ETH_DMAC0RxDTPR

ETH_DMAC0TxRLR

ETH_DMAC0RxRLR

ETH_DMACIER (ETH_DMAC0IER)

ETH_DMAC0RxIWTR

ETH_DMAC0SFCSR

ETH_DMAC0CATxDR

ETH_DMAC0CARxDR

ETH_DMAC0CATxBR

ETH_DMACCARxBR (ETH_DMAC0CARxBR)

ETH_DMAC0SR

ETH_DMAC0MFCR

ETH_DMAC1CR

ETH_DMAC1TxCR

ETH_DMAC1TxDLAR

ETH_DMAC1TxDTPR

ETH_DMAC1TxRLR

ETH_DMAC1IER

ETH_DMAC1SFCSR

ETH_DMAC1CATxDR

ETH_DMAC1CATxBR

ETH_DMAC1SR

ETH_DMAC1MFCR

ETH_DMAA4TxACR

ETH_DMAA4RxACR

ETH_DMAA4DACR

ETH_DMASBMR

ETH_DMAISR

ETH_DMADSR


ETH_DMAMR

DMA mode register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAMR ETH_DMAMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR TAA TXPR PR INTM

SWR : Software Reset
bits : 0 - 0 (1 bit)

TAA : TAA
bits : 2 - 4 (3 bit)

TXPR : Transmit priority
bits : 11 - 11 (1 bit)

PR : Priority ratio
bits : 12 - 14 (3 bit)

INTM : Interrupt Mode
bits : 16 - 17 (2 bit)


ETH_DMAC0CR

Channel 0 control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0CR ETH_DMAC0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSS PBLX8 DSL

MSS : MSS
bits : 0 - 13 (14 bit)

PBLX8 : PBLX8
bits : 16 - 16 (1 bit)

DSL : DSL
bits : 18 - 20 (3 bit)


ETH_DMAC0TxCR

Channel 0 transmit control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0TxCR ETH_DMAC0TxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST TCW OSF TSE TXPBL TQOS

ST : ST
bits : 0 - 0 (1 bit)

TCW : TCW
bits : 1 - 3 (3 bit)

OSF : OSF
bits : 4 - 4 (1 bit)

TSE : TSE
bits : 12 - 12 (1 bit)

TXPBL : TXPBL
bits : 16 - 21 (6 bit)

TQOS : TQOS
bits : 24 - 27 (4 bit)


ETH_DMAC0RxCR

Channel receive control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0RxCR ETH_DMAC0RxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR RBSZ RXPBL RQOS RPF

SR : Start or Stop Receive Command
bits : 0 - 0 (1 bit)

RBSZ : Receive Buffer size
bits : 1 - 14 (14 bit)

RXPBL : RXPBL
bits : 16 - 21 (6 bit)

RQOS : RQOS
bits : 24 - 27 (4 bit)

RPF : DMA Rx Channel Packet Flush
bits : 31 - 31 (1 bit)


ETH_DMAC0TxDLAR

Channel i Tx descriptor list address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0TxDLAR ETH_DMAC0TxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDESLA

TDESLA : Start of Transmit List
bits : 3 - 31 (29 bit)


ETH_DMAC0RxDLAR

Channel Rx descriptor list address register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0RxDLAR ETH_DMAC0RxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDESLA

RDESLA : Start of Receive List
bits : 3 - 31 (29 bit)


ETH_DMAC0TxDTPR

Channel Tx descriptor tail pointer register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0TxDTPR ETH_DMAC0TxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDT

TDT : Transmit Descriptor Tail Pointer
bits : 3 - 31 (29 bit)


ETH_DMAC0RxDTPR

Channel Rx descriptor tail pointer register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0RxDTPR ETH_DMAC0RxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDT

RDT : Receive Descriptor Tail Pointer
bits : 3 - 31 (29 bit)


ETH_DMAC0TxRLR

Channel Tx descriptor ring length register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0TxRLR ETH_DMAC0TxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRL

TDRL : Transmit Descriptor Ring Length
bits : 0 - 9 (10 bit)


ETH_DMAC0RxRLR

Channel Rx descriptor ring length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0RxRLR ETH_DMAC0RxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRL

RDRL : Receive Descriptor Ring Length
bits : 0 - 9 (10 bit)


ETH_DMACIER (ETH_DMAC0IER)

Channel interrupt enable register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMACIER ETH_DMACIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TXSE TBUE RIE RBUE RSE RWTE ETIE ERIE FBEE CDEE AIE NIE

TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)

TXSE : Transmit Stopped Enable
bits : 1 - 1 (1 bit)

TBUE : Transmit Buffer Unavailable Enable
bits : 2 - 2 (1 bit)

RIE : Receive Interrupt Enable
bits : 6 - 6 (1 bit)

RBUE : Receive Buffer Unavailable Enable
bits : 7 - 7 (1 bit)

RSE : Receive Stopped Enable
bits : 8 - 8 (1 bit)

RWTE : Receive Watchdog Timeout Enable
bits : 9 - 9 (1 bit)

ETIE : Early Transmit Interrupt Enable
bits : 10 - 10 (1 bit)

ERIE : Early Receive Interrupt Enable
bits : 11 - 11 (1 bit)

FBEE : Fatal Bus Error Enable
bits : 12 - 12 (1 bit)

CDEE : Context Descriptor Error Enable
bits : 13 - 13 (1 bit)

AIE : Abnormal Interrupt Summary Enable
bits : 14 - 14 (1 bit)

NIE : Normal Interrupt Summary Enable
bits : 15 - 15 (1 bit)


ETH_DMAC0RxIWTR

Channel Rx interrupt watchdog timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0RxIWTR ETH_DMAC0RxIWTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWT

RWT : Receive Interrupt Watchdog Timer Count
bits : 0 - 7 (8 bit)


ETH_DMAC0SFCSR

Channel i slot function control status register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0SFCSR ETH_DMAC0SFCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESC ASC RSN

ESC : ESC
bits : 0 - 0 (1 bit)

ASC : ASC
bits : 1 - 1 (1 bit)

RSN : RSN
bits : 16 - 19 (4 bit)


ETH_DMAC0CATxDR

Channel current application transmit descriptor register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0CATxDR ETH_DMAC0CATxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTDESAPTR

CURTDESAPTR : Application Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)


ETH_DMAC0CARxDR

Channel 0 current application receive descriptor register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : DMAC1CATxDR
reset_Mask : 0x0

ETH_DMAC0CARxDR ETH_DMAC0CARxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRDESAPTR

CURRDESAPTR : Application Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)


ETH_DMAC0CATxBR

Channel 0 current application transmit buffer register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0CATxBR ETH_DMAC0CATxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTBUFAPTR

CURTBUFAPTR : Application Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)


ETH_DMACCARxBR (ETH_DMAC0CARxBR)

Channel current application receive buffer register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMACCARxBR ETH_DMACCARxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRBUFAPTR

CURRBUFAPTR : Application Receive Buffer Address Pointer
bits : 0 - 31 (32 bit)


ETH_DMAC0SR

Channel status register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0SR ETH_DMAC0SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI TPS TBU RI RBU RPS RWT ETI ERI FBE CDE AIS NIS TEB REB

TI : Transmit Interrupt
bits : 0 - 0 (1 bit)

TPS : Transmit Process Stopped
bits : 1 - 1 (1 bit)

TBU : Transmit Buffer Unavailable
bits : 2 - 2 (1 bit)

RI : Receive Interrupt
bits : 6 - 6 (1 bit)

RBU : Receive Buffer Unavailable
bits : 7 - 7 (1 bit)

RPS : Receive Process Stopped
bits : 8 - 8 (1 bit)

RWT : Receive Watchdog Timeout
bits : 9 - 9 (1 bit)

ETI : Early Transmit Interrupt
bits : 10 - 10 (1 bit)

ERI : Early Receive Interrupt
bits : 11 - 11 (1 bit)

FBE : Fatal Bus Error
bits : 12 - 12 (1 bit)

CDE : Context Descriptor Error
bits : 13 - 13 (1 bit)

AIS : Abnormal Interrupt Summary
bits : 14 - 14 (1 bit)

NIS : Normal Interrupt Summary
bits : 15 - 15 (1 bit)

TEB : Tx DMA Error Bits
bits : 16 - 18 (3 bit)

REB : Rx DMA Error Bits
bits : 19 - 21 (3 bit)


ETH_DMAC0MFCR

Channel missed frame count register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC0MFCR ETH_DMAC0MFCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFC MFCO

MFC : Dropped Packet Counters
bits : 0 - 10 (11 bit)

MFCO : Overflow status of the MFC Counter
bits : 15 - 15 (1 bit)


ETH_DMAC1CR

Channel 1 control register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1CR ETH_DMAC1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSS PBLX8 DSL

MSS : MSS
bits : 0 - 13 (14 bit)

PBLX8 : PBLX8
bits : 16 - 16 (1 bit)

DSL : DSL
bits : 18 - 20 (3 bit)


ETH_DMAC1TxCR

Channel 1 transmit control register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1TxCR ETH_DMAC1TxCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST TCW OSF TSE TXPBL TQOS

ST : ST
bits : 0 - 0 (1 bit)

TCW : TCW
bits : 1 - 3 (3 bit)

OSF : OSF
bits : 4 - 4 (1 bit)

TSE : TSE
bits : 12 - 12 (1 bit)

TXPBL : TXPBL
bits : 16 - 21 (6 bit)

TQOS : TQOS
bits : 24 - 27 (4 bit)


ETH_DMAC1TxDLAR

Channel i Tx descriptor list address register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1TxDLAR ETH_DMAC1TxDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDESLA

TDESLA : Start of Transmit List
bits : 3 - 31 (29 bit)


ETH_DMAC1TxDTPR

Channel Tx descriptor tail pointer register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1TxDTPR ETH_DMAC1TxDTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDT

TDT : Transmit Descriptor Tail Pointer
bits : 3 - 31 (29 bit)


ETH_DMAC1TxRLR

Channel Tx descriptor ring length register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1TxRLR ETH_DMAC1TxRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRL

TDRL : Transmit Descriptor Ring Length
bits : 0 - 9 (10 bit)


ETH_DMAC1IER

Channel interrupt enable register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1IER ETH_DMAC1IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TXSE TBUE RIE RBUE RSE RWTE ETIE ERIE FBEE CDEE AIE NIE

TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)

TXSE : Transmit Stopped Enable
bits : 1 - 1 (1 bit)

TBUE : Transmit Buffer Unavailable Enable
bits : 2 - 2 (1 bit)

RIE : Receive Interrupt Enable
bits : 6 - 6 (1 bit)

RBUE : Receive Buffer Unavailable Enable
bits : 7 - 7 (1 bit)

RSE : Receive Stopped Enable
bits : 8 - 8 (1 bit)

RWTE : Receive Watchdog Timeout Enable
bits : 9 - 9 (1 bit)

ETIE : Early Transmit Interrupt Enable
bits : 10 - 10 (1 bit)

ERIE : Early Receive Interrupt Enable
bits : 11 - 11 (1 bit)

FBEE : Fatal Bus Error Enable
bits : 12 - 12 (1 bit)

CDEE : Context Descriptor Error Enable
bits : 13 - 13 (1 bit)

AIE : Abnormal Interrupt Summary Enable
bits : 14 - 14 (1 bit)

NIE : Normal Interrupt Summary Enable
bits : 15 - 15 (1 bit)


ETH_DMAC1SFCSR

Channel i slot function control status register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1SFCSR ETH_DMAC1SFCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESC ASC RSN

ESC : ESC
bits : 0 - 0 (1 bit)

ASC : ASC
bits : 1 - 1 (1 bit)

RSN : RSN
bits : 16 - 19 (4 bit)


ETH_DMAC1CATxDR

Channel current application transmit descriptor register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1CATxDR ETH_DMAC1CATxDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTDESAPTR

CURTDESAPTR : Application Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)


ETH_DMAC1CATxBR

Channel 0 current application transmit buffer register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1CATxBR ETH_DMAC1CATxBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTBUFAPTR

CURTBUFAPTR : Application Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)


ETH_DMAC1SR

Channel status register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1SR ETH_DMAC1SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI TPS TBU RI RBU RPS RWT ETI ERI FBE CDE AIS NIS TEB REB

TI : Transmit Interrupt
bits : 0 - 0 (1 bit)

TPS : Transmit Process Stopped
bits : 1 - 1 (1 bit)

TBU : Transmit Buffer Unavailable
bits : 2 - 2 (1 bit)

RI : Receive Interrupt
bits : 6 - 6 (1 bit)

RBU : Receive Buffer Unavailable
bits : 7 - 7 (1 bit)

RPS : Receive Process Stopped
bits : 8 - 8 (1 bit)

RWT : Receive Watchdog Timeout
bits : 9 - 9 (1 bit)

ETI : Early Transmit Interrupt
bits : 10 - 10 (1 bit)

ERI : Early Receive Interrupt
bits : 11 - 11 (1 bit)

FBE : Fatal Bus Error
bits : 12 - 12 (1 bit)

CDE : Context Descriptor Error
bits : 13 - 13 (1 bit)

AIS : Abnormal Interrupt Summary
bits : 14 - 14 (1 bit)

NIS : Normal Interrupt Summary
bits : 15 - 15 (1 bit)

TEB : Tx DMA Error Bits
bits : 16 - 18 (3 bit)

REB : Rx DMA Error Bits
bits : 19 - 21 (3 bit)


ETH_DMAC1MFCR

Channel missed frame count register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAC1MFCR ETH_DMAC1MFCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFC MFCO

MFC : Dropped Packet Counters
bits : 0 - 10 (11 bit)

MFCO : Overflow status of the MFC Counter
bits : 15 - 15 (1 bit)


ETH_DMAA4TxACR

AXI4 transmit channel ACE control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAA4TxACR ETH_DMAA4TxACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDRC TEC THC

TDRC : TDRC
bits : 0 - 3 (4 bit)

TEC : TEC
bits : 8 - 11 (4 bit)

THC : THC
bits : 16 - 19 (4 bit)


ETH_DMAA4RxACR

AXI4 receive channel ACE control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAA4RxACR ETH_DMAA4RxACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDWC RPC RHC RDC

RDWC : RDWC
bits : 0 - 3 (4 bit)

RPC : RPC
bits : 8 - 11 (4 bit)

RHC : RHC
bits : 16 - 19 (4 bit)

RDC : RDC
bits : 24 - 25 (2 bit)


ETH_DMAA4DACR

AXI4 descriptor ACE control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAA4DACR ETH_DMAA4DACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDWC TDWD RDRC RDP WRP

TDWC : TDWC
bits : 0 - 3 (4 bit)

TDWD : TDWD
bits : 4 - 5 (2 bit)

RDRC : RDRC
bits : 8 - 11 (4 bit)

RDP : RDP
bits : 16 - 18 (3 bit)

WRP : WRP
bits : 20 - 22 (3 bit)


ETH_DMASBMR

System bus mode register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_DMASBMR ETH_DMASBMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB BLEN4 BLEN8 BLEN16 BLEN32 BLEN64 BLEN128 BLEN256 AAL ONEKBBE RD_OSR_LMT WR_OSR_LMT LPI_XIT_PKT EN_LPI

FB : Fixed Burst Length
bits : 0 - 0 (1 bit)

BLEN4 : BLEN4
bits : 1 - 1 (1 bit)

BLEN8 : BLEN8
bits : 2 - 2 (1 bit)

BLEN16 : BLEN16
bits : 3 - 3 (1 bit)

BLEN32 : BLEN32
bits : 4 - 4 (1 bit)

BLEN64 : BLEN64
bits : 5 - 5 (1 bit)

BLEN128 : BLEN128
bits : 6 - 6 (1 bit)

BLEN256 : BLEN256
bits : 7 - 7 (1 bit)

AAL : Address-Aligned Beats
bits : 12 - 12 (1 bit)

ONEKBBE : ONEKBBE
bits : 13 - 13 (1 bit)

RD_OSR_LMT : RD_OSR_LMT
bits : 16 - 17 (2 bit)

WR_OSR_LMT : WR_OSR_LMT
bits : 24 - 25 (2 bit)

LPI_XIT_PKT : LPI_XIT_PKT
bits : 30 - 30 (1 bit)

EN_LPI : EN_LPI
bits : 31 - 31 (1 bit)


ETH_DMAISR

Interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMAISR ETH_DMAISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC0IS DC1IS MTLIS MACIS

DC0IS : DMA Channel Interrupt Status
bits : 0 - 0 (1 bit)

DC1IS : DC1IS
bits : 1 - 1 (1 bit)

MTLIS : MTL Interrupt Status
bits : 16 - 16 (1 bit)

MACIS : MAC Interrupt Status
bits : 17 - 17 (1 bit)


ETH_DMADSR

Debug status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETH_DMADSR ETH_DMADSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AXWHSTS AXRHSTS RPS0 TPS0 RPS1 TPS1

AXWHSTS : AHB Master Write Channel
bits : 0 - 0 (1 bit)

AXRHSTS : AXRHSTS
bits : 1 - 1 (1 bit)

RPS0 : RPS0
bits : 8 - 11 (4 bit)

TPS0 : TPS0
bits : 12 - 15 (4 bit)

RPS1 : RPS1
bits : 16 - 19 (4 bit)

TPS1 : TPS1
bits : 20 - 23 (4 bit)



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