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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

EXTI_RTSR1 (RTSR1)

EXTI_FPR1 (FPR1)

EXTI_TZENR1 (TZENR1)

EXTI_RTSR2 (RTSR2)

EXTI_FTSR2 (FTSR2)

EXTI_SWIER2 (SWIER2)

EXTI_RPR2 (RPR2)

EXTI_FPR2 (FPR2)

EXTI_TZENR2 (TZENR2)

EXTI_HWCFGR13 (HWCFGR13)

EXTI_HWCFGR12 (HWCFGR12)

EXTI_HWCFGR11 (HWCFGR11)

EXTI_HWCFGR10 (HWCFGR10)

EXTI_HWCFGR9 (HWCFGR9)

EXTI_HWCFGR8 (HWCFGR8)

EXTI_HWCFGR7 (HWCFGR7)

EXTI_HWCFGR6 (HWCFGR6)

EXTI_HWCFGR5 (HWCFGR5)

EXTI_HWCFGR4 (HWCFGR4)

EXTI_HWCFGR3 (HWCFGR3)

EXTI_HWCFGR2 (HWCFGR2)

EXTI_HWCFGR1 (HWCFGR1)

EXTI_VERR (VERR)

EXTI_IPIDR (IPIDR)

EXTI_SIDR (SIDR)

EXTI_FTSR1 (FTSR1)

EXTI_RTSR3 (RTSR3)

EXTI_FTSR3 (FTSR3)

EXTI_SWIER3 (SWIER3)

EXTI_RPR3 (RPR3)

EXTI_FPR3 (FPR3)

EXTI_TZENR3 (TZENR3)

EXTI_EXTICR1 (EXTICR1)

EXTI_EXTICR2 (EXTICR2)

EXTI_EXTICR3 (EXTICR3)

EXTI_EXTICR4 (EXTICR4)

EXTI_SWIER1 (SWIER1)

EXTI_IMR1 (IMR1)

EXTI_EMR1 (EMR1)

EXTI_IMR2 (IMR2)

EXTI_EMR2 (EMR2)

EXTI_IMR3 (IMR3)

EXTI_EMR3 (EMR3)

EXTI_RPR1 (RPR1)

EXTI_C2IMR1 (C2IMR1)

EXTI_C2EMR1 (C2EMR1)

EXTI_C2IMR2 (C2IMR2)

EXTI_C2EMR2 (C2EMR2)

EXTI_C2IMR3 (C2IMR3)

EXTI_C2EMR3 (C2EMR3)


EXTI_RTSR1 (RTSR1)

Contains only register bits for configurable events.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_RTSR1 EXTI_RTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT0 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16

RT0 : RT0
bits : 0 - 0 (1 bit)

RT1 : RT1
bits : 1 - 1 (1 bit)

RT2 : RT2
bits : 2 - 2 (1 bit)

RT3 : RT3
bits : 3 - 3 (1 bit)

RT4 : RT4
bits : 4 - 4 (1 bit)

RT5 : RT5
bits : 5 - 5 (1 bit)

RT6 : RT6
bits : 6 - 6 (1 bit)

RT7 : RT7
bits : 7 - 7 (1 bit)

RT8 : RT8
bits : 8 - 8 (1 bit)

RT9 : RT9
bits : 9 - 9 (1 bit)

RT10 : RT10
bits : 10 - 10 (1 bit)

RT11 : RT11
bits : 11 - 11 (1 bit)

RT12 : RT12
bits : 12 - 12 (1 bit)

RT13 : RT13
bits : 13 - 13 (1 bit)

RT14 : RT14
bits : 14 - 14 (1 bit)

RT15 : RT15
bits : 15 - 15 (1 bit)

RT16 : RT16
bits : 16 - 16 (1 bit)


EXTI_FPR1 (FPR1)

Contains only register bits for configurable events.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_FPR1 EXTI_FPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPIF0 FPIF1 FPIF2 FPIF3 FPIF4 FPIF5 FPIF6 FPIF7 FPIF8 FPIF9 FPIF10 FPIF11 FPIF12 FPIF13 FPIF14 FPIF15 FPIF16

FPIF0 : FPIF0
bits : 0 - 0 (1 bit)

FPIF1 : FPIF1
bits : 1 - 1 (1 bit)

FPIF2 : FPIF2
bits : 2 - 2 (1 bit)

FPIF3 : FPIF3
bits : 3 - 3 (1 bit)

FPIF4 : FPIF4
bits : 4 - 4 (1 bit)

FPIF5 : FPIF5
bits : 5 - 5 (1 bit)

FPIF6 : FPIF6
bits : 6 - 6 (1 bit)

FPIF7 : FPIF7
bits : 7 - 7 (1 bit)

FPIF8 : FPIF8
bits : 8 - 8 (1 bit)

FPIF9 : FPIF9
bits : 9 - 9 (1 bit)

FPIF10 : FPIF10
bits : 10 - 10 (1 bit)

FPIF11 : FPIF11
bits : 11 - 11 (1 bit)

FPIF12 : FPIF12
bits : 12 - 12 (1 bit)

FPIF13 : FPIF13
bits : 13 - 13 (1 bit)

FPIF14 : FPIF14
bits : 14 - 14 (1 bit)

FPIF15 : FPIF15
bits : 15 - 15 (1 bit)

FPIF16 : FPIF16
bits : 16 - 16 (1 bit)


EXTI_TZENR1 (TZENR1)

This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_TZENR1 EXTI_TZENR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZEN0 TZEN1 TZEN2 TZEN3 TZEN4 TZEN5 TZEN6 TZEN7 TZEN8 TZEN9 TZEN10 TZEN11 TZEN12 TZEN13 TZEN14 TZEN15 TZEN17 TZEN18 TZEN19 TZEN24 TZEN26

TZEN0 : TZEN0
bits : 0 - 0 (1 bit)

TZEN1 : TZEN1
bits : 1 - 1 (1 bit)

TZEN2 : TZEN2
bits : 2 - 2 (1 bit)

TZEN3 : TZEN3
bits : 3 - 3 (1 bit)

TZEN4 : TZEN4
bits : 4 - 4 (1 bit)

TZEN5 : TZEN5
bits : 5 - 5 (1 bit)

TZEN6 : TZEN6
bits : 6 - 6 (1 bit)

TZEN7 : TZEN7
bits : 7 - 7 (1 bit)

TZEN8 : TZEN8
bits : 8 - 8 (1 bit)

TZEN9 : TZEN9
bits : 9 - 9 (1 bit)

TZEN10 : TZEN10
bits : 10 - 10 (1 bit)

TZEN11 : TZEN11
bits : 11 - 11 (1 bit)

TZEN12 : TZEN12
bits : 12 - 12 (1 bit)

TZEN13 : TZEN13
bits : 13 - 13 (1 bit)

TZEN14 : TZEN14
bits : 14 - 14 (1 bit)

TZEN15 : TZEN15
bits : 15 - 15 (1 bit)

TZEN17 : TZEN17
bits : 17 - 17 (1 bit)

TZEN18 : TZEN18
bits : 18 - 18 (1 bit)

TZEN19 : TZEN19
bits : 19 - 19 (1 bit)

TZEN24 : TZEN24
bits : 24 - 24 (1 bit)

TZEN26 : TZEN26
bits : 26 - 26 (1 bit)


EXTI_RTSR2 (RTSR2)

Contains only register bits for configurable events.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_RTSR2 EXTI_RTSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_FTSR2 (FTSR2)

Contains only register bits for configurable events.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_FTSR2 EXTI_FTSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_SWIER2 (SWIER2)

Contains only register bits for configurable events.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_SWIER2 EXTI_SWIER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_RPR2 (RPR2)

Contains only register bits for configurable events.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_RPR2 EXTI_RPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_FPR2 (FPR2)

Contains only register bits for configurable events.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_FPR2 EXTI_FPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_TZENR2 (TZENR2)

This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_TZENR2 EXTI_TZENR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZEN41 TZEN54 TZEN55 TZEN56 TZEN57 TZEN58 TZEN59 TZEN60

TZEN41 : TZEN41
bits : 9 - 9 (1 bit)

TZEN54 : TZEN54
bits : 22 - 22 (1 bit)

TZEN55 : TZEN55
bits : 23 - 23 (1 bit)

TZEN56 : TZEN56
bits : 24 - 24 (1 bit)

TZEN57 : TZEN57
bits : 25 - 25 (1 bit)

TZEN58 : TZEN58
bits : 26 - 26 (1 bit)

TZEN59 : TZEN59
bits : 27 - 27 (1 bit)

TZEN60 : TZEN60
bits : 28 - 28 (1 bit)


EXTI_HWCFGR13 (HWCFGR13)

EXTI hardware configuration register 13
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR13 EXTI_HWCFGR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZ

TZ : TZ
bits : 0 - 31 (32 bit)


EXTI_HWCFGR12 (HWCFGR12)

EXTI hardware configuration register 12
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR12 EXTI_HWCFGR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZ

TZ : TZ
bits : 0 - 31 (32 bit)


EXTI_HWCFGR11 (HWCFGR11)

EXTI hardware configuration register 11
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR11 EXTI_HWCFGR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZ

TZ : TZ
bits : 0 - 31 (32 bit)


EXTI_HWCFGR10 (HWCFGR10)

EXTI hardware configuration register 10
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR10 EXTI_HWCFGR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_HWCFGR9 (HWCFGR9)

EXTI hardware configuration register 9
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR9 EXTI_HWCFGR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_HWCFGR8 (HWCFGR8)

EXTI hardware configuration register 8
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR8 EXTI_HWCFGR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_HWCFGR7 (HWCFGR7)

EXTI hardware configuration register 7
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR7 EXTI_HWCFGR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUEVENT

CPUEVENT : CPUEVENT
bits : 0 - 31 (32 bit)


EXTI_HWCFGR6 (HWCFGR6)

EXTI hardware configuration register 6
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR6 EXTI_HWCFGR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUEVENT

CPUEVENT : CPUEVENT
bits : 0 - 31 (32 bit)


EXTI_HWCFGR5 (HWCFGR5)

EXTI hardware configuration register 5
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR5 EXTI_HWCFGR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUEVENT

CPUEVENT : CPUEVENT
bits : 0 - 31 (32 bit)


EXTI_HWCFGR4 (HWCFGR4)

EXTI hardware configuration register 4
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR4 EXTI_HWCFGR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENT_TRG

EVENT_TRG : EVENT_TRG
bits : 0 - 31 (32 bit)


EXTI_HWCFGR3 (HWCFGR3)

EXTI hardware configuration register 3
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR3 EXTI_HWCFGR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENT_TRG

EVENT_TRG : EVENT_TRG
bits : 0 - 31 (32 bit)


EXTI_HWCFGR2 (HWCFGR2)

EXTI hardware configuration register 2
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR2 EXTI_HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENT_TRG

EVENT_TRG : EVENT_TRG
bits : 0 - 31 (32 bit)


EXTI_HWCFGR1 (HWCFGR1)

EXTI hardware configuration register 1
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_HWCFGR1 EXTI_HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBEVENTS NBCPUS CPUEVTEN NBIOPORT

NBEVENTS : NBEVENTS
bits : 0 - 7 (8 bit)

NBCPUS : NBCPUS
bits : 8 - 11 (4 bit)

CPUEVTEN : CPUEVTEN
bits : 12 - 15 (4 bit)

NBIOPORT : NBIOPORT
bits : 16 - 23 (8 bit)


EXTI_VERR (VERR)

EXTI IP version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_VERR EXTI_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


EXTI_IPIDR (IPIDR)

EXTI identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_IPIDR EXTI_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPID

IPID : IPID
bits : 0 - 31 (32 bit)


EXTI_SIDR (SIDR)

EXTI size ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXTI_SIDR EXTI_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


EXTI_FTSR1 (FTSR1)

Contains only register bits for configurable events.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_FTSR1 EXTI_FTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FT0 FT1 FT2 FT3 FT4 FT5 FT6 FT7 FT8 FT9 FT10 FT11 FT12 FT13 FT14 FT15 FT16

FT0 : FT0
bits : 0 - 0 (1 bit)

FT1 : FT1
bits : 1 - 1 (1 bit)

FT2 : FT2
bits : 2 - 2 (1 bit)

FT3 : FT3
bits : 3 - 3 (1 bit)

FT4 : FT4
bits : 4 - 4 (1 bit)

FT5 : FT5
bits : 5 - 5 (1 bit)

FT6 : FT6
bits : 6 - 6 (1 bit)

FT7 : FT7
bits : 7 - 7 (1 bit)

FT8 : FT8
bits : 8 - 8 (1 bit)

FT9 : FT9
bits : 9 - 9 (1 bit)

FT10 : FT10
bits : 10 - 10 (1 bit)

FT11 : FT11
bits : 11 - 11 (1 bit)

FT12 : FT12
bits : 12 - 12 (1 bit)

FT13 : FT13
bits : 13 - 13 (1 bit)

FT14 : FT14
bits : 14 - 14 (1 bit)

FT15 : FT15
bits : 15 - 15 (1 bit)

FT16 : FT16
bits : 16 - 16 (1 bit)


EXTI_RTSR3 (RTSR3)

Contains only register bits for configurable events.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_RTSR3 EXTI_RTSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT65 RT66 RT68 RT73 RT74

RT65 : RT65
bits : 1 - 1 (1 bit)

RT66 : RT66
bits : 2 - 2 (1 bit)

RT68 : RT68
bits : 4 - 4 (1 bit)

RT73 : RT73
bits : 9 - 9 (1 bit)

RT74 : RT74
bits : 10 - 10 (1 bit)


EXTI_FTSR3 (FTSR3)

Contains only register bits for configurable events.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_FTSR3 EXTI_FTSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FT65 FT66 FT68 FT73 FT74

FT65 : FT65
bits : 1 - 1 (1 bit)

FT66 : FT66
bits : 2 - 2 (1 bit)

FT68 : FT68
bits : 4 - 4 (1 bit)

FT73 : FT73
bits : 9 - 9 (1 bit)

FT74 : FT74
bits : 10 - 10 (1 bit)


EXTI_SWIER3 (SWIER3)

Contains only register bits for configurable events.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_SWIER3 EXTI_SWIER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWI65 SWI66 SWI68 SWI73 SWI74

SWI65 : SWI65
bits : 1 - 1 (1 bit)

SWI66 : SWI66
bits : 2 - 2 (1 bit)

SWI68 : SWI68
bits : 4 - 4 (1 bit)

SWI73 : SWI73
bits : 9 - 9 (1 bit)

SWI74 : SWI74
bits : 10 - 10 (1 bit)


EXTI_RPR3 (RPR3)

Contains only register bits for configurable events.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_RPR3 EXTI_RPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPIF65 RPIF66 RPIF68 RPIF73 RPIF74

RPIF65 : RPIF65
bits : 1 - 1 (1 bit)

RPIF66 : RPIF66
bits : 2 - 2 (1 bit)

RPIF68 : RPIF68
bits : 4 - 4 (1 bit)

RPIF73 : RPIF73
bits : 9 - 9 (1 bit)

RPIF74 : RPIF74
bits : 10 - 10 (1 bit)


EXTI_FPR3 (FPR3)

Contains only register bits for configurable events.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_FPR3 EXTI_FPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPIF65 FPIF66 FPIF68 FPIF73 FPIF74

FPIF65 : FPIF65
bits : 1 - 1 (1 bit)

FPIF66 : FPIF66
bits : 2 - 2 (1 bit)

FPIF68 : FPIF68
bits : 4 - 4 (1 bit)

FPIF73 : FPIF73
bits : 9 - 9 (1 bit)

FPIF74 : FPIF74
bits : 10 - 10 (1 bit)


EXTI_TZENR3 (TZENR3)

This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_TZENR3 EXTI_TZENR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR1 (EXTICR1)

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EXTICR1 EXTI_EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI0
bits : 0 - 7 (8 bit)

EXTI1 : EXTI1
bits : 8 - 15 (8 bit)

EXTI2 : EXTI2
bits : 16 - 23 (8 bit)

EXTI3 : EXTI3
bits : 24 - 31 (8 bit)


EXTI_EXTICR2 (EXTICR2)

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EXTICR2 EXTI_EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI4
bits : 0 - 7 (8 bit)

EXTI5 : EXTI5
bits : 8 - 15 (8 bit)

EXTI6 : EXTI6
bits : 16 - 23 (8 bit)

EXTI7 : EXTI7
bits : 24 - 31 (8 bit)


EXTI_EXTICR3 (EXTICR3)

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EXTICR3 EXTI_EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI8
bits : 0 - 7 (8 bit)

EXTI9 : EXTI9
bits : 8 - 15 (8 bit)

EXTI10 : EXTI10
bits : 16 - 23 (8 bit)

EXTI11 : EXTI11
bits : 24 - 31 (8 bit)


EXTI_EXTICR4 (EXTICR4)

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EXTICR4 EXTI_EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12
bits : 0 - 7 (8 bit)

EXTI13 : EXTI13
bits : 8 - 15 (8 bit)

EXTI14 : EXTI14
bits : 16 - 23 (8 bit)

EXTI15 : EXTI15
bits : 24 - 31 (8 bit)


EXTI_SWIER1 (SWIER1)

Contains only register bits for configurable events.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_SWIER1 EXTI_SWIER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWI0 SWI1 SWI2 SWI3 SWI4 SWI5 SWI6 SWI7 SWI8 SWI9 SWI10 SWI11 SWI12 SWI13 SWI14 SWI15 SWI16

SWI0 : SWI0
bits : 0 - 0 (1 bit)

SWI1 : SWI1
bits : 1 - 1 (1 bit)

SWI2 : SWI2
bits : 2 - 2 (1 bit)

SWI3 : SWI3
bits : 3 - 3 (1 bit)

SWI4 : SWI4
bits : 4 - 4 (1 bit)

SWI5 : SWI5
bits : 5 - 5 (1 bit)

SWI6 : SWI6
bits : 6 - 6 (1 bit)

SWI7 : SWI7
bits : 7 - 7 (1 bit)

SWI8 : SWI8
bits : 8 - 8 (1 bit)

SWI9 : SWI9
bits : 9 - 9 (1 bit)

SWI10 : SWI10
bits : 10 - 10 (1 bit)

SWI11 : SWI11
bits : 11 - 11 (1 bit)

SWI12 : SWI12
bits : 12 - 12 (1 bit)

SWI13 : SWI13
bits : 13 - 13 (1 bit)

SWI14 : SWI14
bits : 14 - 14 (1 bit)

SWI15 : SWI15
bits : 15 - 15 (1 bit)

SWI16 : SWI16
bits : 16 - 16 (1 bit)


EXTI_IMR1 (IMR1)

Contains register bits for configurable events and Direct events.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_IMR1 EXTI_IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15 IM16 IM17 IM18 IM19 IM20 IM21 IM22 IM23 IM24 IM25 IM26 IM27 IM28 IM29 IM30 IM31

IM0 : IM0
bits : 0 - 0 (1 bit)

IM1 : IM1
bits : 1 - 1 (1 bit)

IM2 : IM2
bits : 2 - 2 (1 bit)

IM3 : IM3
bits : 3 - 3 (1 bit)

IM4 : IM4
bits : 4 - 4 (1 bit)

IM5 : IM5
bits : 5 - 5 (1 bit)

IM6 : IM6
bits : 6 - 6 (1 bit)

IM7 : IM7
bits : 7 - 7 (1 bit)

IM8 : IM8
bits : 8 - 8 (1 bit)

IM9 : IM9
bits : 9 - 9 (1 bit)

IM10 : IM10
bits : 10 - 10 (1 bit)

IM11 : IM11
bits : 11 - 11 (1 bit)

IM12 : IM12
bits : 12 - 12 (1 bit)

IM13 : IM13
bits : 13 - 13 (1 bit)

IM14 : IM14
bits : 14 - 14 (1 bit)

IM15 : IM15
bits : 15 - 15 (1 bit)

IM16 : IM16
bits : 16 - 16 (1 bit)

IM17 : IM17
bits : 17 - 17 (1 bit)

IM18 : IM18
bits : 18 - 18 (1 bit)

IM19 : IM19
bits : 19 - 19 (1 bit)

IM20 : IM20
bits : 20 - 20 (1 bit)

IM21 : IM21
bits : 21 - 21 (1 bit)

IM22 : IM22
bits : 22 - 22 (1 bit)

IM23 : IM23
bits : 23 - 23 (1 bit)

IM24 : IM24
bits : 24 - 24 (1 bit)

IM25 : IM25
bits : 25 - 25 (1 bit)

IM26 : IM26
bits : 26 - 26 (1 bit)

IM27 : IM27
bits : 27 - 27 (1 bit)

IM28 : IM28
bits : 28 - 28 (1 bit)

IM29 : IM29
bits : 29 - 29 (1 bit)

IM30 : IM30
bits : 30 - 30 (1 bit)

IM31 : IM31
bits : 31 - 31 (1 bit)


EXTI_EMR1 (EMR1)

EXTI CPU wakeup with event mask register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EMR1 EXTI_EMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EM4 EM5 EM6 EM7 EM8 EM9 EM10 EM11 EM12 EM13 EM14 EM15 EM17 EM18 EM19

EM0 : EM0
bits : 0 - 0 (1 bit)

EM1 : EM1
bits : 1 - 1 (1 bit)

EM2 : EM2
bits : 2 - 2 (1 bit)

EM3 : EM3
bits : 3 - 3 (1 bit)

EM4 : EM4
bits : 4 - 4 (1 bit)

EM5 : EM5
bits : 5 - 5 (1 bit)

EM6 : EM6
bits : 6 - 6 (1 bit)

EM7 : EM7
bits : 7 - 7 (1 bit)

EM8 : EM8
bits : 8 - 8 (1 bit)

EM9 : EM9
bits : 9 - 9 (1 bit)

EM10 : EM10
bits : 10 - 10 (1 bit)

EM11 : EM11
bits : 11 - 11 (1 bit)

EM12 : EM12
bits : 12 - 12 (1 bit)

EM13 : EM13
bits : 13 - 13 (1 bit)

EM14 : EM14
bits : 14 - 14 (1 bit)

EM15 : EM15
bits : 15 - 15 (1 bit)

EM17 : EM17
bits : 17 - 17 (1 bit)

EM18 : EM18
bits : 18 - 18 (1 bit)

EM19 : EM19
bits : 19 - 19 (1 bit)


EXTI_IMR2 (IMR2)

Contains register bits for configurable events and direct events.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_IMR2 EXTI_IMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM32 IM33 IM34 IM35 IM36 IM37 IM38 IM39 IM40 IM41 IM42 IM43 IM44 IM45 IM46 IM47 IM48 IM49 IM50 IM51 IM52 IM53 IM54 IM55 IM56 IM57 IM58 IM59 IM60 IM61 IM62 IM63

IM32 : IM32
bits : 0 - 0 (1 bit)

IM33 : IM33
bits : 1 - 1 (1 bit)

IM34 : IM34
bits : 2 - 2 (1 bit)

IM35 : IM35
bits : 3 - 3 (1 bit)

IM36 : IM36
bits : 4 - 4 (1 bit)

IM37 : IM37
bits : 5 - 5 (1 bit)

IM38 : IM38
bits : 6 - 6 (1 bit)

IM39 : IM39
bits : 7 - 7 (1 bit)

IM40 : IM40
bits : 8 - 8 (1 bit)

IM41 : IM41
bits : 9 - 9 (1 bit)

IM42 : IM42
bits : 10 - 10 (1 bit)

IM43 : IM43
bits : 11 - 11 (1 bit)

IM44 : IM44
bits : 12 - 12 (1 bit)

IM45 : IM45
bits : 13 - 13 (1 bit)

IM46 : IM46
bits : 14 - 14 (1 bit)

IM47 : IM47
bits : 15 - 15 (1 bit)

IM48 : IM48
bits : 16 - 16 (1 bit)

IM49 : IM49
bits : 17 - 17 (1 bit)

IM50 : IM50
bits : 18 - 18 (1 bit)

IM51 : IM51
bits : 19 - 19 (1 bit)

IM52 : IM52
bits : 20 - 20 (1 bit)

IM53 : IM53
bits : 21 - 21 (1 bit)

IM54 : IM54
bits : 22 - 22 (1 bit)

IM55 : IM55
bits : 23 - 23 (1 bit)

IM56 : IM56
bits : 24 - 24 (1 bit)

IM57 : IM57
bits : 25 - 25 (1 bit)

IM58 : IM58
bits : 26 - 26 (1 bit)

IM59 : IM59
bits : 27 - 27 (1 bit)

IM60 : IM60
bits : 28 - 28 (1 bit)

IM61 : IM61
bits : 29 - 29 (1 bit)

IM62 : IM62
bits : 30 - 30 (1 bit)

IM63 : IM63
bits : 31 - 31 (1 bit)


EXTI_EMR2 (EMR2)

EXTI CPU wakeup with event mask register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EMR2 EXTI_EMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_IMR3 (IMR3)

Contains register bits for configurable events and direct events.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_IMR3 EXTI_IMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM64 IM65 IM66 IM67 IM68 IM69 IM70 IM71 IM72 IM73 IM74 IM75

IM64 : IM64
bits : 0 - 0 (1 bit)

IM65 : IM65
bits : 1 - 1 (1 bit)

IM66 : IM66
bits : 2 - 2 (1 bit)

IM67 : IM67
bits : 3 - 3 (1 bit)

IM68 : IM68
bits : 4 - 4 (1 bit)

IM69 : IM69
bits : 5 - 5 (1 bit)

IM70 : IM70
bits : 6 - 6 (1 bit)

IM71 : IM71
bits : 7 - 7 (1 bit)

IM72 : IM72
bits : 8 - 8 (1 bit)

IM73 : IM73
bits : 9 - 9 (1 bit)

IM74 : IM74
bits : 10 - 10 (1 bit)

IM75 : IM75
bits : 11 - 11 (1 bit)


EXTI_EMR3 (EMR3)

EXTI CPU wakeup with event mask register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_EMR3 EXTI_EMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM66

EM66 : EM66
bits : 2 - 2 (1 bit)


EXTI_RPR1 (RPR1)

Contains only register bits for configurable events.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_RPR1 EXTI_RPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPIF0 RPIF1 RPIF2 RPIF3 RPIF4 RPIF5 RPIF6 RPIF7 RPIF8 RPIF9 RPIF10 RPIF11 RPIF12 RPIF13 RPIF14 RPIF15 RPIF16

RPIF0 : RPIF0
bits : 0 - 0 (1 bit)

RPIF1 : RPIF1
bits : 1 - 1 (1 bit)

RPIF2 : RPIF2
bits : 2 - 2 (1 bit)

RPIF3 : RPIF3
bits : 3 - 3 (1 bit)

RPIF4 : RPIF4
bits : 4 - 4 (1 bit)

RPIF5 : RPIF5
bits : 5 - 5 (1 bit)

RPIF6 : RPIF6
bits : 6 - 6 (1 bit)

RPIF7 : RPIF7
bits : 7 - 7 (1 bit)

RPIF8 : RPIF8
bits : 8 - 8 (1 bit)

RPIF9 : RPIF9
bits : 9 - 9 (1 bit)

RPIF10 : RPIF10
bits : 10 - 10 (1 bit)

RPIF11 : RPIF11
bits : 11 - 11 (1 bit)

RPIF12 : RPIF12
bits : 12 - 12 (1 bit)

RPIF13 : RPIF13
bits : 13 - 13 (1 bit)

RPIF14 : RPIF14
bits : 14 - 14 (1 bit)

RPIF15 : RPIF15
bits : 15 - 15 (1 bit)

RPIF16 : RPIF16
bits : 16 - 16 (1 bit)


EXTI_C2IMR1 (C2IMR1)

Contains register bits for configurable events and Direct events.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_C2IMR1 EXTI_C2IMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15 IM16 IM17 IM18 IM19 IM20 IM21 IM22 IM23 IM24 IM25 IM26 IM27 IM28 IM29 IM30 IM31

IM0 : IM0
bits : 0 - 0 (1 bit)

IM1 : IM1
bits : 1 - 1 (1 bit)

IM2 : IM2
bits : 2 - 2 (1 bit)

IM3 : IM3
bits : 3 - 3 (1 bit)

IM4 : IM4
bits : 4 - 4 (1 bit)

IM5 : IM5
bits : 5 - 5 (1 bit)

IM6 : IM6
bits : 6 - 6 (1 bit)

IM7 : IM7
bits : 7 - 7 (1 bit)

IM8 : IM8
bits : 8 - 8 (1 bit)

IM9 : IM9
bits : 9 - 9 (1 bit)

IM10 : IM10
bits : 10 - 10 (1 bit)

IM11 : IM11
bits : 11 - 11 (1 bit)

IM12 : IM12
bits : 12 - 12 (1 bit)

IM13 : IM13
bits : 13 - 13 (1 bit)

IM14 : IM14
bits : 14 - 14 (1 bit)

IM15 : IM15
bits : 15 - 15 (1 bit)

IM16 : IM16
bits : 16 - 16 (1 bit)

IM17 : IM17
bits : 17 - 17 (1 bit)

IM18 : IM18
bits : 18 - 18 (1 bit)

IM19 : IM19
bits : 19 - 19 (1 bit)

IM20 : IM20
bits : 20 - 20 (1 bit)

IM21 : IM21
bits : 21 - 21 (1 bit)

IM22 : IM22
bits : 22 - 22 (1 bit)

IM23 : IM23
bits : 23 - 23 (1 bit)

IM24 : IM24
bits : 24 - 24 (1 bit)

IM25 : IM25
bits : 25 - 25 (1 bit)

IM26 : IM26
bits : 26 - 26 (1 bit)

IM27 : IM27
bits : 27 - 27 (1 bit)

IM28 : IM28
bits : 28 - 28 (1 bit)

IM29 : IM29
bits : 29 - 29 (1 bit)

IM30 : IM30
bits : 30 - 30 (1 bit)

IM31 : IM31
bits : 31 - 31 (1 bit)


EXTI_C2EMR1 (C2EMR1)

EXTI CPU2 wakeup with event mask register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_C2EMR1 EXTI_C2EMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EM2 EM3 EM4 EM5 EM6 EM7 EM8 EM9 EM10 EM11 EM12 EM13 EM14 EM15 EM17 EM18 EM19

EM0 : EM0
bits : 0 - 0 (1 bit)

EM1 : EM1
bits : 1 - 1 (1 bit)

EM2 : EM2
bits : 2 - 2 (1 bit)

EM3 : EM3
bits : 3 - 3 (1 bit)

EM4 : EM4
bits : 4 - 4 (1 bit)

EM5 : EM5
bits : 5 - 5 (1 bit)

EM6 : EM6
bits : 6 - 6 (1 bit)

EM7 : EM7
bits : 7 - 7 (1 bit)

EM8 : EM8
bits : 8 - 8 (1 bit)

EM9 : EM9
bits : 9 - 9 (1 bit)

EM10 : EM10
bits : 10 - 10 (1 bit)

EM11 : EM11
bits : 11 - 11 (1 bit)

EM12 : EM12
bits : 12 - 12 (1 bit)

EM13 : EM13
bits : 13 - 13 (1 bit)

EM14 : EM14
bits : 14 - 14 (1 bit)

EM15 : EM15
bits : 15 - 15 (1 bit)

EM17 : EM17
bits : 17 - 17 (1 bit)

EM18 : EM18
bits : 18 - 18 (1 bit)

EM19 : EM19
bits : 19 - 19 (1 bit)


EXTI_C2IMR2 (C2IMR2)

Contains register bits for configurable events and direct events.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_C2IMR2 EXTI_C2IMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM32 IM33 IM34 IM35 IM36 IM37 IM38 IM39 IM40 IM41 IM42 IM43 IM44 IM45 IM46 IM47 IM48 IM49 IM50 IM51 IM52 IM53 IM54 IM55 IM56 IM57 IM58 IM59 IM60 IM61 IM62 IM63

IM32 : IM32
bits : 0 - 0 (1 bit)

IM33 : IM33
bits : 1 - 1 (1 bit)

IM34 : IM34
bits : 2 - 2 (1 bit)

IM35 : IM35
bits : 3 - 3 (1 bit)

IM36 : IM36
bits : 4 - 4 (1 bit)

IM37 : IM37
bits : 5 - 5 (1 bit)

IM38 : IM38
bits : 6 - 6 (1 bit)

IM39 : IM39
bits : 7 - 7 (1 bit)

IM40 : IM40
bits : 8 - 8 (1 bit)

IM41 : IM41
bits : 9 - 9 (1 bit)

IM42 : IM42
bits : 10 - 10 (1 bit)

IM43 : IM43
bits : 11 - 11 (1 bit)

IM44 : IM44
bits : 12 - 12 (1 bit)

IM45 : IM45
bits : 13 - 13 (1 bit)

IM46 : IM46
bits : 14 - 14 (1 bit)

IM47 : IM47
bits : 15 - 15 (1 bit)

IM48 : IM48
bits : 16 - 16 (1 bit)

IM49 : IM49
bits : 17 - 17 (1 bit)

IM50 : IM50
bits : 18 - 18 (1 bit)

IM51 : IM51
bits : 19 - 19 (1 bit)

IM52 : IM52
bits : 20 - 20 (1 bit)

IM53 : IM53
bits : 21 - 21 (1 bit)

IM54 : IM54
bits : 22 - 22 (1 bit)

IM55 : IM55
bits : 23 - 23 (1 bit)

IM56 : IM56
bits : 24 - 24 (1 bit)

IM57 : IM57
bits : 25 - 25 (1 bit)

IM58 : IM58
bits : 26 - 26 (1 bit)

IM59 : IM59
bits : 27 - 27 (1 bit)

IM60 : IM60
bits : 28 - 28 (1 bit)

IM61 : IM61
bits : 29 - 29 (1 bit)

IM62 : IM62
bits : 30 - 30 (1 bit)

IM63 : IM63
bits : 31 - 31 (1 bit)


EXTI_C2EMR2 (C2EMR2)

EXTI CPU2 wakeup with event mask register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_C2EMR2 EXTI_C2EMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_C2IMR3 (C2IMR3)

Contains register bits for configurable events and direct events.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_C2IMR3 EXTI_C2IMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM64 IM65 IM66 IM67 IM68 IM69 IM70 IM71 IM72 IM73 IM74 IM75

IM64 : IM64
bits : 0 - 0 (1 bit)

IM65 : IM65
bits : 1 - 1 (1 bit)

IM66 : IM66
bits : 2 - 2 (1 bit)

IM67 : IM67
bits : 3 - 3 (1 bit)

IM68 : IM68
bits : 4 - 4 (1 bit)

IM69 : IM69
bits : 5 - 5 (1 bit)

IM70 : IM70
bits : 6 - 6 (1 bit)

IM71 : IM71
bits : 7 - 7 (1 bit)

IM72 : IM72
bits : 8 - 8 (1 bit)

IM73 : IM73
bits : 9 - 9 (1 bit)

IM74 : IM74
bits : 10 - 10 (1 bit)

IM75 : IM75
bits : 11 - 11 (1 bit)


EXTI_C2EMR3 (C2EMR3)

EXTI CPU2 wakeup with event mask register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_C2EMR3 EXTI_C2EMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM66

EM66 : EM66
bits : 2 - 2 (1 bit)



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