\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
FDCAN core release register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : DAY
bits : 0 - 7 (8 bit)
MON : MON
bits : 8 - 15 (8 bit)
YEAR : YEAR
bits : 16 - 19 (4 bit)
SUBSTEP : SUBSTEP
bits : 20 - 23 (4 bit)
STEP : STEP
bits : 24 - 27 (4 bit)
REL : REL
bits : 28 - 31 (4 bit)
Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : LBCK
bits : 4 - 4 (1 bit)
access : read-write
TX : TX
bits : 5 - 6 (2 bit)
access : read-write
RX : RX
bits : 7 - 7 (1 bit)
access : read-only
FDCAN TT trigger memory configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSA : TMSA
bits : 2 - 15 (14 bit)
TME : TME
bits : 16 - 22 (7 bit)
FDCAN TT reference message configuration register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RID : RID
bits : 0 - 28 (29 bit)
XTD : XTD
bits : 30 - 30 (1 bit)
RMPS : RMPS
bits : 31 - 31 (1 bit)
FDCAN TT operation configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OM : OM
bits : 0 - 1 (2 bit)
GEN : GEN
bits : 3 - 3 (1 bit)
TM : TM
bits : 4 - 4 (1 bit)
LDSDL : LDSDL
bits : 5 - 7 (3 bit)
IRTO : IRTO
bits : 8 - 14 (7 bit)
EECS : EECS
bits : 15 - 15 (1 bit)
AWL : AWL
bits : 16 - 23 (8 bit)
EGTF : EGTF
bits : 24 - 24 (1 bit)
ECC : ECC
bits : 25 - 25 (1 bit)
EVTP : EVTP
bits : 26 - 26 (1 bit)
FDCAN TT matrix limits register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM : CCM
bits : 0 - 5 (6 bit)
CSS : CSS
bits : 6 - 7 (2 bit)
TXEW : TXEW
bits : 8 - 11 (4 bit)
ENTT : ENTT
bits : 16 - 27 (12 bit)
The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCL : NCL
bits : 0 - 15 (16 bit)
DC : DC
bits : 16 - 29 (14 bit)
ELT : ELT
bits : 31 - 31 (1 bit)
FDCAN TT operation control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGT : SGT
bits : 0 - 0 (1 bit)
access : read-write
ECS : ECS
bits : 1 - 1 (1 bit)
access : read-write
SWP : SWP
bits : 2 - 2 (1 bit)
access : read-write
SWS : SWS
bits : 3 - 4 (2 bit)
access : read-write
RTIE : RTIE
bits : 5 - 5 (1 bit)
access : read-write
TMC : TMC
bits : 6 - 7 (2 bit)
access : read-write
TTIE : TTIE
bits : 8 - 8 (1 bit)
access : read-write
GCS : GCS
bits : 9 - 9 (1 bit)
access : read-write
FGP : FGP
bits : 10 - 10 (1 bit)
access : read-write
TMG : TMG
bits : 11 - 11 (1 bit)
access : read-write
NIG : NIG
bits : 12 - 12 (1 bit)
access : read-write
ESCN : ESCN
bits : 13 - 13 (1 bit)
access : read-write
LCKC : LCKC
bits : 15 - 15 (1 bit)
access : read-only
If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master.
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TP : TP
bits : 0 - 15 (16 bit)
CTP : CTP
bits : 16 - 31 (16 bit)
A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TM : TM
bits : 0 - 15 (16 bit)
access : read-write
TICC : TICC
bits : 16 - 22 (7 bit)
access : read-write
LCKM : LCKM
bits : 31 - 31 (1 bit)
access : read-only
The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBC : SBC
bits : 0 - 0 (1 bit)
SMC : SMC
bits : 1 - 1 (1 bit)
CSM : CSM
bits : 2 - 2 (1 bit)
SOG : SOG
bits : 3 - 3 (1 bit)
RTMI : RTMI
bits : 4 - 4 (1 bit)
TTMI : TTMI
bits : 5 - 5 (1 bit)
SWE : SWE
bits : 6 - 6 (1 bit)
GTW : GTW
bits : 7 - 7 (1 bit)
GTD : GTD
bits : 8 - 8 (1 bit)
GTE : GTE
bits : 9 - 9 (1 bit)
TXU : TXU
bits : 10 - 10 (1 bit)
TXO : TXO
bits : 11 - 11 (1 bit)
SE1 : SE1
bits : 12 - 12 (1 bit)
SE2 : SE2
bits : 13 - 13 (1 bit)
ELC : ELC
bits : 14 - 14 (1 bit)
IWTG : IWTG
bits : 15 - 15 (1 bit)
WT : WT
bits : 16 - 16 (1 bit)
AW : AW
bits : 17 - 17 (1 bit)
CER : CER
bits : 18 - 18 (1 bit)
The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt.
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBCE : SBCE
bits : 0 - 0 (1 bit)
SMCE : SMCE
bits : 1 - 1 (1 bit)
CSME : CSME
bits : 2 - 2 (1 bit)
SOGE : SOGE
bits : 3 - 3 (1 bit)
RTMIE : RTMIE
bits : 4 - 4 (1 bit)
TTMIE : TTMIE
bits : 5 - 5 (1 bit)
SWEE : SWEE
bits : 6 - 6 (1 bit)
GTWE : GTWE
bits : 7 - 7 (1 bit)
GTDE : GTDE
bits : 8 - 8 (1 bit)
GTEE : GTEE
bits : 9 - 9 (1 bit)
TXUE : TXUE
bits : 10 - 10 (1 bit)
TXOE : TXOE
bits : 11 - 11 (1 bit)
SE1E : SE1E
bits : 12 - 12 (1 bit)
SE2E : SE2E
bits : 13 - 13 (1 bit)
ELCE : ELCE
bits : 14 - 14 (1 bit)
IWTE : IWTE
bits : 15 - 15 (1 bit)
WTE : WTE
bits : 16 - 16 (1 bit)
AWE : AWE
bits : 17 - 17 (1 bit)
CERE : CERE
bits : 18 - 18 (1 bit)
The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBCL : SBCL
bits : 0 - 0 (1 bit)
SMCL : SMCL
bits : 1 - 1 (1 bit)
CSML : CSML
bits : 2 - 2 (1 bit)
SOGL : SOGL
bits : 3 - 3 (1 bit)
RTMIL : RTMIL
bits : 4 - 4 (1 bit)
TTMIL : TTMIL
bits : 5 - 5 (1 bit)
SWEL : SWEL
bits : 6 - 6 (1 bit)
GTWL : GTWL
bits : 7 - 7 (1 bit)
GTDL : GTDL
bits : 8 - 8 (1 bit)
GTEL : GTEL
bits : 9 - 9 (1 bit)
TXUL : TXUL
bits : 10 - 10 (1 bit)
TXOL : TXOL
bits : 11 - 11 (1 bit)
SE1L : SE1L
bits : 12 - 12 (1 bit)
SE2L : SE2L
bits : 13 - 13 (1 bit)
ELCL : ELCL
bits : 14 - 14 (1 bit)
IWTL : IWTL
bits : 15 - 15 (1 bit)
WTL : WTL
bits : 16 - 16 (1 bit)
AWL : AWL
bits : 17 - 17 (1 bit)
CERL : CERL
bits : 18 - 18 (1 bit)
FDCAN TT operation status register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EL : EL
bits : 0 - 1 (2 bit)
MS : MS
bits : 2 - 3 (2 bit)
SYS : SYS
bits : 4 - 5 (2 bit)
QGTP : QGTP
bits : 6 - 6 (1 bit)
QCS : QCS
bits : 7 - 7 (1 bit)
RTO : RTO
bits : 8 - 15 (8 bit)
WGTD : WGTD
bits : 22 - 22 (1 bit)
GFI : GFI
bits : 23 - 23 (1 bit)
TMP : TMP
bits : 24 - 26 (3 bit)
GSI : GSI
bits : 27 - 27 (1 bit)
WFE : WFE
bits : 28 - 28 (1 bit)
AWE : AWE
bits : 29 - 29 (1 bit)
WECS : WECS
bits : 30 - 30 (1 bit)
SPL : SPL
bits : 31 - 31 (1 bit)
There is no drift compensation in TTCAN level 1.
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NAV : NAV
bits : 0 - 17 (18 bit)
FDCAN TT local and global time register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LT : LT
bits : 0 - 15 (16 bit)
GT : GT
bits : 16 - 31 (16 bit)
FDCAN TT cycle time and count register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CT : CT
bits : 0 - 15 (16 bit)
CC : CC
bits : 16 - 21 (6 bit)
FDCAN TT capture time register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CCV : CCV
bits : 0 - 5 (6 bit)
SWV : SWV
bits : 16 - 31 (16 bit)
The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : WDC
bits : 0 - 7 (8 bit)
access : read-write
WDV : WDV
bits : 8 - 15 (8 bit)
access : read-only
FDCAN TT cycle sync mark register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSM : CSM
bits : 0 - 15 (16 bit)
For details about setting and resetting of single bits see Software initialization.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : INIT
bits : 0 - 0 (1 bit)
access : read-write
CCE : CCE
bits : 1 - 1 (1 bit)
access : read-write
ASM : ASM
bits : 2 - 2 (1 bit)
access : read-write
CSA : CSA
bits : 3 - 3 (1 bit)
access : read-only
CSR : CSR
bits : 4 - 4 (1 bit)
access : read-write
MON : MON
bits : 5 - 5 (1 bit)
access : read-write
DAR : DAR
bits : 6 - 6 (1 bit)
access : read-write
TEST : TEST
bits : 7 - 7 (1 bit)
access : read-write
FDOE : FDOE
bits : 8 - 8 (1 bit)
access : read-write
BRSE : BRSE
bits : 9 - 9 (1 bit)
access : read-write
PXHD : PXHD
bits : 12 - 12 (1 bit)
access : read-write
EFBI : EFBI
bits : 13 - 13 (1 bit)
access : read-write
TXP : TXP
bits : 14 - 14 (1 bit)
access : read-write
NISO : NISO
bits : 15 - 15 (1 bit)
access : read-write
This register is dedicated to the nominal bit timing used during the arbitration phase.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTSEG2 : NTSEG2
bits : 0 - 6 (7 bit)
NTSEG1 : NTSEG1
bits : 8 - 15 (8 bit)
NBRP : NBRP
bits : 16 - 24 (9 bit)
NSJW : NSJW
bits : 25 - 31 (7 bit)
FDCAN timestamp counter configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : TSS
bits : 0 - 1 (2 bit)
TCP : TCP
bits : 16 - 19 (4 bit)
FDCAN timestamp counter value register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSC : TSC
bits : 0 - 15 (16 bit)
FDCAN timeout counter configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : ETOC
bits : 0 - 0 (1 bit)
TOS : TOS
bits : 1 - 2 (2 bit)
TOP : TOP
bits : 16 - 31 (16 bit)
FDCAN timeout counter value register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : TOC
bits : 0 - 15 (16 bit)
The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger.
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTDEL : SWTDEL
bits : 0 - 1 (2 bit)
EVTSEL : EVTSEL
bits : 4 - 5 (2 bit)
FDCAN Endian register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETV : ETV
bits : 0 - 31 (32 bit)
FDCAN error counter register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEC : TEC
bits : 0 - 7 (8 bit)
access : read-only
TREC : TREC
bits : 8 - 14 (7 bit)
access : read-only
RP : RP
bits : 15 - 15 (1 bit)
access : read-only
CEL : CEL
bits : 16 - 23 (8 bit)
access : read-write
FDCAN protocol status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEC : LEC
bits : 0 - 2 (3 bit)
access : read-only
ACT : ACT
bits : 3 - 4 (2 bit)
access : read-only
EP : EP
bits : 5 - 5 (1 bit)
access : read-only
EW : EW
bits : 6 - 6 (1 bit)
access : read-only
BO : BO
bits : 7 - 7 (1 bit)
access : read-only
DLEC : DLEC
bits : 8 - 10 (3 bit)
access : read-only
RESI : RESI
bits : 11 - 11 (1 bit)
access : read-write
RBRS : RBRS
bits : 12 - 12 (1 bit)
access : read-write
REDL : REDL
bits : 13 - 13 (1 bit)
access : read-write
PXE : PXE
bits : 14 - 14 (1 bit)
access : read-write
TDCV : TDCV
bits : 16 - 22 (7 bit)
access : read-only
FDCAN transmitter delay compensation register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCF : TDCF
bits : 0 - 6 (7 bit)
TDCO : TDCO
bits : 8 - 14 (7 bit)
The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : RF0N
bits : 0 - 0 (1 bit)
RF0W : RF0W
bits : 1 - 1 (1 bit)
RF0F : RF0F
bits : 2 - 2 (1 bit)
RF0L : RF0L
bits : 3 - 3 (1 bit)
RF1N : RF1N
bits : 4 - 4 (1 bit)
RF1W : RF1W
bits : 5 - 5 (1 bit)
RF1F : RF1F
bits : 6 - 6 (1 bit)
RF1L : RF1L
bits : 7 - 7 (1 bit)
HPM : HPM
bits : 8 - 8 (1 bit)
TC : TC
bits : 9 - 9 (1 bit)
TCF : TCF
bits : 10 - 10 (1 bit)
TFE : TFE
bits : 11 - 11 (1 bit)
TEFN : TEFN
bits : 12 - 12 (1 bit)
TEFW : TEFW
bits : 13 - 13 (1 bit)
TEFF : TEFF
bits : 14 - 14 (1 bit)
TEFL : TEFL
bits : 15 - 15 (1 bit)
TSW : TSW
bits : 16 - 16 (1 bit)
MRAF : MRAF
bits : 17 - 17 (1 bit)
TOO : TOO
bits : 18 - 18 (1 bit)
DRX : DRX
bits : 19 - 19 (1 bit)
ELO : ELO
bits : 22 - 22 (1 bit)
EP : EP
bits : 23 - 23 (1 bit)
EW : EW
bits : 24 - 24 (1 bit)
BO : BO
bits : 25 - 25 (1 bit)
WDI : WDI
bits : 26 - 26 (1 bit)
PEA : PEA
bits : 27 - 27 (1 bit)
PED : PED
bits : 28 - 28 (1 bit)
ARA : ARA
bits : 29 - 29 (1 bit)
The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : RF0NE
bits : 0 - 0 (1 bit)
RF0WE : RF0WE
bits : 1 - 1 (1 bit)
RF0FE : RF0FE
bits : 2 - 2 (1 bit)
RF0LE : RF0LE
bits : 3 - 3 (1 bit)
RF1NE : RF1NE
bits : 4 - 4 (1 bit)
RF1WE : RF1WE
bits : 5 - 5 (1 bit)
RF1FE : RF1FE
bits : 6 - 6 (1 bit)
RF1LE : RF1LE
bits : 7 - 7 (1 bit)
HPME : HPME
bits : 8 - 8 (1 bit)
TCE : TCE
bits : 9 - 9 (1 bit)
TCFE : TCFE
bits : 10 - 10 (1 bit)
TFEE : TFEE
bits : 11 - 11 (1 bit)
TEFNE : TEFNE
bits : 12 - 12 (1 bit)
TEFWE : TEFWE
bits : 13 - 13 (1 bit)
TEFFE : TEFFE
bits : 14 - 14 (1 bit)
TEFLE : TEFLE
bits : 15 - 15 (1 bit)
TSWE : TSWE
bits : 16 - 16 (1 bit)
MRAFE : MRAFE
bits : 17 - 17 (1 bit)
TOOE : TOOE
bits : 18 - 18 (1 bit)
DRXE : DRXE
bits : 19 - 19 (1 bit)
BECE : BECE
bits : 20 - 20 (1 bit)
BEUE : BEUE
bits : 21 - 21 (1 bit)
ELOE : ELOE
bits : 22 - 22 (1 bit)
EPE : EPE
bits : 23 - 23 (1 bit)
EWE : EWE
bits : 24 - 24 (1 bit)
BOE : BOE
bits : 25 - 25 (1 bit)
WDIE : WDIE
bits : 26 - 26 (1 bit)
PEAE : PEAE
bits : 27 - 27 (1 bit)
PEDE : PEDE
bits : 28 - 28 (1 bit)
ARAE : ARAE
bits : 29 - 29 (1 bit)
This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : RF0NL
bits : 0 - 0 (1 bit)
RF0WL : RF0WL
bits : 1 - 1 (1 bit)
RF0FL : RF0FL
bits : 2 - 2 (1 bit)
RF0LL : RF0LL
bits : 3 - 3 (1 bit)
RF1NL : RF1NL
bits : 4 - 4 (1 bit)
RF1WL : RF1WL
bits : 5 - 5 (1 bit)
RF1FL : RF1FL
bits : 6 - 6 (1 bit)
RF1LL : RF1LL
bits : 7 - 7 (1 bit)
HPML : HPML
bits : 8 - 8 (1 bit)
TCL : TCL
bits : 9 - 9 (1 bit)
TCFL : TCFL
bits : 10 - 10 (1 bit)
TFEL : TFEL
bits : 11 - 11 (1 bit)
TEFNL : TEFNL
bits : 12 - 12 (1 bit)
TEFWL : TEFWL
bits : 13 - 13 (1 bit)
TEFFL : TEFFL
bits : 14 - 14 (1 bit)
TEFLL : TEFLL
bits : 15 - 15 (1 bit)
TSWL : TSWL
bits : 16 - 16 (1 bit)
MRAFL : MRAFL
bits : 17 - 17 (1 bit)
TOOL : TOOL
bits : 18 - 18 (1 bit)
DRXL : DRXL
bits : 19 - 19 (1 bit)
BECL : BECL
bits : 20 - 20 (1 bit)
BEUL : BEUL
bits : 21 - 21 (1 bit)
ELOL : ELOL
bits : 22 - 22 (1 bit)
EPL : EPL
bits : 23 - 23 (1 bit)
EWL : EWL
bits : 24 - 24 (1 bit)
BOL : BOL
bits : 25 - 25 (1 bit)
WDIL : WDIL
bits : 26 - 26 (1 bit)
PEAL : PEAL
bits : 27 - 27 (1 bit)
PEDL : PEDL
bits : 28 - 28 (1 bit)
ARAL : ARAL
bits : 29 - 29 (1 bit)
Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : EINT0
bits : 0 - 0 (1 bit)
EINT1 : EINT1
bits : 1 - 1 (1 bit)
Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : RRFE
bits : 0 - 0 (1 bit)
RRFS : RRFS
bits : 1 - 1 (1 bit)
ANFE : ANFE
bits : 2 - 3 (2 bit)
ANFS : ANFS
bits : 4 - 5 (2 bit)
Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : FLSSA
bits : 2 - 15 (14 bit)
LSS : LSS
bits : 16 - 23 (8 bit)
Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : FLESA
bits : 2 - 15 (14 bit)
LSE : LSE
bits : 16 - 23 (8 bit)
FDCAN extended ID and mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : EIDM
bits : 0 - 28 (29 bit)
This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : BIDX
bits : 0 - 5 (6 bit)
MSI : MSI
bits : 6 - 7 (2 bit)
FIDX : FIDX
bits : 8 - 14 (7 bit)
FLST : FLST
bits : 15 - 15 (1 bit)
FDCAN new data 1 register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND0 : ND0
bits : 0 - 0 (1 bit)
ND1 : ND1
bits : 1 - 1 (1 bit)
ND2 : ND2
bits : 2 - 2 (1 bit)
ND3 : ND3
bits : 3 - 3 (1 bit)
ND4 : ND4
bits : 4 - 4 (1 bit)
ND5 : ND5
bits : 5 - 5 (1 bit)
ND6 : ND6
bits : 6 - 6 (1 bit)
ND7 : ND7
bits : 7 - 7 (1 bit)
ND8 : ND8
bits : 8 - 8 (1 bit)
ND9 : ND9
bits : 9 - 9 (1 bit)
ND10 : ND10
bits : 10 - 10 (1 bit)
ND11 : ND11
bits : 11 - 11 (1 bit)
ND12 : ND12
bits : 12 - 12 (1 bit)
ND13 : ND13
bits : 13 - 13 (1 bit)
ND14 : ND14
bits : 14 - 14 (1 bit)
ND15 : ND15
bits : 15 - 15 (1 bit)
ND16 : ND16
bits : 16 - 16 (1 bit)
ND17 : ND17
bits : 17 - 17 (1 bit)
ND18 : ND18
bits : 18 - 18 (1 bit)
ND19 : ND19
bits : 19 - 19 (1 bit)
ND20 : ND20
bits : 20 - 20 (1 bit)
ND21 : ND21
bits : 21 - 21 (1 bit)
ND22 : ND22
bits : 22 - 22 (1 bit)
ND23 : ND23
bits : 23 - 23 (1 bit)
ND24 : ND24
bits : 24 - 24 (1 bit)
ND25 : ND25
bits : 25 - 25 (1 bit)
ND26 : ND26
bits : 26 - 26 (1 bit)
ND27 : ND27
bits : 27 - 27 (1 bit)
ND28 : ND28
bits : 28 - 28 (1 bit)
ND29 : ND29
bits : 29 - 29 (1 bit)
ND30 : ND30
bits : 30 - 30 (1 bit)
ND31 : ND31
bits : 31 - 31 (1 bit)
FDCAN new data 2 register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND32 : ND32
bits : 0 - 0 (1 bit)
ND33 : ND33
bits : 1 - 1 (1 bit)
ND34 : ND34
bits : 2 - 2 (1 bit)
ND35 : ND35
bits : 3 - 3 (1 bit)
ND36 : ND36
bits : 4 - 4 (1 bit)
ND37 : ND37
bits : 5 - 5 (1 bit)
ND38 : ND38
bits : 6 - 6 (1 bit)
ND39 : ND39
bits : 7 - 7 (1 bit)
ND40 : ND40
bits : 8 - 8 (1 bit)
ND41 : ND41
bits : 9 - 9 (1 bit)
ND42 : ND42
bits : 10 - 10 (1 bit)
ND43 : ND43
bits : 11 - 11 (1 bit)
ND44 : ND44
bits : 12 - 12 (1 bit)
ND45 : ND45
bits : 13 - 13 (1 bit)
ND46 : ND46
bits : 14 - 14 (1 bit)
ND47 : ND47
bits : 15 - 15 (1 bit)
ND48 : ND48
bits : 16 - 16 (1 bit)
ND49 : ND49
bits : 17 - 17 (1 bit)
ND50 : ND50
bits : 18 - 18 (1 bit)
ND51 : ND51
bits : 19 - 19 (1 bit)
ND52 : ND52
bits : 20 - 20 (1 bit)
ND53 : ND53
bits : 21 - 21 (1 bit)
ND54 : ND54
bits : 22 - 22 (1 bit)
ND55 : ND55
bits : 23 - 23 (1 bit)
ND56 : ND56
bits : 24 - 24 (1 bit)
ND57 : ND57
bits : 25 - 25 (1 bit)
ND58 : ND58
bits : 26 - 26 (1 bit)
ND59 : ND59
bits : 27 - 27 (1 bit)
ND60 : ND60
bits : 28 - 28 (1 bit)
ND61 : ND61
bits : 29 - 29 (1 bit)
ND62 : ND62
bits : 30 - 30 (1 bit)
ND63 : ND63
bits : 31 - 31 (1 bit)
FDCAN Rx FIFO 0 configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : F0SA
bits : 2 - 15 (14 bit)
F0S : F0S
bits : 16 - 22 (7 bit)
F0WM : F0WM
bits : 24 - 30 (7 bit)
F0OM : F0OM
bits : 31 - 31 (1 bit)
FDCAN Rx FIFO 0 status register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0FL : F0FL
bits : 0 - 6 (7 bit)
F0GI : F0GI
bits : 8 - 13 (6 bit)
F0PI : F0PI
bits : 16 - 21 (6 bit)
F0F : F0F
bits : 24 - 24 (1 bit)
RF0L : RF0L
bits : 25 - 25 (1 bit)
FDCAN Rx FIFO 0 acknowledge register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : F0AI
bits : 0 - 5 (6 bit)
FDCAN Rx buffer configuration register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : RBSA
bits : 2 - 15 (14 bit)
FDCAN Rx FIFO 1 configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : F1SA
bits : 2 - 15 (14 bit)
F1S : F1S
bits : 16 - 22 (7 bit)
F1WM : F1WM
bits : 24 - 30 (7 bit)
F1OM : F1OM
bits : 31 - 31 (1 bit)
FDCAN Rx FIFO 1 status register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : F1FL
bits : 0 - 6 (7 bit)
F1GI : F1GI
bits : 8 - 13 (6 bit)
F1PI : F1PI
bits : 16 - 21 (6 bit)
F1F : F1F
bits : 24 - 24 (1 bit)
RF1L : RF1L
bits : 25 - 25 (1 bit)
DMS : DMS
bits : 30 - 31 (2 bit)
FDCAN Rx FIFO 1 acknowledge register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : F1AI
bits : 0 - 5 (6 bit)
Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0DS : F0DS
bits : 0 - 2 (3 bit)
F1DS : F1DS
bits : 4 - 6 (3 bit)
RBDS : RBDS
bits : 8 - 10 (3 bit)
This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSJW : DSJW
bits : 0 - 3 (4 bit)
DTSEG2 : DTSEG2
bits : 4 - 7 (4 bit)
DTSEG1 : DTSEG1
bits : 8 - 12 (5 bit)
DBRP : DBRP
bits : 16 - 20 (5 bit)
TDC : TDC
bits : 23 - 23 (1 bit)
FDCAN Tx buffer configuration register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : TBSA
bits : 2 - 15 (14 bit)
NDTB : NDTB
bits : 16 - 21 (6 bit)
TFQS : TFQS
bits : 24 - 29 (6 bit)
TFQM : TFQM
bits : 30 - 30 (1 bit)
The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated).
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : TFFL
bits : 0 - 5 (6 bit)
TFGI : TFGI
bits : 8 - 12 (5 bit)
TFQPI : TFQPI
bits : 16 - 20 (5 bit)
TFQF : TFQF
bits : 21 - 21 (1 bit)
Configures the number of data bytes belonging to a Tx buffer element. Data field sizes and gt 8 bytes are intended for CAN FD operation only.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TBDS : TBDS
bits : 0 - 2 (3 bit)
FDCAN Tx buffer add request register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR : AR
bits : 0 - 31 (32 bit)
FDCAN Tx buffer cancellation request register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR : CR
bits : 0 - 31 (32 bit)
FDCAN Tx buffer transmission occurred register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TO : TO
bits : 0 - 31 (32 bit)
FDCAN Tx buffer cancellation finished register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF : CF
bits : 0 - 31 (32 bit)
FDCAN Tx buffer transmission interrupt enable register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : TIE
bits : 0 - 31 (32 bit)
FDCAN Tx buffer cancellation finished interrupt enable register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFIE : CFIE
bits : 0 - 31 (32 bit)
FDCAN Tx event FIFO configuration register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : EFSA
bits : 2 - 15 (14 bit)
EFS : EFS
bits : 16 - 21 (6 bit)
EFWM : EFWM
bits : 24 - 29 (6 bit)
FDCAN Tx event FIFO status register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : EFFL
bits : 0 - 5 (6 bit)
EFGI : EFGI
bits : 8 - 12 (5 bit)
EFPI : EFPI
bits : 16 - 20 (5 bit)
EFF : EFF
bits : 24 - 24 (1 bit)
TEFL : TEFL
bits : 25 - 25 (1 bit)
FDCAN Tx event FIFO acknowledge register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : EFAI
bits : 0 - 4 (5 bit)
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