Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
GICD_IPRIORITYR0 (IPRIORITYR0)
GICD_IPRIORITYR1 (IPRIORITYR1)
GICD_IPRIORITYR2 (IPRIORITYR2)
GICD_IPRIORITYR3 (IPRIORITYR3)
GICD_IPRIORITYR4 (IPRIORITYR4)
GICD_IPRIORITYR5 (IPRIORITYR5)
GICD_IPRIORITYR6 (IPRIORITYR6)
GICD_IPRIORITYR7 (IPRIORITYR7)
GICD_IPRIORITYR8 (IPRIORITYR8)
GICD_IPRIORITYR9 (IPRIORITYR9)
GICD_IPRIORITYR10 (IPRIORITYR10)
GICD_IPRIORITYR11 (IPRIORITYR11)
GICD_IPRIORITYR12 (IPRIORITYR12)
GICD_IPRIORITYR13 (IPRIORITYR13)
GICD_IPRIORITYR14 (IPRIORITYR14)
GICD_IPRIORITYR15 (IPRIORITYR15)
GICD_IPRIORITYR16 (IPRIORITYR16)
GICD_IPRIORITYR17 (IPRIORITYR17)
GICD_IPRIORITYR18 (IPRIORITYR18)
GICD_IPRIORITYR19 (IPRIORITYR19)
GICD_IPRIORITYR20 (IPRIORITYR20)
GICD_IPRIORITYR21 (IPRIORITYR21)
GICD_IPRIORITYR22 (IPRIORITYR22)
GICD_IPRIORITYR23 (IPRIORITYR23)
GICD_IPRIORITYR24 (IPRIORITYR24)
GICD_IPRIORITYR25 (IPRIORITYR25)
GICD_IPRIORITYR26 (IPRIORITYR26)
GICD_IPRIORITYR27 (IPRIORITYR27)
GICD_IPRIORITYR28 (IPRIORITYR28)
GICD_IPRIORITYR29 (IPRIORITYR29)
GICD_IPRIORITYR30 (IPRIORITYR30)
GICD_IPRIORITYR31 (IPRIORITYR31)
GICD_IPRIORITYR32 (IPRIORITYR32)
GICD_IPRIORITYR33 (IPRIORITYR33)
GICD_IPRIORITYR34 (IPRIORITYR34)
GICD_IPRIORITYR35 (IPRIORITYR35)
GICD_IPRIORITYR36 (IPRIORITYR36)
GICD_IPRIORITYR37 (IPRIORITYR37)
GICD_IPRIORITYR38 (IPRIORITYR38)
GICD_IPRIORITYR39 (IPRIORITYR39)
GICD_IPRIORITYR40 (IPRIORITYR40)
GICD_IPRIORITYR41 (IPRIORITYR41)
GICD_IPRIORITYR42 (IPRIORITYR42)
GICD_IPRIORITYR43 (IPRIORITYR43)
GICD_IPRIORITYR44 (IPRIORITYR44)
GICD_IPRIORITYR45 (IPRIORITYR45)
GICD_IPRIORITYR46 (IPRIORITYR46)
GICD_IPRIORITYR47 (IPRIORITYR47)
GICD_IPRIORITYR48 (IPRIORITYR48)
GICD_IPRIORITYR49 (IPRIORITYR49)
GICD_IPRIORITYR50 (IPRIORITYR50)
GICD_IPRIORITYR51 (IPRIORITYR51)
GICD_IPRIORITYR52 (IPRIORITYR52)
GICD_IPRIORITYR53 (IPRIORITYR53)
GICD_IPRIORITYR54 (IPRIORITYR54)
GICD_IPRIORITYR55 (IPRIORITYR55)
GICD_IPRIORITYR56 (IPRIORITYR56)
GICD_IPRIORITYR57 (IPRIORITYR57)
GICD_IPRIORITYR58 (IPRIORITYR58)
GICD_IPRIORITYR59 (IPRIORITYR59)
GICD_IPRIORITYR60 (IPRIORITYR60)
GICD_IPRIORITYR61 (IPRIORITYR61)
GICD_IPRIORITYR62 (IPRIORITYR62)
GICD_IPRIORITYR63 (IPRIORITYR63)
GICD_IPRIORITYR64 (IPRIORITYR64)
GICD_IPRIORITYR65 (IPRIORITYR65)
GICD_IPRIORITYR66 (IPRIORITYR66)
GICD_IPRIORITYR67 (IPRIORITYR67)
GICD_IPRIORITYR68 (IPRIORITYR68)
GICD_IPRIORITYR69 (IPRIORITYR69)
GICD_IPRIORITYR70 (IPRIORITYR70)
GICD_IPRIORITYR71 (IPRIORITYR71)
GICD_ITARGETSR10 (ITARGETSR10)
GICD_ITARGETSR11 (ITARGETSR11)
GICD_ITARGETSR12 (ITARGETSR12)
GICD_ITARGETSR13 (ITARGETSR13)
GICD_ITARGETSR14 (ITARGETSR14)
GICD_ITARGETSR15 (ITARGETSR15)
GICD_ITARGETSR16 (ITARGETSR16)
GICD_ITARGETSR17 (ITARGETSR17)
GICD_ITARGETSR18 (ITARGETSR18)
GICD_ITARGETSR19 (ITARGETSR19)
GICD_ITARGETSR20 (ITARGETSR20)
GICD_ITARGETSR21 (ITARGETSR21)
GICD_ITARGETSR22 (ITARGETSR22)
GICD_ITARGETSR23 (ITARGETSR23)
GICD_ITARGETSR24 (ITARGETSR24)
GICD_ITARGETSR25 (ITARGETSR25)
GICD_ITARGETSR26 (ITARGETSR26)
GICD_ITARGETSR27 (ITARGETSR27)
GICD_ITARGETSR28 (ITARGETSR28)
GICD_ITARGETSR29 (ITARGETSR29)
GICD_ITARGETSR30 (ITARGETSR30)
GICD_ITARGETSR31 (ITARGETSR31)
GICD_ITARGETSR32 (ITARGETSR32)
GICD_ITARGETSR33 (ITARGETSR33)
GICD_ITARGETSR34 (ITARGETSR34)
GICD_ITARGETSR35 (ITARGETSR35)
GICD_ITARGETSR36 (ITARGETSR36)
GICD_ITARGETSR37 (ITARGETSR37)
GICD_ITARGETSR38 (ITARGETSR38)
GICD_ITARGETSR39 (ITARGETSR39)
GICD_ITARGETSR40 (ITARGETSR40)
GICD_ITARGETSR41 (ITARGETSR41)
GICD_ITARGETSR42 (ITARGETSR42)
GICD_ITARGETSR43 (ITARGETSR43)
GICD_ITARGETSR44 (ITARGETSR44)
GICD_ITARGETSR45 (ITARGETSR45)
GICD_ITARGETSR46 (ITARGETSR46)
GICD_ITARGETSR47 (ITARGETSR47)
GICD_ITARGETSR48 (ITARGETSR48)
GICD_ITARGETSR49 (ITARGETSR49)
GICD_ITARGETSR50 (ITARGETSR50)
GICD_ITARGETSR51 (ITARGETSR51)
GICD_ITARGETSR52 (ITARGETSR52)
GICD_ITARGETSR53 (ITARGETSR53)
GICD_ITARGETSR54 (ITARGETSR54)
GICD_ITARGETSR55 (ITARGETSR55)
GICD_ITARGETSR56 (ITARGETSR56)
GICD_ITARGETSR57 (ITARGETSR57)
GICD_ITARGETSR58 (ITARGETSR58)
GICD_ITARGETSR59 (ITARGETSR59)
GICD_ITARGETSR60 (ITARGETSR60)
GICD_ITARGETSR61 (ITARGETSR61)
GICD_ITARGETSR62 (ITARGETSR62)
GICD_ITARGETSR63 (ITARGETSR63)
GICD_ITARGETSR64 (ITARGETSR64)
GICD_ITARGETSR65 (ITARGETSR65)
GICD_ITARGETSR66 (ITARGETSR66)
GICD_ITARGETSR67 (ITARGETSR67)
GICD_ITARGETSR68 (ITARGETSR68)
GICD_ITARGETSR69 (ITARGETSR69)
GICD_ITARGETSR70 (ITARGETSR70)
GICD_ITARGETSR71 (ITARGETSR71)
GICD control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLEGRP0 : ENABLEGRP0
bits : 0 - 0 (1 bit)
ENABLEGRP1 : ENABLEGRP1
bits : 1 - 1 (1 bit)
For interrupts ID = 0 to ID = 31
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER0 : ISENABLER0
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER1 : ISENABLER1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER2 : ISENABLER2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER3 : ISENABLER3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER4 : ISENABLER4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER5 : ISENABLER5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER6 : ISENABLER6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER7 : ISENABLER7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISENABLER8 : ISENABLER8
bits : 0 - 31 (32 bit)
For interrupts ID = 0 to ID = 31
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER0 : ICENABLER0
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER1 : ICENABLER1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER2 : ICENABLER2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER3 : ICENABLER3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER4 : ICENABLER4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER5 : ICENABLER5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER6 : ICENABLER6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER7 : ICENABLER7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICENABLER8 : ICENABLER8
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR0 : ISPENDR0
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR1 : ISPENDR1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR2 : ISPENDR2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR3 : ISPENDR3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR4 : ISPENDR4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR5 : ISPENDR5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR6 : ISPENDR6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR7 : ISPENDR7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPENDR8 : ISPENDR8
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR0 : ICPENDR0
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR1 : ICPENDR1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR2 : ICPENDR2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR3 : ICPENDR3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR4 : ICPENDR4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR5 : ICPENDR5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR6 : ICPENDR6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR7 : ICPENDR7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICPENDR8 : ICPENDR8
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER0 : ISACTIVER0
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER1 : ISACTIVER1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER2 : ISACTIVER2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER3 : ISACTIVER3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER4 : ISACTIVER4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER5 : ISACTIVER5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER6 : ISACTIVER6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER7 : ISACTIVER7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISACTIVER8 : ISACTIVER8
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER0 : ICACTIVER0
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER1 : ICACTIVER1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER2 : ICACTIVER2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER3 : ICACTIVER3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER4 : ICACTIVER4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER5 : ICACTIVER5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER6 : ICACTIVER6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER7 : ICACTIVER7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICACTIVER8 : ICACTIVER8
bits : 0 - 31 (32 bit)
GICD interrupt controller type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ITLINESNUMBER : ITLINESNUMBER
bits : 0 - 4 (5 bit)
CPUNUMBER : CPUNUMBER
bits : 5 - 7 (3 bit)
SECURITYEXTN : SECURITYEXTN
bits : 10 - 10 (1 bit)
LSPI : LSPI
bits : 11 - 15 (5 bit)
GICD interrupt priority register 0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 1
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 2
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 3
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 4
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 5
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 6
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 7
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 8
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 9
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 10
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 11
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 12
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 13
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 14
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 15
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 16
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 17
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 18
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 19
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 20
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 21
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 22
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 23
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 24
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 25
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 26
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 27
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 28
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 29
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 30
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 31
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 32
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 33
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 34
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 35
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 36
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 37
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 38
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 39
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 40
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 41
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 42
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 43
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 44
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 45
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 46
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 47
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 48
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 49
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 50
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 51
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 52
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 53
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 54
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 55
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 56
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 57
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 58
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 59
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 60
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 61
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 62
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 63
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 64
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 65
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 66
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 67
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 68
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 69
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 70
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD interrupt priority register 71
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIORITY0 : PRIORITY0
bits : 3 - 7 (5 bit)
PRIORITY1 : PRIORITY1
bits : 11 - 15 (5 bit)
PRIORITY2 : PRIORITY2
bits : 19 - 23 (5 bit)
PRIORITY3 : PRIORITY3
bits : 27 - 31 (5 bit)
GICD implementer identification register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMPLEMENTER : IMPLEMENTER
bits : 0 - 11 (12 bit)
VARIANT : VARIANT
bits : 12 - 15 (4 bit)
REVISION : REVISION
bits : 16 - 19 (4 bit)
PRODUCTID : PRODUCTID
bits : 24 - 31 (8 bit)
For interrupts ID
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR0 : IGROUPR0
bits : 0 - 31 (32 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 8
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 9
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 10
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 11
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 12
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 13
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 14
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 15
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For interrupts ID
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR1 : IGROUPR1
bits : 0 - 31 (32 bit)
GICD interrupt processor target register 16
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 17
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 18
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 19
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 20
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 21
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 22
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 23
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 24
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 25
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 26
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 27
address_offset : 0x86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 28
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 29
address_offset : 0x874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 30
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 31
address_offset : 0x87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For interrupts ID
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR2 : IGROUPR2
bits : 0 - 31 (32 bit)
GICD interrupt processor target register 32
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 33
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 34
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 35
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 36
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 37
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 38
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 39
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 40
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 41
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 42
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 43
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 44
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 45
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 46
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 47
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For interrupts ID = x*32 to ID = x*32+31
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR3 : IGROUPR3
bits : 0 - 31 (32 bit)
GICD interrupt processor target register 48
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 49
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 50
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 51
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 52
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 53
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 54
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 55
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 56
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 57
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 58
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 59
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 60
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 61
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 62
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 63
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For interrupts ID = x*32 to ID = x*32+31
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR4 : IGROUPR4
bits : 0 - 31 (32 bit)
GICD interrupt processor target register 64
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 65
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 66
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 67
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 68
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 69
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 70
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
GICD interrupt processor target register 71
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_TARGETS0 : CPU_TARGETS0
bits : 0 - 1 (2 bit)
CPU_TARGETS1 : CPU_TARGETS1
bits : 8 - 9 (2 bit)
CPU_TARGETS2 : CPU_TARGETS2
bits : 16 - 17 (2 bit)
CPU_TARGETS3 : CPU_TARGETS3
bits : 24 - 25 (2 bit)
For interrupts ID
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR5 : IGROUPR5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR6 : IGROUPR6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR7 : IGROUPR7
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IGROUPR8 : IGROUPR8
bits : 0 - 31 (32 bit)
GICD interrupt configuration register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 2
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 3
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 4
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 5
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 6
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 7
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 8
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 9
address_offset : 0xC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 10
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 11
address_offset : 0xC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 12
address_offset : 0xC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 13
address_offset : 0xC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 14
address_offset : 0xC38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 15
address_offset : 0xC3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 16
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD interrupt configuration register 17
address_offset : 0xC44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_CONFIG0 : INT_CONFIG0
bits : 0 - 1 (2 bit)
INT_CONFIG1 : INT_CONFIG1
bits : 2 - 3 (2 bit)
INT_CONFIG2 : INT_CONFIG2
bits : 4 - 5 (2 bit)
INT_CONFIG3 : INT_CONFIG3
bits : 6 - 7 (2 bit)
INT_CONFIG4 : INT_CONFIG4
bits : 8 - 9 (2 bit)
INT_CONFIG5 : INT_CONFIG5
bits : 10 - 11 (2 bit)
INT_CONFIG6 : INT_CONFIG6
bits : 12 - 13 (2 bit)
INT_CONFIG7 : INT_CONFIG7
bits : 14 - 15 (2 bit)
INT_CONFIG8 : INT_CONFIG8
bits : 16 - 17 (2 bit)
INT_CONFIG9 : INT_CONFIG9
bits : 18 - 19 (2 bit)
INT_CONFIG10 : INT_CONFIG10
bits : 20 - 21 (2 bit)
INT_CONFIG11 : INT_CONFIG11
bits : 22 - 23 (2 bit)
INT_CONFIG12 : INT_CONFIG12
bits : 24 - 25 (2 bit)
INT_CONFIG13 : INT_CONFIG13
bits : 26 - 27 (2 bit)
INT_CONFIG14 : INT_CONFIG14
bits : 28 - 29 (2 bit)
INT_CONFIG15 : INT_CONFIG15
bits : 30 - 31 (2 bit)
GICD private peripheral interrupt status register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPI6 : PPI6
bits : 9 - 9 (1 bit)
PPI5 : PPI5
bits : 10 - 10 (1 bit)
PPI4 : PPI4
bits : 11 - 11 (1 bit)
PPI0 : PPI0
bits : 12 - 12 (1 bit)
PPI1 : PPI1
bits : 13 - 13 (1 bit)
PPI2 : PPI2
bits : 14 - 14 (1 bit)
PPI3 : PPI3
bits : 15 - 15 (1 bit)
For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32]
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR1 : SPISR1
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR2 : SPISR2
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR3 : SPISR3
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR4 : SPISR4
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR5 : SPISR5
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR6 : SPISR6
bits : 0 - 31 (32 bit)
For interrupts ID
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPISR7 : SPISR7
bits : 0 - 31 (32 bit)
GICD software generated interrupt register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SGIINTID : SGIINTID
bits : 0 - 3 (4 bit)
NSATT : NSATT
bits : 15 - 15 (1 bit)
CPUTARGETLIST : CPUTARGETLIST
bits : 16 - 17 (2 bit)
TARGETLISTFILTER : TARGETLISTFILTER
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : SGI_CLEAR_PENDING0
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : SGI_CLEAR_PENDING1
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : SGI_CLEAR_PENDING2
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : SGI_CLEAR_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : SGI_CLEAR_PENDING0
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : SGI_CLEAR_PENDING1
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : SGI_CLEAR_PENDING2
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : SGI_CLEAR_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : SGI_CLEAR_PENDING0
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : SGI_CLEAR_PENDING1
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : SGI_CLEAR_PENDING2
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : SGI_CLEAR_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_CLEAR_PENDING0 : SGI_CLEAR_PENDING0
bits : 0 - 1 (2 bit)
SGI_CLEAR_PENDING1 : SGI_CLEAR_PENDING1
bits : 8 - 9 (2 bit)
SGI_CLEAR_PENDING2 : SGI_CLEAR_PENDING2
bits : 16 - 17 (2 bit)
SGI_CLEAR_PENDING3 : SGI_CLEAR_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : SGI_SET_PENDING0
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : SGI_SET_PENDING1
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : SGI_SET_PENDING2
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : SGI_SET_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : SGI_SET_PENDING0
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : SGI_SET_PENDING1
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : SGI_SET_PENDING2
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : SGI_SET_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : SGI_SET_PENDING0
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : SGI_SET_PENDING1
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : SGI_SET_PENDING2
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : SGI_SET_PENDING3
bits : 24 - 25 (2 bit)
For SGI x*4 to SGI x*4+3
address_offset : 0xF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGI_SET_PENDING0 : SGI_SET_PENDING0
bits : 0 - 1 (2 bit)
SGI_SET_PENDING1 : SGI_SET_PENDING1
bits : 8 - 9 (2 bit)
SGI_SET_PENDING2 : SGI_SET_PENDING2
bits : 16 - 17 (2 bit)
SGI_SET_PENDING3 : SGI_SET_PENDING3
bits : 24 - 25 (2 bit)
GICD peripheral ID4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR4 : PIDR4
bits : 0 - 31 (32 bit)
GICD peripheral ID5 to ID7 register 5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR5 : PIDR5
bits : 0 - 31 (32 bit)
GICD peripheral ID5 to ID7 register 6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR6 : PIDR6
bits : 0 - 31 (32 bit)
GICD peripheral ID5 to ID7 register 7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR7 : PIDR7
bits : 0 - 31 (32 bit)
GICD peripheral ID0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR0 : PIDR0
bits : 0 - 31 (32 bit)
GICD peripheral ID1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR1 : PIDR1
bits : 0 - 31 (32 bit)
GICD peripheral ID2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR2 : PIDR2
bits : 0 - 31 (32 bit)
GICD peripheral ID3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR3 : PIDR3
bits : 0 - 31 (32 bit)
GICD component ID0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR0 : CIDR0
bits : 0 - 31 (32 bit)
GICD component ID1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR1 : CIDR1
bits : 0 - 31 (32 bit)
GICD component ID2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR2 : CIDR2
bits : 0 - 31 (32 bit)
GICD component ID3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIDR3 : CIDR3
bits : 0 - 31 (32 bit)
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