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GICC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

GICC_CTLR (CTLR)

GICC_EOIR (EOIR)

GICC_DIR (DIR)

GICC_RPR (RPR)

GICC_HPPIR (HPPIR)

GICC_ABPR (ABPR)

GICC_AIAR (AIAR)

GICC_AEOIR (AEOIR)

GICC_AHPPIR (AHPPIR)

GICC_PMR (PMR)

GICC_BPR (BPR)

GICC_IAR (IAR)

GICC_APR0 (APR0)

GICC_NSAPR0 (NSAPR0)

GICC_IIDR (IIDR)


GICC_CTLR (CTLR)

GICC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICC_CTLR GICC_CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLEGRP0 ENABLEGRP1 ACKCTL FIQEN CBPR FIQBYPDISGRP0 IRQBYPDISGRP0 FIQBYPDISGRP1 IRQBYPDISGRP1 EOIMODES EOIMODENS

ENABLEGRP0 : ENABLEGRP0
bits : 0 - 0 (1 bit)

ENABLEGRP1 : ENABLEGRP1
bits : 1 - 1 (1 bit)

ACKCTL : ACKCTL
bits : 2 - 2 (1 bit)

FIQEN : FIQEN
bits : 3 - 3 (1 bit)

CBPR : CBPR
bits : 4 - 4 (1 bit)

FIQBYPDISGRP0 : FIQBYPDISGRP0
bits : 5 - 5 (1 bit)

IRQBYPDISGRP0 : IRQBYPDISGRP0
bits : 6 - 6 (1 bit)

FIQBYPDISGRP1 : FIQBYPDISGRP1
bits : 7 - 7 (1 bit)

IRQBYPDISGRP1 : IRQBYPDISGRP1
bits : 8 - 8 (1 bit)

EOIMODES : EOIMODES
bits : 9 - 9 (1 bit)

EOIMODENS : EOIMODENS
bits : 10 - 10 (1 bit)


GICC_EOIR (EOIR)

GICC end of interrupt register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICC_EOIR GICC_EOIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIINTID CPUID

EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_DIR (DIR)

GICC deactivate interrupt register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICC_DIR GICC_DIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_RPR (RPR)

GICC running priority register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICC_RPR GICC_RPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY

PRIORITY : PRIORITY
bits : 3 - 7 (5 bit)


GICC_HPPIR (HPPIR)

GICC highest priority pending interrupt register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICC_HPPIR GICC_HPPIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDINTID CPUID

PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_ABPR (ABPR)

GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICC_ABPR GICC_ABPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


GICC_AIAR (AIAR)

GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICC_AIAR GICC_AIAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_AEOIR (AEOIR)

GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICC_AEOIR GICC_AEOIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIINTID CPUID

EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_AHPPIR (AHPPIR)

ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICC_AHPPIR GICC_AHPPIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDINTID CPUID

PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_PMR (PMR)

GICC input priority mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICC_PMR GICC_PMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY

PRIORITY : PRIORITY
bits : 3 - 7 (5 bit)


GICC_BPR (BPR)

GICC binary point register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICC_BPR GICC_BPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


GICC_IAR (IAR)

GICC interrupt acknowledge register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICC_IAR GICC_IAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICC_APR0 (APR0)

GICC active priority register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICC_APR0 GICC_APR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APR0

APR0 : APR0
bits : 0 - 31 (32 bit)


GICC_NSAPR0 (NSAPR0)

GICC non-secure active priority register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICC_NSAPR0 GICC_NSAPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAPR0

NSAPR0 : NSAPR0
bits : 0 - 31 (32 bit)


GICC_IIDR (IIDR)

GICC interface identification register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICC_IIDR GICC_IIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMPLEMENTER REVISION ARCH PRODUCTID

IMPLEMENTER : IMPLEMENTER
bits : 0 - 11 (12 bit)

REVISION : REVISION
bits : 12 - 15 (4 bit)

ARCH : ARCH
bits : 16 - 19 (4 bit)

PRODUCTID : PRODUCTID
bits : 20 - 31 (12 bit)



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