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GICH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

GICH_HCR (HCR)

GICH_MISR (MISR)

GICH_LR0 (LR0)

GICH_LR1 (LR1)

GICH_LR2 (LR2)

GICH_LR3 (LR3)

GICH_EISR0 (EISR0)

GICH_ELSR0 (ELSR0)

GICH_VTR (VTR)

GICH_VMCR (VMCR)

GICH_APR0 (APR0)


GICH_HCR (HCR)

GICH hypervisor control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_HCR GICH_HCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UIE LRENPIE NPIE VGRP0EIE VGRP0DIE VGRP1EIE VGRP1DIE EOICOUNT

EN : EN
bits : 0 - 0 (1 bit)

UIE : UIE
bits : 1 - 1 (1 bit)

LRENPIE : LRENPIE
bits : 2 - 2 (1 bit)

NPIE : NPIE
bits : 3 - 3 (1 bit)

VGRP0EIE : VGRP0EIE
bits : 4 - 4 (1 bit)

VGRP0DIE : VGRP0DIE
bits : 5 - 5 (1 bit)

VGRP1EIE : VGRP1EIE
bits : 6 - 6 (1 bit)

VGRP1DIE : VGRP1DIE
bits : 7 - 7 (1 bit)

EOICOUNT : EOICOUNT
bits : 27 - 31 (5 bit)


GICH_MISR (MISR)

GICH maintenance interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICH_MISR GICH_MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOI U LRENP NP VGRP0E VGRP0D VGRP1E VGRP1D

EOI : EOI
bits : 0 - 0 (1 bit)

U : U
bits : 1 - 1 (1 bit)

LRENP : LRENP
bits : 2 - 2 (1 bit)

NP : NP
bits : 3 - 3 (1 bit)

VGRP0E : VGRP0E
bits : 4 - 4 (1 bit)

VGRP0D : VGRP0D
bits : 5 - 5 (1 bit)

VGRP1E : VGRP1E
bits : 6 - 6 (1 bit)

VGRP1D : VGRP1D
bits : 7 - 7 (1 bit)


GICH_LR0 (LR0)

GICH list register 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_LR0 GICH_LR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : VIRTUALID
bits : 0 - 9 (10 bit)

PHYSICALID : PHYSICALID
bits : 10 - 19 (10 bit)

PRIORITY : PRIORITY
bits : 23 - 27 (5 bit)

STATE : STATE
bits : 28 - 29 (2 bit)

GRP1 : GRP1
bits : 30 - 30 (1 bit)

HW : HW
bits : 31 - 31 (1 bit)


GICH_LR1 (LR1)

GICH list register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_LR1 GICH_LR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : VIRTUALID
bits : 0 - 9 (10 bit)

PHYSICALID : PHYSICALID
bits : 10 - 19 (10 bit)

PRIORITY : PRIORITY
bits : 23 - 27 (5 bit)

STATE : STATE
bits : 28 - 29 (2 bit)

GRP1 : GRP1
bits : 30 - 30 (1 bit)

HW : HW
bits : 31 - 31 (1 bit)


GICH_LR2 (LR2)

GICH list register 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_LR2 GICH_LR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : VIRTUALID
bits : 0 - 9 (10 bit)

PHYSICALID : PHYSICALID
bits : 10 - 19 (10 bit)

PRIORITY : PRIORITY
bits : 23 - 27 (5 bit)

STATE : STATE
bits : 28 - 29 (2 bit)

GRP1 : GRP1
bits : 30 - 30 (1 bit)

HW : HW
bits : 31 - 31 (1 bit)


GICH_LR3 (LR3)

GICH list register 3
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_LR3 GICH_LR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIRTUALID PHYSICALID PRIORITY STATE GRP1 HW

VIRTUALID : VIRTUALID
bits : 0 - 9 (10 bit)

PHYSICALID : PHYSICALID
bits : 10 - 19 (10 bit)

PRIORITY : PRIORITY
bits : 23 - 27 (5 bit)

STATE : STATE
bits : 28 - 29 (2 bit)

GRP1 : GRP1
bits : 30 - 30 (1 bit)

HW : HW
bits : 31 - 31 (1 bit)


GICH_EISR0 (EISR0)

GICH end of interrupt status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICH_EISR0 GICH_EISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EISR0

EISR0 : EISR0
bits : 0 - 31 (32 bit)


GICH_ELSR0 (ELSR0)

GICH empty list status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICH_ELSR0 GICH_ELSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELSR0

ELSR0 : ELSR0
bits : 0 - 31 (32 bit)


GICH_VTR (VTR)

GICH VGIC type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICH_VTR GICH_VTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LISTREGS PREBITS PRIBITS

LISTREGS : LISTREGS
bits : 0 - 4 (5 bit)

PREBITS : PREBITS
bits : 26 - 28 (3 bit)

PRIBITS : PRIBITS
bits : 29 - 31 (3 bit)


GICH_VMCR (VMCR)

GICH virtual machine control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_VMCR GICH_VMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMGRP0EN VMGRP1EN VMACKCTL VMFIQEN VMCBPR VEM VMABP VMBP VMPRIMASK

VMGRP0EN : VMGRP0EN
bits : 0 - 0 (1 bit)

VMGRP1EN : VMGRP1EN
bits : 1 - 1 (1 bit)

VMACKCTL : VMACKCTL
bits : 2 - 2 (1 bit)

VMFIQEN : VMFIQEN
bits : 3 - 3 (1 bit)

VMCBPR : VMCBPR
bits : 4 - 4 (1 bit)

VEM : VEM
bits : 9 - 9 (1 bit)

VMABP : VMABP
bits : 18 - 20 (3 bit)

VMBP : VMBP
bits : 21 - 23 (3 bit)

VMPRIMASK : VMPRIMASK
bits : 27 - 31 (5 bit)


GICH_APR0 (APR0)

GICH active priority register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICH_APR0 GICH_APR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APR0

APR0 : APR0
bits : 0 - 31 (32 bit)



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