\n

GICV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

GICV_CTLR (CTLR)

GICV_EOIR (EOIR)

GICV_DIR (DIR)

GICV_RPR (RPR)

GICV_HPPIR (HPPIR)

GICV_ABPR (ABPR)

GICV_AIAR (AIAR)

GICV_AEOIR (AEOIR)

GICV_AHPPIR (AHPPIR)

GICV_PMR (PMR)

GICV_BPR (BPR)

GICV_IAR (IAR)

GICV_APR0 (APR0)

GICV_IIDR (IIDR)


GICV_CTLR (CTLR)

GICV virtual machine control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICV_CTLR GICV_CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLEGRP0 ENABLEGRP1 ACKCTL FIQEN CBPR EOIMODE

ENABLEGRP0 : ENABLEGRP0
bits : 0 - 0 (1 bit)

ENABLEGRP1 : ENABLEGRP1
bits : 1 - 1 (1 bit)

ACKCTL : ACKCTL
bits : 2 - 2 (1 bit)

FIQEN : FIQEN
bits : 3 - 3 (1 bit)

CBPR : CBPR
bits : 4 - 4 (1 bit)

EOIMODE : EOIMODE
bits : 9 - 9 (1 bit)


GICV_EOIR (EOIR)

GICV VM end of interrupt register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICV_EOIR GICV_EOIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIINTID CPUID

EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_DIR (DIR)

GICV VM deactivate interrupt register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICV_DIR GICV_DIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_RPR (RPR)

GICV VM running priority register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICV_RPR GICV_RPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY

PRIORITY : PRIORITY
bits : 3 - 7 (5 bit)


GICV_HPPIR (HPPIR)

GICV VM highest priority pending interrupt register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICV_HPPIR GICV_HPPIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDINTID CPUID

PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_ABPR (ABPR)

GICV VM aliased binary point register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICV_ABPR GICV_ABPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


GICV_AIAR (AIAR)

GICV VM aliased interrupt register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICV_AIAR GICV_AIAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_AEOIR (AEOIR)

GICV VM aliased end of interrupt register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICV_AEOIR GICV_AEOIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIINTID CPUID

EOIINTID : EOIINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_AHPPIR (AHPPIR)

GICV VM aliased highest priority pending interrupt register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICV_AHPPIR GICV_AHPPIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDINTID CPUID

PENDINTID : PENDINTID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_PMR (PMR)

GICV VM priority mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICV_PMR GICV_PMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY

PRIORITY : PRIORITY
bits : 3 - 7 (5 bit)


GICV_BPR (BPR)

GICV VM binary point register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICV_BPR GICV_BPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY_POINT

BINARY_POINT : BINARY_POINT
bits : 0 - 2 (3 bit)


GICV_IAR (IAR)

GICV VM interrupt acknowledge register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICV_IAR GICV_IAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERRUPT_ID CPUID

INTERRUPT_ID : INTERRUPT_ID
bits : 0 - 9 (10 bit)

CPUID : CPUID
bits : 10 - 10 (1 bit)


GICV_APR0 (APR0)

The GICV_APR0 is an alias of GICH_APR.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICV_APR0 GICV_APR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APR0

APR0 : APR0
bits : 0 - 31 (32 bit)


GICV_IIDR (IIDR)

The GICV_IIDR is an alias of GICC_IIDR.
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GICV_IIDR GICV_IIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IIDR

IIDR : IIDR
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.