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TIM4

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TIM4_CR1 (CR1)

TIM4_SR (SR)

TIM4_EGR (EGR)

TIM4_CCMR1ALTERNATE4 (CCMR1ALTERNATE4)

TIM4_CCMR2ALTERNATE20 (CCMR2ALTERNATE20)

TIM4_CCER (CCER)

TIM4_CNT (CNT)

TIM4_PSC (PSC)

TIM4_ARR (ARR)

TIM4_RCR (RCR)

TIM4_CCR1 (CCR1)

TIM4_CCR2 (CCR2)

TIM4_CCR3 (CCR3)

TIM4_CR2 (CR2)

TIM4_CCR4 (CCR4)

TIM4_BDTR (BDTR)

TIM4_DCR (DCR)

TIM4_DMAR (DMAR)

TIM4_CCMR3 (CCMR3)

TIM4_CCR5 (CCR5)

TIM4_CCR6 (CCR6)

TIM4_SMCR (SMCR)

TIM4_DIER (DIER)


TIM4_CR1 (CR1)

TIM4 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CR1 TIM4_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM DIR CMS ARPE CKD UIFREMAP

CEN : CEN
bits : 0 - 0 (1 bit)

UDIS : UDIS
bits : 1 - 1 (1 bit)

URS : URS
bits : 2 - 2 (1 bit)

OPM : OPM
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CMS : CMS
bits : 5 - 6 (2 bit)

ARPE : ARPE
bits : 7 - 7 (1 bit)

CKD : CKD
bits : 8 - 9 (2 bit)

UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)


TIM4_SR (SR)

TIM4 status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_SR TIM4_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF CC3IF CC4IF COMIF TIF BIF B2IF CC1OF CC2OF CC3OF CC4OF SBIF CC5IF CC6IF

UIF : UIF
bits : 0 - 0 (1 bit)

CC1IF : CC1IF
bits : 1 - 1 (1 bit)

CC2IF : CC2IF
bits : 2 - 2 (1 bit)

CC3IF : CC3IF
bits : 3 - 3 (1 bit)

CC4IF : CC4IF
bits : 4 - 4 (1 bit)

COMIF : COMIF
bits : 5 - 5 (1 bit)

TIF : TIF
bits : 6 - 6 (1 bit)

BIF : BIF
bits : 7 - 7 (1 bit)

B2IF : B2IF
bits : 8 - 8 (1 bit)

CC1OF : CC1OF
bits : 9 - 9 (1 bit)

CC2OF : CC2OF
bits : 10 - 10 (1 bit)

CC3OF : CC3OF
bits : 11 - 11 (1 bit)

CC4OF : CC4OF
bits : 12 - 12 (1 bit)

SBIF : SBIF
bits : 13 - 13 (1 bit)

CC5IF : CC5IF
bits : 16 - 16 (1 bit)

CC6IF : CC6IF
bits : 17 - 17 (1 bit)


TIM4_EGR (EGR)

TIM4 event generation register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TIM4_EGR TIM4_EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G CC3G CC4G COMG TG BG B2G

UG : UG
bits : 0 - 0 (1 bit)

CC1G : CC1G
bits : 1 - 1 (1 bit)

CC2G : CC2G
bits : 2 - 2 (1 bit)

CC3G : CC3G
bits : 3 - 3 (1 bit)

CC4G : CC4G
bits : 4 - 4 (1 bit)

COMG : COMG
bits : 5 - 5 (1 bit)

TG : TG
bits : 6 - 6 (1 bit)

BG : BG
bits : 7 - 7 (1 bit)

B2G : B2G
bits : 8 - 8 (1 bit)


TIM4_CCMR1ALTERNATE4 (CCMR1ALTERNATE4)

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCMR1ALTERNATE4 TIM4_CCMR1ALTERNATE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S IC1PSC IC1F CC2S IC2PSC IC2F

CC1S : CC1S
bits : 0 - 1 (2 bit)

IC1PSC : IC1PSC
bits : 2 - 3 (2 bit)

IC1F : IC1F
bits : 4 - 7 (4 bit)

CC2S : CC2S
bits : 8 - 9 (2 bit)

IC2PSC : IC2PSC
bits : 10 - 11 (2 bit)

IC2F : IC2F
bits : 12 - 15 (4 bit)


TIM4_CCMR2ALTERNATE20 (CCMR2ALTERNATE20)

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCMR2ALTERNATE20 TIM4_CCMR2ALTERNATE20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S IC3PSC IC3F CC4S IC4PSC IC4F

CC3S : CC3S
bits : 0 - 1 (2 bit)

IC3PSC : IC3PSC
bits : 2 - 3 (2 bit)

IC3F : IC3F
bits : 4 - 7 (4 bit)

CC4S : CC4S
bits : 8 - 9 (2 bit)

IC4PSC : IC4PSC
bits : 10 - 11 (2 bit)

IC4F : IC4F
bits : 12 - 15 (4 bit)


TIM4_CCER (CCER)

TIM4 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCER TIM4_CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NE CC1NP CC2E CC2P CC2NE CC2NP CC3E CC3P CC3NE CC3NP CC4E CC4P CC4NP CC5E CC5P CC6E CC6P

CC1E : CC1E
bits : 0 - 0 (1 bit)

CC1P : CC1P
bits : 1 - 1 (1 bit)

CC1NE : CC1NE
bits : 2 - 2 (1 bit)

CC1NP : CC1NP
bits : 3 - 3 (1 bit)

CC2E : CC2E
bits : 4 - 4 (1 bit)

CC2P : CC2P
bits : 5 - 5 (1 bit)

CC2NE : CC2NE
bits : 6 - 6 (1 bit)

CC2NP : CC2NP
bits : 7 - 7 (1 bit)

CC3E : CC3E
bits : 8 - 8 (1 bit)

CC3P : CC3P
bits : 9 - 9 (1 bit)

CC3NE : CC3NE
bits : 10 - 10 (1 bit)

CC3NP : CC3NP
bits : 11 - 11 (1 bit)

CC4E : CC4E
bits : 12 - 12 (1 bit)

CC4P : CC4P
bits : 13 - 13 (1 bit)

CC4NP : CC4NP
bits : 15 - 15 (1 bit)

CC5E : CC5E
bits : 16 - 16 (1 bit)

CC5P : CC5P
bits : 17 - 17 (1 bit)

CC6E : CC6E
bits : 20 - 20 (1 bit)

CC6P : CC6P
bits : 21 - 21 (1 bit)


TIM4_CNT (CNT)

TIM4 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CNT TIM4_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT UIFCPY

CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write

UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only


TIM4_PSC (PSC)

TIM4 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_PSC TIM4_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 15 (16 bit)


TIM4_ARR (ARR)

TIM4 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_ARR TIM4_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)


TIM4_RCR (RCR)

TIM4 repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_RCR TIM4_RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP

REP : REP
bits : 0 - 15 (16 bit)


TIM4_CCR1 (CCR1)

TIM4 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCR1 TIM4_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : CCR1
bits : 0 - 15 (16 bit)


TIM4_CCR2 (CCR2)

TIM4 capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCR2 TIM4_CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : CCR2
bits : 0 - 15 (16 bit)


TIM4_CCR3 (CCR3)

TIM4 capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCR3 TIM4_CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR3

CCR3 : CCR3
bits : 0 - 15 (16 bit)


TIM4_CR2 (CR2)

TIM4 control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CR2 TIM4_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCPC CCUS CCDS MMS TI1S OIS1 OIS1N OIS2 OIS2N OIS3 OIS3N OIS4 OIS5 OIS6 MMS2

CCPC : CCPC
bits : 0 - 0 (1 bit)

CCUS : CCUS
bits : 2 - 2 (1 bit)

CCDS : CCDS
bits : 3 - 3 (1 bit)

MMS : MMS
bits : 4 - 6 (3 bit)

TI1S : TI1S
bits : 7 - 7 (1 bit)

OIS1 : OIS1
bits : 8 - 8 (1 bit)

OIS1N : OIS1N
bits : 9 - 9 (1 bit)

OIS2 : OIS2
bits : 10 - 10 (1 bit)

OIS2N : OIS2N
bits : 11 - 11 (1 bit)

OIS3 : OIS3
bits : 12 - 12 (1 bit)

OIS3N : OIS3N
bits : 13 - 13 (1 bit)

OIS4 : OIS4
bits : 14 - 14 (1 bit)

OIS5 : OIS5
bits : 16 - 16 (1 bit)

OIS6 : OIS6
bits : 18 - 18 (1 bit)

MMS2 : MMS2
bits : 20 - 23 (4 bit)


TIM4_CCR4 (CCR4)

TIM4 capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCR4 TIM4_CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR4

CCR4 : CCR4
bits : 0 - 15 (16 bit)


TIM4_BDTR (BDTR)

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_BDTR TIM4_BDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTG LOCK OSSI OSSR BKE BKP AOE MOE BKF BK2F BK2E BK2P BKDSRM BK2DSRM BKBID BK2BID

DTG : DTG
bits : 0 - 7 (8 bit)

LOCK : LOCK
bits : 8 - 9 (2 bit)

OSSI : OSSI
bits : 10 - 10 (1 bit)

OSSR : OSSR
bits : 11 - 11 (1 bit)

BKE : BKE
bits : 12 - 12 (1 bit)

BKP : BKP
bits : 13 - 13 (1 bit)

AOE : AOE
bits : 14 - 14 (1 bit)

MOE : MOE
bits : 15 - 15 (1 bit)

BKF : BKF
bits : 16 - 19 (4 bit)

BK2F : BK2F
bits : 20 - 23 (4 bit)

BK2E : BK2E
bits : 24 - 24 (1 bit)

BK2P : BK2P
bits : 25 - 25 (1 bit)

BKDSRM : BKDSRM
bits : 26 - 26 (1 bit)

BK2DSRM : BK2DSRM
bits : 27 - 27 (1 bit)

BKBID : BKBID
bits : 28 - 28 (1 bit)

BK2BID : BK2BID
bits : 29 - 29 (1 bit)


TIM4_DCR (DCR)

TIM4 DMA control register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_DCR TIM4_DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA DBL

DBA : DBA
bits : 0 - 4 (5 bit)

DBL : DBL
bits : 8 - 12 (5 bit)


TIM4_DMAR (DMAR)

TIM4 DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_DMAR TIM4_DMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAB

DMAB : DMAB
bits : 0 - 31 (32 bit)


TIM4_CCMR3 (CCMR3)

The channels 5 and 6 can only be configured in output. Output compare mode:
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCMR3 TIM4_CCMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC5FE OC5PE OC5M OC5CE OC6FE OC6PE OC6M OC6CE OC5M3 OC6M3

OC5FE : OC5FE
bits : 2 - 2 (1 bit)

OC5PE : OC5PE
bits : 3 - 3 (1 bit)

OC5M : OC5M
bits : 4 - 6 (3 bit)

OC5CE : OC5CE
bits : 7 - 7 (1 bit)

OC6FE : OC6FE
bits : 10 - 10 (1 bit)

OC6PE : OC6PE
bits : 11 - 11 (1 bit)

OC6M : OC6M
bits : 12 - 14 (3 bit)

OC6CE : OC6CE
bits : 15 - 15 (1 bit)

OC5M3 : OC5M3
bits : 16 - 16 (1 bit)

OC6M3 : OC6M3
bits : 24 - 24 (1 bit)


TIM4_CCR5 (CCR5)

TIM4 capture/compare register 5
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCR5 TIM4_CCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR5 GC5C1 GC5C2 GC5C3

CCR5 : CCR5
bits : 0 - 15 (16 bit)

GC5C1 : GC5C1
bits : 29 - 29 (1 bit)

GC5C2 : GC5C2
bits : 30 - 30 (1 bit)

GC5C3 : GC5C3
bits : 31 - 31 (1 bit)


TIM4_CCR6 (CCR6)

TIM4 capture/compare register 6
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_CCR6 TIM4_CCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR6

CCR6 : CCR6
bits : 0 - 15 (16 bit)


TIM4_SMCR (SMCR)

TIM4 slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_SMCR TIM4_SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM ETF ETPS ECE ETP SMS3 TS3 TS4

SMS : SMS
bits : 0 - 2 (3 bit)

TS : TS
bits : 4 - 6 (3 bit)

MSM : MSM
bits : 7 - 7 (1 bit)

ETF : ETF
bits : 8 - 11 (4 bit)

ETPS : ETPS
bits : 12 - 13 (2 bit)

ECE : ECE
bits : 14 - 14 (1 bit)

ETP : ETP
bits : 15 - 15 (1 bit)

SMS3 : SMS3
bits : 16 - 16 (1 bit)

TS3 : TS3
bits : 20 - 20 (1 bit)

TS4 : TS4
bits : 21 - 21 (1 bit)


TIM4_DIER (DIER)

TIM4 DMA/interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM4_DIER TIM4_DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE CC3IE CC4IE COMIE TIE BIE UDE CC1DE CC2DE CC3DE CC4DE COMDE TDE

UIE : UIE
bits : 0 - 0 (1 bit)

CC1IE : CC1IE
bits : 1 - 1 (1 bit)

CC2IE : CC2IE
bits : 2 - 2 (1 bit)

CC3IE : CC3IE
bits : 3 - 3 (1 bit)

CC4IE : CC4IE
bits : 4 - 4 (1 bit)

COMIE : COMIE
bits : 5 - 5 (1 bit)

TIE : TIE
bits : 6 - 6 (1 bit)

BIE : BIE
bits : 7 - 7 (1 bit)

UDE : UDE
bits : 8 - 8 (1 bit)

CC1DE : CC1DE
bits : 9 - 9 (1 bit)

CC2DE : CC2DE
bits : 10 - 10 (1 bit)

CC3DE : CC3DE
bits : 11 - 11 (1 bit)

CC4DE : CC4DE
bits : 12 - 12 (1 bit)

COMDE : COMDE
bits : 13 - 13 (1 bit)

TDE : TDE
bits : 14 - 14 (1 bit)



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