\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
TIM13 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
UDIS : UDIS
bits : 1 - 1 (1 bit)
URS : URS
bits : 2 - 2 (1 bit)
OPM : OPM
bits : 3 - 3 (1 bit)
ARPE : ARPE
bits : 7 - 7 (1 bit)
CKD : CKD
bits : 8 - 9 (2 bit)
UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
TIM13 status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
CC1IF : CC1IF
bits : 1 - 1 (1 bit)
CC1OF : CC1OF
bits : 9 - 9 (1 bit)
TIM13 event generation register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : UG
bits : 0 - 0 (1 bit)
CC1G : CC1G
bits : 1 - 1 (1 bit)
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : CC1S
bits : 0 - 1 (2 bit)
OC1FE : OC1FE
bits : 2 - 2 (1 bit)
OC1PE : OC1PE
bits : 3 - 3 (1 bit)
OC1M : OC1M
bits : 4 - 6 (3 bit)
OC1M3 : OC1M3
bits : 16 - 16 (1 bit)
TIM13 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : CC1E
bits : 0 - 0 (1 bit)
CC1P : CC1P
bits : 1 - 1 (1 bit)
CC1NP : CC1NP
bits : 3 - 3 (1 bit)
TIM13 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
TIM13 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC
bits : 0 - 15 (16 bit)
TIM13 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ARR
bits : 0 - 15 (16 bit)
TIM13 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : CCR1
bits : 0 - 15 (16 bit)
TIM13 timer input selection register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
TIM13 Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
CC1IE : CC1IE
bits : 1 - 1 (1 bit)
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