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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

RTC_TR (TR)

RTC_PRER (PRER)

RTC_WUTR (WUTR)

RTC_CR (CR)

RTC_SMCR (SMCR)

RTC_WPR (WPR)

RTC_CALR (CALR)

RTC_SHIFTR (SHIFTR)

RTC_TSTR (TSTR)

RTC_TSDR (TSDR)

RTC_TSSSR (TSSSR)

RTC_HWCFGR (HWCFGR)

RTC_VERR (VERR)

RTC_IPIDR (IPIDR)

RTC_SIDR (SIDR)

RTC_DR (DR)

RTC_ALRMAR (ALRMAR)

RTC_ALRMASSR (ALRMASSR)

RTC_ALRMBR (ALRMBR)

RTC_ALRMBSSR (ALRMBSSR)

RTC_SR (SR)

RTC_MISR (MISR)

RTC_SMISR (SMISR)

RTC_SCR (SCR)

RTC_CFGR (CFGR)

RTC_SSR (SSR)

RTC_ICSR (ICSR)


RTC_TR (TR)

The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TR RTC_TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MNU MNT HU HT PM

SU : SU
bits : 0 - 3 (4 bit)

ST : ST
bits : 4 - 6 (3 bit)

MNU : MNU
bits : 8 - 11 (4 bit)

MNT : MNT
bits : 12 - 14 (3 bit)

HU : HU
bits : 16 - 19 (4 bit)

HT : HT
bits : 20 - 21 (2 bit)

PM : PM
bits : 22 - 22 (1 bit)


RTC_PRER (PRER)

This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_PRER RTC_PRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDIV_S PREDIV_A

PREDIV_S : PREDIV_S
bits : 0 - 14 (15 bit)

PREDIV_A : PREDIV_A
bits : 16 - 22 (7 bit)


RTC_WUTR (WUTR)

This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_WUTR RTC_WUTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUT

WUT : WUT
bits : 0 - 15 (16 bit)


RTC_CR (CR)

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CR RTC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUCKSEL TSEDGE REFCKON BYPSHAD FMT ALRAE ALRBE WUTE TSE ALRAIE ALRBIE WUTIE TSIE ADD1H SUB1H BKP COSEL POL OSEL COE ITSE TAMPTS TAMPOE TAMPALRM_PU TAMPALRM_TYPE OUT2EN

WUCKSEL : WUCKSEL
bits : 0 - 2 (3 bit)
access : read-write

TSEDGE : TSEDGE
bits : 3 - 3 (1 bit)
access : read-write

REFCKON : REFCKON
bits : 4 - 4 (1 bit)
access : read-write

BYPSHAD : BYPSHAD
bits : 5 - 5 (1 bit)
access : read-write

FMT : FMT
bits : 6 - 6 (1 bit)
access : read-write

ALRAE : ALRAE
bits : 8 - 8 (1 bit)
access : read-write

ALRBE : ALRBE
bits : 9 - 9 (1 bit)
access : read-write

WUTE : WUTE
bits : 10 - 10 (1 bit)
access : read-write

TSE : TSE
bits : 11 - 11 (1 bit)
access : read-write

ALRAIE : ALRAIE
bits : 12 - 12 (1 bit)
access : read-write

ALRBIE : ALRBIE
bits : 13 - 13 (1 bit)
access : read-write

WUTIE : WUTIE
bits : 14 - 14 (1 bit)
access : read-write

TSIE : TSIE
bits : 15 - 15 (1 bit)
access : read-write

ADD1H : ADD1H
bits : 16 - 16 (1 bit)
access : write-only

SUB1H : SUB1H
bits : 17 - 17 (1 bit)
access : write-only

BKP : BKP
bits : 18 - 18 (1 bit)
access : read-write

COSEL : COSEL
bits : 19 - 19 (1 bit)
access : read-write

POL : POL
bits : 20 - 20 (1 bit)
access : read-write

OSEL : OSEL
bits : 21 - 22 (2 bit)
access : read-write

COE : COE
bits : 23 - 23 (1 bit)
access : read-write

ITSE : ITSE
bits : 24 - 24 (1 bit)
access : read-write

TAMPTS : TAMPTS
bits : 25 - 25 (1 bit)
access : read-write

TAMPOE : TAMPOE
bits : 26 - 26 (1 bit)
access : read-write

TAMPALRM_PU : TAMPALRM_PU
bits : 29 - 29 (1 bit)
access : read-write

TAMPALRM_TYPE : TAMPALRM_TYPE
bits : 30 - 30 (1 bit)
access : read-write

OUT2EN : OUT2EN
bits : 31 - 31 (1 bit)
access : read-write


RTC_SMCR (SMCR)

This register can be written only when the APB access is secure.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SMCR RTC_SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRADPROT ALRBDPROT WUTDPROT TSDPROT CALDPROT INITDPROT DECPROT

ALRADPROT : ALRADPROT
bits : 0 - 0 (1 bit)

ALRBDPROT : ALRBDPROT
bits : 1 - 1 (1 bit)

WUTDPROT : WUTDPROT
bits : 2 - 2 (1 bit)

TSDPROT : TSDPROT
bits : 3 - 3 (1 bit)

CALDPROT : CALDPROT
bits : 13 - 13 (1 bit)

INITDPROT : INITDPROT
bits : 14 - 14 (1 bit)

DECPROT : DECPROT
bits : 15 - 15 (1 bit)


RTC_WPR (WPR)

RTC write protection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RTC_WPR RTC_WPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 7 (8 bit)


RTC_CALR (CALR)

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CALR RTC_CALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALM CALW16 CALW8 CALP

CALM : CALM
bits : 0 - 8 (9 bit)

CALW16 : CALW16
bits : 13 - 13 (1 bit)

CALW8 : CALW8
bits : 14 - 14 (1 bit)

CALP : CALP
bits : 15 - 15 (1 bit)


RTC_SHIFTR (SHIFTR)

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RTC_SHIFTR RTC_SHIFTR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBFS ADD1S

SUBFS : SUBFS
bits : 0 - 14 (15 bit)

ADD1S : ADD1S
bits : 31 - 31 (1 bit)


RTC_TSTR (TSTR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_TSTR RTC_TSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MNU MNT HU HT PM

SU : SU
bits : 0 - 3 (4 bit)

ST : ST
bits : 4 - 6 (3 bit)

MNU : MNU
bits : 8 - 11 (4 bit)

MNT : MNT
bits : 12 - 14 (3 bit)

HU : HU
bits : 16 - 19 (4 bit)

HT : HT
bits : 20 - 21 (2 bit)

PM : PM
bits : 22 - 22 (1 bit)


RTC_TSDR (TSDR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_TSDR RTC_TSDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DU DT MU MT WDU

DU : DU
bits : 0 - 3 (4 bit)

DT : DT
bits : 4 - 5 (2 bit)

MU : MU
bits : 8 - 11 (4 bit)

MT : MT
bits : 12 - 12 (1 bit)

WDU : WDU
bits : 13 - 15 (3 bit)


RTC_TSSSR (TSSSR)

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_TSSSR RTC_TSSSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS

SS : SS
bits : 0 - 15 (16 bit)


RTC_HWCFGR (HWCFGR)

RTC hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_HWCFGR RTC_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALARMB WAKEUP SMOOTH_CALIB TIMESTAMP OPTIONREG_OUT TRUST_ZONE

ALARMB : ALARMB
bits : 0 - 3 (4 bit)

WAKEUP : WAKEUP
bits : 4 - 7 (4 bit)

SMOOTH_CALIB : SMOOTH_CALIB
bits : 8 - 11 (4 bit)

TIMESTAMP : TIMESTAMP
bits : 12 - 15 (4 bit)

OPTIONREG_OUT : OPTIONREG_OUT
bits : 16 - 23 (8 bit)

TRUST_ZONE : TRUST_ZONE
bits : 24 - 27 (4 bit)


RTC_VERR (VERR)

RTC version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_VERR RTC_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


RTC_IPIDR (IPIDR)

RTC identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_IPIDR RTC_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


RTC_SIDR (SIDR)

RTC size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_SIDR RTC_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


RTC_DR (DR)

The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_DR RTC_DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DU DT MU MT WDU YU YT

DU : DU
bits : 0 - 3 (4 bit)

DT : DT
bits : 4 - 5 (2 bit)

MU : MU
bits : 8 - 11 (4 bit)

MT : MT
bits : 12 - 12 (1 bit)

WDU : WDU
bits : 13 - 15 (3 bit)

YU : YU
bits : 16 - 19 (4 bit)

YT : YT
bits : 20 - 23 (4 bit)


RTC_ALRMAR (ALRMAR)

This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_ALRMAR RTC_ALRMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MSK1 MNU MNT MSK2 HU HT PM MSK3 DU DT WDSEL MSK4

SU : SU
bits : 0 - 3 (4 bit)

ST : ST
bits : 4 - 6 (3 bit)

MSK1 : MSK1
bits : 7 - 7 (1 bit)

MNU : MNU
bits : 8 - 11 (4 bit)

MNT : MNT
bits : 12 - 14 (3 bit)

MSK2 : MSK2
bits : 15 - 15 (1 bit)

HU : HU
bits : 16 - 19 (4 bit)

HT : HT
bits : 20 - 21 (2 bit)

PM : PM
bits : 22 - 22 (1 bit)

MSK3 : MSK3
bits : 23 - 23 (1 bit)

DU : DU
bits : 24 - 27 (4 bit)

DT : DT
bits : 28 - 29 (2 bit)

WDSEL : WDSEL
bits : 30 - 30 (1 bit)

MSK4 : MSK4
bits : 31 - 31 (1 bit)


RTC_ALRMASSR (ALRMASSR)

This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_ALRMASSR RTC_ALRMASSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS MASKSS

SS : SS
bits : 0 - 14 (15 bit)

MASKSS : MASKSS
bits : 24 - 27 (4 bit)


RTC_ALRMBR (ALRMBR)

This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_ALRMBR RTC_ALRMBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MSK1 MNU MNT MSK2 HU HT PM MSK3 DU DT WDSEL MSK4

SU : SU
bits : 0 - 3 (4 bit)

ST : ST
bits : 4 - 6 (3 bit)

MSK1 : MSK1
bits : 7 - 7 (1 bit)

MNU : MNU
bits : 8 - 11 (4 bit)

MNT : MNT
bits : 12 - 14 (3 bit)

MSK2 : MSK2
bits : 15 - 15 (1 bit)

HU : HU
bits : 16 - 19 (4 bit)

HT : HT
bits : 20 - 21 (2 bit)

PM : PM
bits : 22 - 22 (1 bit)

MSK3 : MSK3
bits : 23 - 23 (1 bit)

DU : DU
bits : 24 - 27 (4 bit)

DT : DT
bits : 28 - 29 (2 bit)

WDSEL : WDSEL
bits : 30 - 30 (1 bit)

MSK4 : MSK4
bits : 31 - 31 (1 bit)


RTC_ALRMBSSR (ALRMBSSR)

This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_ALRMBSSR RTC_ALRMBSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS MASKSS

SS : SS
bits : 0 - 14 (15 bit)

MASKSS : MASKSS
bits : 24 - 27 (4 bit)


RTC_SR (SR)

This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_SR RTC_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAF ALRBF WUTF TSF TSOVF ITSF

ALRAF : ALRAF
bits : 0 - 0 (1 bit)

ALRBF : ALRBF
bits : 1 - 1 (1 bit)

WUTF : WUTF
bits : 2 - 2 (1 bit)

TSF : TSF
bits : 3 - 3 (1 bit)

TSOVF : TSOVF
bits : 4 - 4 (1 bit)

ITSF : ITSF
bits : 5 - 5 (1 bit)


RTC_MISR (MISR)

RTC non-secure masked interrupt status register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_MISR RTC_MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAMF ALRBMF WUTMF TSMF TSOVMF ITSMF

ALRAMF : ALRAMF
bits : 0 - 0 (1 bit)

ALRBMF : ALRBMF
bits : 1 - 1 (1 bit)

WUTMF : WUTMF
bits : 2 - 2 (1 bit)

TSMF : TSMF
bits : 3 - 3 (1 bit)

TSOVMF : TSOVMF
bits : 4 - 4 (1 bit)

ITSMF : ITSMF
bits : 5 - 5 (1 bit)


RTC_SMISR (SMISR)

This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_SMISR RTC_SMISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAMF ALRBMF WUTMF TSMF TSOVMF ITSMF

ALRAMF : ALRAMF
bits : 0 - 0 (1 bit)

ALRBMF : ALRBMF
bits : 1 - 1 (1 bit)

WUTMF : WUTMF
bits : 2 - 2 (1 bit)

TSMF : TSMF
bits : 3 - 3 (1 bit)

TSOVMF : TSOVMF
bits : 4 - 4 (1 bit)

ITSMF : ITSMF
bits : 5 - 5 (1 bit)


RTC_SCR (SCR)

This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RTC_SCR RTC_SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALRAF CALRBF CWUTF CTSF CTSOVF CITSF

CALRAF : CALRAF
bits : 0 - 0 (1 bit)

CALRBF : CALRBF
bits : 1 - 1 (1 bit)

CWUTF : CWUTF
bits : 2 - 2 (1 bit)

CTSF : CTSF
bits : 3 - 3 (1 bit)

CTSOVF : CTSOVF
bits : 4 - 4 (1 bit)

CITSF : CITSF
bits : 5 - 5 (1 bit)


RTC_CFGR (CFGR)

RTC configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CFGR RTC_CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT2_RMP LSCOEN

OUT2_RMP : OUT2_RMP
bits : 0 - 0 (1 bit)

LSCOEN : LSCOEN
bits : 1 - 2 (2 bit)


RTC_SSR (SSR)

RTC sub second register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_SSR RTC_SSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS

SS : SS
bits : 0 - 15 (16 bit)


RTC_ICSR (ICSR)

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_ICSR RTC_ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAWF ALRBWF WUTWF SHPF INITS RSF INITF INIT RECALPF

ALRAWF : ALRAWF
bits : 0 - 0 (1 bit)
access : read-only

ALRBWF : ALRBWF
bits : 1 - 1 (1 bit)
access : read-only

WUTWF : WUTWF
bits : 2 - 2 (1 bit)
access : read-only

SHPF : SHPF
bits : 3 - 3 (1 bit)
access : read-only

INITS : INITS
bits : 4 - 4 (1 bit)
access : read-only

RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write

INITF : INITF
bits : 6 - 6 (1 bit)
access : read-only

INIT : INIT
bits : 7 - 7 (1 bit)
access : read-write

RECALPF : RECALPF
bits : 16 - 16 (1 bit)
access : read-only



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