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SPI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

SPI2S_CR1

SPI2S_IER

SPI2S_SR

SPI2S_IFCR

SPI2S_TXDR

SPI2S_RXDR

SPI_I2S_HWCFGR

SPI_VERR

SPI_IPIDR

SPI_SIDR

SPI_CR2

SPI_CRCPOLY

SPI_TXCRC

SPI_RXCRC

SPI_UDRDR

SPI_I2SCFGR

SPI_CFG1

SPI_CFG2


SPI2S_CR1

SPI/I2S control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI2S_CR1 SPI2S_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPE MASRX CSTART CSUSP HDDIR SSI CRC33_17 RCRCINI TCRCINI IOLOCK

SPE : SPE
bits : 0 - 0 (1 bit)
access : read-write

MASRX : MASRX
bits : 8 - 8 (1 bit)
access : read-write

CSTART : CSTART
bits : 9 - 9 (1 bit)
access : read-write

CSUSP : CSUSP
bits : 10 - 10 (1 bit)
access : write-only

HDDIR : HDDIR
bits : 11 - 11 (1 bit)
access : read-write

SSI : SSI
bits : 12 - 12 (1 bit)
access : read-write

CRC33_17 : CRC33_17
bits : 13 - 13 (1 bit)
access : read-write

RCRCINI : RCRCINI
bits : 14 - 14 (1 bit)
access : read-write

TCRCINI : TCRCINI
bits : 15 - 15 (1 bit)
access : read-write

IOLOCK : IOLOCK
bits : 16 - 16 (1 bit)
access : read-write


SPI2S_IER

SPI/I2S interrupt enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI2S_IER SPI2S_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPIE TXPIE DXPIE EOTIE TXTFIE UDRIE OVRIE CRCEIE TIFREIE MODFIE TSERFIE

RXPIE : RXPIE
bits : 0 - 0 (1 bit)

TXPIE : TXPIE
bits : 1 - 1 (1 bit)

DXPIE : DXPIE
bits : 2 - 2 (1 bit)

EOTIE : EOTIE
bits : 3 - 3 (1 bit)

TXTFIE : TXTFIE
bits : 4 - 4 (1 bit)

UDRIE : UDRIE
bits : 5 - 5 (1 bit)

OVRIE : OVRIE
bits : 6 - 6 (1 bit)

CRCEIE : CRCEIE
bits : 7 - 7 (1 bit)

TIFREIE : TIFREIE
bits : 8 - 8 (1 bit)

MODFIE : MODFIE
bits : 9 - 9 (1 bit)

TSERFIE : TSERFIE
bits : 10 - 10 (1 bit)


SPI2S_SR

SPI/I2S status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI2S_SR SPI2S_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXP TXP DXP EOT TXTF UDR OVR CRCE TIFRE MODF TSERF SUSP TXC RXPLVL RXWNE CTSIZE

RXP : RXP
bits : 0 - 0 (1 bit)

TXP : TXP
bits : 1 - 1 (1 bit)

DXP : DXP
bits : 2 - 2 (1 bit)

EOT : EOT
bits : 3 - 3 (1 bit)

TXTF : TXTF
bits : 4 - 4 (1 bit)

UDR : UDR
bits : 5 - 5 (1 bit)

OVR : OVR
bits : 6 - 6 (1 bit)

CRCE : CRCE
bits : 7 - 7 (1 bit)

TIFRE : TIFRE
bits : 8 - 8 (1 bit)

MODF : MODF
bits : 9 - 9 (1 bit)

TSERF : TSERF
bits : 10 - 10 (1 bit)

SUSP : SUSP
bits : 11 - 11 (1 bit)

TXC : TXC
bits : 12 - 12 (1 bit)

RXPLVL : RXPLVL
bits : 13 - 14 (2 bit)

RXWNE : RXWNE
bits : 15 - 15 (1 bit)

CTSIZE : CTSIZE
bits : 16 - 31 (16 bit)


SPI2S_IFCR

SPI/I2S interrupt/status flags clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPI2S_IFCR SPI2S_IFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOTC TXTFC UDRC OVRC CRCEC TIFREC MODFC TSERFC SUSPC

EOTC : EOTC
bits : 3 - 3 (1 bit)

TXTFC : TXTFC
bits : 4 - 4 (1 bit)

UDRC : UDRC
bits : 5 - 5 (1 bit)

OVRC : OVRC
bits : 6 - 6 (1 bit)

CRCEC : CRCEC
bits : 7 - 7 (1 bit)

TIFREC : TIFREC
bits : 8 - 8 (1 bit)

MODFC : MODFC
bits : 9 - 9 (1 bit)

TSERFC : TSERFC
bits : 10 - 10 (1 bit)

SUSPC : SUSPC
bits : 11 - 11 (1 bit)


SPI2S_TXDR

SPI/I2S transmit data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPI2S_TXDR SPI2S_TXDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDR

TXDR : TXDR
bits : 0 - 31 (32 bit)


SPI2S_RXDR

SPI/I2S receive data register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI2S_RXDR SPI2S_RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDR

RXDR : RXDR
bits : 0 - 31 (32 bit)


SPI_I2S_HWCFGR

SPI/I2S hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_I2S_HWCFGR SPI_I2S_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFCFG RXFCFG CRCCFG I2SCFG DSCFG

TXFCFG : TXFCFG
bits : 0 - 3 (4 bit)

RXFCFG : RXFCFG
bits : 4 - 7 (4 bit)

CRCCFG : CRCCFG
bits : 8 - 11 (4 bit)

I2SCFG : I2SCFG
bits : 12 - 15 (4 bit)

DSCFG : DSCFG
bits : 16 - 19 (4 bit)


SPI_VERR

SPI/I2S version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_VERR SPI_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


SPI_IPIDR

SPI/I2S identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_IPIDR SPI_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


SPI_SIDR

SPI/I2S size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SIDR SPI_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


SPI_CR2

SPI control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CR2 SPI_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSIZE TSER

TSIZE : TSIZE
bits : 0 - 15 (16 bit)

TSER : TSER
bits : 16 - 31 (16 bit)


SPI_CRCPOLY

SPI polynomial register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CRCPOLY SPI_CRCPOLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCPOLY

CRCPOLY : CRCPOLY
bits : 0 - 31 (32 bit)


SPI_TXCRC

SPI transmitter CRC register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_TXCRC SPI_TXCRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCRC

TXCRC : TXCRC
bits : 0 - 31 (32 bit)


SPI_RXCRC

SPI receiver CRC register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_RXCRC SPI_RXCRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRC

RXCRC : RXCRC
bits : 0 - 31 (32 bit)


SPI_UDRDR

SPI underrun data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_UDRDR SPI_UDRDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDRDR

UDRDR : UDRDR
bits : 0 - 31 (32 bit)


SPI_I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_I2SCFGR SPI_I2SCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SMOD I2SCFG I2SSTD PCMSYNC DATLEN CHLEN CKPOL FIXCH WSINV DATFMT I2SDIV ODD MCKOE

I2SMOD : I2SMOD
bits : 0 - 0 (1 bit)

I2SCFG : I2SCFG
bits : 1 - 3 (3 bit)

I2SSTD : I2SSTD
bits : 4 - 5 (2 bit)

PCMSYNC : PCMSYNC
bits : 7 - 7 (1 bit)

DATLEN : DATLEN
bits : 8 - 9 (2 bit)

CHLEN : CHLEN
bits : 10 - 10 (1 bit)

CKPOL : CKPOL
bits : 11 - 11 (1 bit)

FIXCH : FIXCH
bits : 12 - 12 (1 bit)

WSINV : WSINV
bits : 13 - 13 (1 bit)

DATFMT : DATFMT
bits : 14 - 14 (1 bit)

I2SDIV : I2SDIV
bits : 16 - 23 (8 bit)

ODD : ODD
bits : 24 - 24 (1 bit)

MCKOE : MCKOE
bits : 25 - 25 (1 bit)


SPI_CFG1

Content of this register is write protected when SPI is enabled
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CFG1 SPI_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSIZE FTHLV UDRCFG UDRDET RXDMAEN TXDMAEN CRCSIZE CRCEN MBR

DSIZE : DSIZE
bits : 0 - 4 (5 bit)

FTHLV : FTHLV
bits : 5 - 8 (4 bit)

UDRCFG : UDRCFG
bits : 9 - 10 (2 bit)

UDRDET : UDRDET
bits : 11 - 12 (2 bit)

RXDMAEN : RXDMAEN
bits : 14 - 14 (1 bit)

TXDMAEN : TXDMAEN
bits : 15 - 15 (1 bit)

CRCSIZE : CRCSIZE
bits : 16 - 20 (5 bit)

CRCEN : CRCEN
bits : 22 - 22 (1 bit)

MBR : MBR
bits : 28 - 30 (3 bit)


SPI_CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_CFG2 SPI_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSSI MIDI IOSWP COMM SP MASTER LSBFRST CPHA CPOL SSM SSIOP SSOE SSOM AFCNTR

MSSI : MSSI
bits : 0 - 3 (4 bit)

MIDI : MIDI
bits : 4 - 7 (4 bit)

IOSWP : IOSWP
bits : 15 - 15 (1 bit)

COMM : COMM
bits : 17 - 18 (2 bit)

SP : SP
bits : 19 - 21 (3 bit)

MASTER : MASTER
bits : 22 - 22 (1 bit)

LSBFRST : LSBFRST
bits : 23 - 23 (1 bit)

CPHA : CPHA
bits : 24 - 24 (1 bit)

CPOL : CPOL
bits : 25 - 25 (1 bit)

SSM : SSM
bits : 26 - 26 (1 bit)

SSIOP : SSIOP
bits : 28 - 28 (1 bit)

SSOE : SSOE
bits : 29 - 29 (1 bit)

SSOM : SSOM
bits : 30 - 30 (1 bit)

AFCNTR : AFCNTR
bits : 31 - 31 (1 bit)



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