\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
LTDC identification register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV : REV
bits : 0 - 7 (8 bit)
MINVER : MINVER
bits : 8 - 15 (8 bit)
MAJVER : MAJVER
bits : 16 - 23 (8 bit)
This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AAH : AAH
bits : 0 - 11 (12 bit)
AAW : AAW
bits : 16 - 27 (12 bit)
LTDC layer 2 control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : LEN
bits : 0 - 0 (1 bit)
COLKEN : COLKEN
bits : 1 - 1 (1 bit)
CLUTEN : CLUTEN
bits : 4 - 4 (1 bit)
This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHSTPOS : WHSTPOS
bits : 0 - 11 (12 bit)
WHSPPOS : WHSPPOS
bits : 16 - 27 (12 bit)
This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVSTPOS : WVSTPOS
bits : 0 - 11 (12 bit)
WVSPPOS : WVSPPOS
bits : 16 - 27 (12 bit)
This register defines the color key value (RGB), that is used by the color keying.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKBLUE : CKBLUE
bits : 0 - 7 (8 bit)
CKGREEN : CKGREEN
bits : 8 - 15 (8 bit)
CKRED : CKRED
bits : 16 - 23 (8 bit)
This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF : PF
bits : 0 - 2 (3 bit)
This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONSTA : CONSTA
bits : 0 - 7 (8 bit)
This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCBLUE : DCBLUE
bits : 0 - 7 (8 bit)
DCGREEN : DCGREEN
bits : 8 - 15 (8 bit)
DCRED : DCRED
bits : 16 - 23 (8 bit)
DCALPHA : DCALPHA
bits : 24 - 31 (8 bit)
This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BF2 : BF2
bits : 0 - 2 (3 bit)
BF1 : BF1
bits : 8 - 10 (3 bit)
This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBADD : CFBADD
bits : 0 - 31 (32 bit)
This register defines the color frame buffer line length and pitch.
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLL : CFBLL
bits : 0 - 13 (14 bit)
CFBP : CFBP
bits : 16 - 29 (14 bit)
This register defines the number of lines in the color frame buffer.
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLNBR : CFBLNBR
bits : 0 - 11 (12 bit)
This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOTALH : TOTALH
bits : 0 - 11 (12 bit)
TOTALW : TOTALW
bits : 16 - 27 (12 bit)
This register defines the CLUT address and the RGB value.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BLUE : BLUE
bits : 0 - 7 (8 bit)
GREEN : GREEN
bits : 8 - 15 (8 bit)
RED : RED
bits : 16 - 23 (8 bit)
CLUTADD : CLUTADD
bits : 24 - 31 (8 bit)
This register defines the global configuration of the LCD-TFT controller.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTDCEN : LTDCEN
bits : 0 - 0 (1 bit)
access : read-write
DBW : DBW
bits : 4 - 6 (3 bit)
access : read-only
DGW : DGW
bits : 8 - 10 (3 bit)
access : read-only
DRW : DRW
bits : 12 - 14 (3 bit)
access : read-only
DEN : DEN
bits : 16 - 16 (1 bit)
access : read-write
PCPOL : PCPOL
bits : 28 - 28 (1 bit)
access : read-write
DEPOL : DEPOL
bits : 29 - 29 (1 bit)
access : read-write
VSPOL : VSPOL
bits : 30 - 30 (1 bit)
access : read-write
HSPOL : HSPOL
bits : 31 - 31 (1 bit)
access : read-write
LTDC global configuration 1 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WBCH : WBCH
bits : 0 - 3 (4 bit)
WGCH : WGCH
bits : 4 - 7 (4 bit)
WRCH : WRCH
bits : 8 - 11 (4 bit)
PRBEN : PRBEN
bits : 12 - 12 (1 bit)
DT : DT
bits : 14 - 15 (2 bit)
GCT : GCT
bits : 17 - 19 (3 bit)
SHREN : SHREN
bits : 21 - 21 (1 bit)
BCP : BCP
bits : 22 - 22 (1 bit)
BBEN : BBEN
bits : 23 - 23 (1 bit)
LNIP : LNIP
bits : 24 - 24 (1 bit)
TP : TP
bits : 25 - 25 (1 bit)
IPP : IPP
bits : 26 - 26 (1 bit)
SPP : SPP
bits : 27 - 27 (1 bit)
DWP : DWP
bits : 28 - 28 (1 bit)
STREN : STREN
bits : 29 - 29 (1 bit)
BMEN : BMEN
bits : 31 - 31 (1 bit)
LTDC global configuration 2 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDCEN : EDCEN
bits : 0 - 0 (1 bit)
STSAEN : STSAEN
bits : 1 - 1 (1 bit)
DVAEN : DVAEN
bits : 2 - 2 (1 bit)
DPAEN : DPAEN
bits : 3 - 3 (1 bit)
BW : BW
bits : 4 - 6 (3 bit)
EDCA : EDCA
bits : 7 - 7 (1 bit)
This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMR : IMR
bits : 0 - 0 (1 bit)
VBR : VBR
bits : 1 - 1 (1 bit)
This register defines the background color (RGB888).
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCBLUE : BCBLUE
bits : 0 - 7 (8 bit)
BCGREEN : BCGREEN
bits : 8 - 15 (8 bit)
BCRED : BCRED
bits : 16 - 23 (8 bit)
This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIE : LIE
bits : 0 - 0 (1 bit)
FUIE : FUIE
bits : 1 - 1 (1 bit)
TERRIE : TERRIE
bits : 2 - 2 (1 bit)
RRIE : RRIE
bits : 3 - 3 (1 bit)
This register returns the interrupt status flag.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LIF : LIF
bits : 0 - 0 (1 bit)
FUIF : FUIF
bits : 1 - 1 (1 bit)
TERRIF : TERRIF
bits : 2 - 2 (1 bit)
RRIF : RRIF
bits : 3 - 3 (1 bit)
LTDC Interrupt Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLIF : CLIF
bits : 0 - 0 (1 bit)
CFUIF : CFUIF
bits : 1 - 1 (1 bit)
CTERRIF : CTERRIF
bits : 2 - 2 (1 bit)
CRRIF : CRRIF
bits : 3 - 3 (1 bit)
LDTC layer count register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LNBR : LNBR
bits : 0 - 7 (8 bit)
This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIPOS : LIPOS
bits : 0 - 11 (12 bit)
LTDC current position status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYPOS : CYPOS
bits : 0 - 15 (16 bit)
CXPOS : CXPOS
bits : 16 - 31 (16 bit)
This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VDES : VDES
bits : 0 - 0 (1 bit)
HDES : HDES
bits : 1 - 1 (1 bit)
VSYNCS : VSYNCS
bits : 2 - 2 (1 bit)
HSYNCS : HSYNCS
bits : 3 - 3 (1 bit)
This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSH : VSH
bits : 0 - 11 (12 bit)
HSW : HSW
bits : 16 - 27 (12 bit)
LTDC layer 1 control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : LEN
bits : 0 - 0 (1 bit)
COLKEN : COLKEN
bits : 1 - 1 (1 bit)
CLUTEN : CLUTEN
bits : 4 - 4 (1 bit)
This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHSTPOS : WHSTPOS
bits : 0 - 11 (12 bit)
WHSPPOS : WHSPPOS
bits : 16 - 27 (12 bit)
This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVSTPOS : WVSTPOS
bits : 0 - 11 (12 bit)
WVSPPOS : WVSPPOS
bits : 16 - 27 (12 bit)
This register defines the color key value (RGB), that is used by the color keying.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKBLUE : CKBLUE
bits : 0 - 7 (8 bit)
CKGREEN : CKGREEN
bits : 8 - 15 (8 bit)
CKRED : CKRED
bits : 16 - 23 (8 bit)
This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF : PF
bits : 0 - 2 (3 bit)
This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONSTA : CONSTA
bits : 0 - 7 (8 bit)
This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCBLUE : DCBLUE
bits : 0 - 7 (8 bit)
DCGREEN : DCGREEN
bits : 8 - 15 (8 bit)
DCRED : DCRED
bits : 16 - 23 (8 bit)
DCALPHA : DCALPHA
bits : 24 - 31 (8 bit)
This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BF2 : BF2
bits : 0 - 2 (3 bit)
BF1 : BF1
bits : 8 - 10 (3 bit)
This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBADD : CFBADD
bits : 0 - 31 (32 bit)
This register defines the color frame buffer line length and pitch.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLL : CFBLL
bits : 0 - 13 (14 bit)
CFBP : CFBP
bits : 16 - 29 (14 bit)
This register defines the number of lines in the color frame buffer.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFBLNBR : CFBLNBR
bits : 0 - 11 (12 bit)
This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AVBP : AVBP
bits : 0 - 11 (12 bit)
AHBP : AHBP
bits : 16 - 27 (12 bit)
This register defines the CLUT address and the RGB value.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BLUE : BLUE
bits : 0 - 7 (8 bit)
GREEN : GREEN
bits : 8 - 15 (8 bit)
RED : RED
bits : 16 - 23 (8 bit)
CLUTADD : CLUTADD
bits : 24 - 31 (8 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.