\n

USBPHYC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

USBPHYC_PLL (PLL)

USBPHYC_TUNE1 (TUNE1)

USBPHYC_TUNE2 (TUNE2)

USBPHYC_MISC (MISC)

USBPHYC_VERR (VERR)


USBPHYC_PLL (PLL)

This register is used to control the PLL of the HS PHY.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHYC_PLL USBPHYC_PLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLNDIV PLLODF PLLFRACIN PLLEN PLLSTRB PLLSTRBYP PLLFRACCTL PLLDITHEN0 PLLDITHEN1

PLLNDIV : PLLNDIV
bits : 0 - 6 (7 bit)

PLLODF : PLLODF
bits : 7 - 9 (3 bit)

PLLFRACIN : PLLFRACIN
bits : 10 - 25 (16 bit)

PLLEN : PLLEN
bits : 26 - 26 (1 bit)

PLLSTRB : PLLSTRB
bits : 27 - 27 (1 bit)

PLLSTRBYP : PLLSTRBYP
bits : 28 - 28 (1 bit)

PLLFRACCTL : PLLFRACCTL
bits : 29 - 29 (1 bit)

PLLDITHEN0 : PLLDITHEN0
bits : 30 - 30 (1 bit)

PLLDITHEN1 : PLLDITHEN1
bits : 31 - 31 (1 bit)


USBPHYC_TUNE1 (TUNE1)

This register is used to control the tune interface of the HS PHY, port #x.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHYC_TUNE1 USBPHYC_TUNE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INCURREN INCURRINT LFSCAPEN HSDRVSLEW HSDRVDCCUR HSDRVDCLEV HSDRVCURINCR FSDRVRFADJ HSDRVRFRED HSDRVCHKITRM HSDRVCHKZTRM OTPCOMP SQLCHCTL HDRXGNEQEN HSRXOFF HSFALLPREEM SHTCCTCTLPROT STAGSEL

INCURREN : INCURREN
bits : 0 - 0 (1 bit)

INCURRINT : INCURRINT
bits : 1 - 1 (1 bit)

LFSCAPEN : LFSCAPEN
bits : 2 - 2 (1 bit)

HSDRVSLEW : HSDRVSLEW
bits : 3 - 3 (1 bit)

HSDRVDCCUR : HSDRVDCCUR
bits : 4 - 4 (1 bit)

HSDRVDCLEV : HSDRVDCLEV
bits : 5 - 5 (1 bit)

HSDRVCURINCR : HSDRVCURINCR
bits : 6 - 6 (1 bit)

FSDRVRFADJ : FSDRVRFADJ
bits : 7 - 7 (1 bit)

HSDRVRFRED : HSDRVRFRED
bits : 8 - 8 (1 bit)

HSDRVCHKITRM : HSDRVCHKITRM
bits : 9 - 12 (4 bit)

HSDRVCHKZTRM : HSDRVCHKZTRM
bits : 13 - 14 (2 bit)

OTPCOMP : OTPCOMP
bits : 15 - 19 (5 bit)

SQLCHCTL : SQLCHCTL
bits : 20 - 21 (2 bit)

HDRXGNEQEN : HDRXGNEQEN
bits : 22 - 22 (1 bit)

HSRXOFF : HSRXOFF
bits : 23 - 24 (2 bit)

HSFALLPREEM : HSFALLPREEM
bits : 25 - 25 (1 bit)

SHTCCTCTLPROT : SHTCCTCTLPROT
bits : 26 - 26 (1 bit)

STAGSEL : STAGSEL
bits : 27 - 27 (1 bit)


USBPHYC_TUNE2 (TUNE2)

This register is used to control the tune interface of the HS PHY, port #x.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHYC_TUNE2 USBPHYC_TUNE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INCURREN INCURRINT LFSCAPEN HSDRVSLEW HSDRVDCCUR HSDRVDCLEV HSDRVCURINCR FSDRVRFADJ HSDRVRFRED HSDRVCHKITRM HSDRVCHKZTRM OTPCOMP SQLCHCTL HDRXGNEQEN HSRXOFF HSFALLPREEM SHTCCTCTLPROT STAGSEL

INCURREN : INCURREN
bits : 0 - 0 (1 bit)

INCURRINT : INCURRINT
bits : 1 - 1 (1 bit)

LFSCAPEN : LFSCAPEN
bits : 2 - 2 (1 bit)

HSDRVSLEW : HSDRVSLEW
bits : 3 - 3 (1 bit)

HSDRVDCCUR : HSDRVDCCUR
bits : 4 - 4 (1 bit)

HSDRVDCLEV : HSDRVDCLEV
bits : 5 - 5 (1 bit)

HSDRVCURINCR : HSDRVCURINCR
bits : 6 - 6 (1 bit)

FSDRVRFADJ : FSDRVRFADJ
bits : 7 - 7 (1 bit)

HSDRVRFRED : HSDRVRFRED
bits : 8 - 8 (1 bit)

HSDRVCHKITRM : HSDRVCHKITRM
bits : 9 - 12 (4 bit)

HSDRVCHKZTRM : HSDRVCHKZTRM
bits : 13 - 14 (2 bit)

OTPCOMP : OTPCOMP
bits : 15 - 19 (5 bit)

SQLCHCTL : SQLCHCTL
bits : 20 - 21 (2 bit)

HDRXGNEQEN : HDRXGNEQEN
bits : 22 - 22 (1 bit)

HSRXOFF : HSRXOFF
bits : 23 - 24 (2 bit)

HSFALLPREEM : HSFALLPREEM
bits : 25 - 25 (1 bit)

SHTCCTCTLPROT : SHTCCTCTLPROT
bits : 26 - 26 (1 bit)

STAGSEL : STAGSEL
bits : 27 - 27 (1 bit)


USBPHYC_MISC (MISC)

This register is used to control the switch between controllers for the HS PHY.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHYC_MISC USBPHYC_MISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITHOST PPCKDIS

SWITHOST : SWITHOST
bits : 0 - 0 (1 bit)

PPCKDIS : PPCKDIS
bits : 1 - 2 (2 bit)


USBPHYC_VERR (VERR)

This register defines the version of this IP.
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USBPHYC_VERR USBPHYC_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.