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QUADSPI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

QUADSPI_CR (CR)

QUADSPI_DLR (DLR)

QUADSPI_CCR (CCR)

QUADSPI_AR (AR)

QUADSPI_ABR (ABR)

QUADSPI_DR (DR)

QUADSPI_PSMKR (PSMKR)

QUADSPI_PSMAR (PSMAR)

QUADSPI_PIR (PIR)

QUADSPI_LPTR (LPTR)

QUADSPI_HWCFGR (HWCFGR)

QUADSPI_VERR (VERR)

QUADSPI_IPIDR (IPIDR)

QUADSPI_SIDR (SIDR)

QUADSPI_DCR (DCR)

QUADSPI_SR (SR)

QUADSPI_FCR (FCR)


QUADSPI_CR (CR)

QUADSPI control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_CR QUADSPI_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN ABORT DMAEN TCEN SSHIFT DFM FSEL FTHRES TEIE TCIE FTIE SMIE TOIE APMS PMM PRESCALER

EN : EN
bits : 0 - 0 (1 bit)

ABORT : ABORT
bits : 1 - 1 (1 bit)

DMAEN : DMAEN
bits : 2 - 2 (1 bit)

TCEN : TCEN
bits : 3 - 3 (1 bit)

SSHIFT : SSHIFT
bits : 4 - 4 (1 bit)

DFM : DFM
bits : 6 - 6 (1 bit)

FSEL : FSEL
bits : 7 - 7 (1 bit)

FTHRES : FTHRES
bits : 8 - 11 (4 bit)

TEIE : TEIE
bits : 16 - 16 (1 bit)

TCIE : TCIE
bits : 17 - 17 (1 bit)

FTIE : FTIE
bits : 18 - 18 (1 bit)

SMIE : SMIE
bits : 19 - 19 (1 bit)

TOIE : TOIE
bits : 20 - 20 (1 bit)

APMS : APMS
bits : 22 - 22 (1 bit)

PMM : PMM
bits : 23 - 23 (1 bit)

PRESCALER : PRESCALER
bits : 24 - 31 (8 bit)


QUADSPI_DLR (DLR)

QUADSPI data length register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_DLR QUADSPI_DLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DL

DL : DL
bits : 0 - 31 (32 bit)


QUADSPI_CCR (CCR)

QUADSPI communication configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_CCR QUADSPI_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION IMODE ADMODE ADSIZE ABMODE ABSIZE DCYC DMODE FMODE SIOO FRCM DHHC DDRM

INSTRUCTION : INSTRUCTION
bits : 0 - 7 (8 bit)

IMODE : IMODE
bits : 8 - 9 (2 bit)

ADMODE : ADMODE
bits : 10 - 11 (2 bit)

ADSIZE : ADSIZE
bits : 12 - 13 (2 bit)

ABMODE : ABMODE
bits : 14 - 15 (2 bit)

ABSIZE : ABSIZE
bits : 16 - 17 (2 bit)

DCYC : DCYC
bits : 18 - 22 (5 bit)

DMODE : DMODE
bits : 24 - 25 (2 bit)

FMODE : FMODE
bits : 26 - 27 (2 bit)

SIOO : SIOO
bits : 28 - 28 (1 bit)

FRCM : FRCM
bits : 29 - 29 (1 bit)

DHHC : DHHC
bits : 30 - 30 (1 bit)

DDRM : DDRM
bits : 31 - 31 (1 bit)


QUADSPI_AR (AR)

QUADSPI address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_AR QUADSPI_AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : ADDRESS
bits : 0 - 31 (32 bit)


QUADSPI_ABR (ABR)

QUADSPI alternate bytes registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_ABR QUADSPI_ABR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALTERNATE

ALTERNATE : ALTERNATE
bits : 0 - 31 (32 bit)


QUADSPI_DR (DR)

QUADSPI data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_DR QUADSPI_DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


QUADSPI_PSMKR (PSMKR)

QUADSPI polling status mask register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_PSMKR QUADSPI_PSMKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : MASK
bits : 0 - 31 (32 bit)


QUADSPI_PSMAR (PSMAR)

QUADSPI polling status match register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_PSMAR QUADSPI_PSMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : MATCH
bits : 0 - 31 (32 bit)


QUADSPI_PIR (PIR)

QUADSPI polling interval register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_PIR QUADSPI_PIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERVAL

INTERVAL : INTERVAL
bits : 0 - 15 (16 bit)


QUADSPI_LPTR (LPTR)

QUADSPI low-power timeout register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_LPTR QUADSPI_LPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT

TIMEOUT : TIMEOUT
bits : 0 - 15 (16 bit)


QUADSPI_HWCFGR (HWCFGR)

QUADSPI HW configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_HWCFGR QUADSPI_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOSIZE FIFOPTR PRESCVAL IDLENGTH

FIFOSIZE : FIFOSIZE
bits : 0 - 3 (4 bit)

FIFOPTR : FIFOPTR
bits : 4 - 7 (4 bit)

PRESCVAL : PRESCVAL
bits : 8 - 11 (4 bit)

IDLENGTH : IDLENGTH
bits : 12 - 15 (4 bit)


QUADSPI_VERR (VERR)

QUADSPI version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_VERR QUADSPI_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


QUADSPI_IPIDR (IPIDR)

QUADSPI identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_IPIDR QUADSPI_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


QUADSPI_SIDR (SIDR)

QUADSPI size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_SIDR QUADSPI_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


QUADSPI_DCR (DCR)

QUADSPI device configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_DCR QUADSPI_DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKMODE CSHT FSIZE

CKMODE : CKMODE
bits : 0 - 0 (1 bit)

CSHT : CSHT
bits : 8 - 10 (3 bit)

FSIZE : FSIZE
bits : 16 - 20 (5 bit)


QUADSPI_SR (SR)

QUADSPI status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_SR QUADSPI_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEF TCF FTF SMF TOF BUSY FLEVEL

TEF : TEF
bits : 0 - 0 (1 bit)

TCF : TCF
bits : 1 - 1 (1 bit)

FTF : FTF
bits : 2 - 2 (1 bit)

SMF : SMF
bits : 3 - 3 (1 bit)

TOF : TOF
bits : 4 - 4 (1 bit)

BUSY : BUSY
bits : 5 - 5 (1 bit)

FLEVEL : FLEVEL
bits : 8 - 12 (5 bit)


QUADSPI_FCR (FCR)

QUADSPI flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

QUADSPI_FCR QUADSPI_FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEF CTCF CSMF CTOF

CTEF : CTEF
bits : 0 - 0 (1 bit)

CTCF : CTCF
bits : 1 - 1 (1 bit)

CSMF : CSMF
bits : 3 - 3 (1 bit)

CTOF : CTOF
bits : 4 - 4 (1 bit)



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