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GPIOK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

GPIOK_MODER (MODER)

GPIOK_IDR (IDR)

GPIOK_ODR (ODR)

GPIOK_BSRR (BSRR)

GPIOK_LCKR (LCKR)

GPIOK_AFRL (AFRL)

GPIOK_AFRH (AFRH)

GPIOK_BRR (BRR)

GPIOK_HWCFGR10 (HWCFGR10)

GPIOK_HWCFGR9 (HWCFGR9)

GPIOK_HWCFGR8 (HWCFGR8)

GPIOK_HWCFGR7 (HWCFGR7)

GPIOK_HWCFGR6 (HWCFGR6)

GPIOK_HWCFGR5 (HWCFGR5)

GPIOK_HWCFGR4 (HWCFGR4)

GPIOK_HWCFGR3 (HWCFGR3)

GPIOK_HWCFGR2 (HWCFGR2)

GPIOK_HWCFGR1 (HWCFGR1)

GPIOK_HWCFGR0 (HWCFGR0)

GPIOK_VERR (VERR)

GPIOK_IPIDR (IPIDR)

GPIOK_SIDR (SIDR)

GPIOK_OTYPER (OTYPER)

GPIOK_OSPEEDR (OSPEEDR)

GPIOK_PUPDR (PUPDR)


GPIOK_MODER (MODER)

GPIO port mode register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_MODER GPIOK_MODER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODER0 MODER1 MODER2 MODER3 MODER4 MODER5 MODER6 MODER7 MODER8 MODER9 MODER10 MODER11 MODER12 MODER13 MODER14 MODER15

MODER0 : MODER0
bits : 0 - 1 (2 bit)

MODER1 : MODER1
bits : 2 - 3 (2 bit)

MODER2 : MODER2
bits : 4 - 5 (2 bit)

MODER3 : MODER3
bits : 6 - 7 (2 bit)

MODER4 : MODER4
bits : 8 - 9 (2 bit)

MODER5 : MODER5
bits : 10 - 11 (2 bit)

MODER6 : MODER6
bits : 12 - 13 (2 bit)

MODER7 : MODER7
bits : 14 - 15 (2 bit)

MODER8 : MODER8
bits : 16 - 17 (2 bit)

MODER9 : MODER9
bits : 18 - 19 (2 bit)

MODER10 : MODER10
bits : 20 - 21 (2 bit)

MODER11 : MODER11
bits : 22 - 23 (2 bit)

MODER12 : MODER12
bits : 24 - 25 (2 bit)

MODER13 : MODER13
bits : 26 - 27 (2 bit)

MODER14 : MODER14
bits : 28 - 29 (2 bit)

MODER15 : MODER15
bits : 30 - 31 (2 bit)


GPIOK_IDR (IDR)

GPIO port input data register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_IDR GPIOK_IDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR0 IDR1 IDR2 IDR3 IDR4 IDR5 IDR6 IDR7 IDR8 IDR9 IDR10 IDR11 IDR12 IDR13 IDR14 IDR15

IDR0 : IDR0
bits : 0 - 0 (1 bit)

IDR1 : IDR1
bits : 1 - 1 (1 bit)

IDR2 : IDR2
bits : 2 - 2 (1 bit)

IDR3 : IDR3
bits : 3 - 3 (1 bit)

IDR4 : IDR4
bits : 4 - 4 (1 bit)

IDR5 : IDR5
bits : 5 - 5 (1 bit)

IDR6 : IDR6
bits : 6 - 6 (1 bit)

IDR7 : IDR7
bits : 7 - 7 (1 bit)

IDR8 : IDR8
bits : 8 - 8 (1 bit)

IDR9 : IDR9
bits : 9 - 9 (1 bit)

IDR10 : IDR10
bits : 10 - 10 (1 bit)

IDR11 : IDR11
bits : 11 - 11 (1 bit)

IDR12 : IDR12
bits : 12 - 12 (1 bit)

IDR13 : IDR13
bits : 13 - 13 (1 bit)

IDR14 : IDR14
bits : 14 - 14 (1 bit)

IDR15 : IDR15
bits : 15 - 15 (1 bit)


GPIOK_ODR (ODR)

GPIO port output data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_ODR GPIOK_ODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODR0 ODR1 ODR2 ODR3 ODR4 ODR5 ODR6 ODR7 ODR8 ODR9 ODR10 ODR11 ODR12 ODR13 ODR14 ODR15

ODR0 : ODR0
bits : 0 - 0 (1 bit)

ODR1 : ODR1
bits : 1 - 1 (1 bit)

ODR2 : ODR2
bits : 2 - 2 (1 bit)

ODR3 : ODR3
bits : 3 - 3 (1 bit)

ODR4 : ODR4
bits : 4 - 4 (1 bit)

ODR5 : ODR5
bits : 5 - 5 (1 bit)

ODR6 : ODR6
bits : 6 - 6 (1 bit)

ODR7 : ODR7
bits : 7 - 7 (1 bit)

ODR8 : ODR8
bits : 8 - 8 (1 bit)

ODR9 : ODR9
bits : 9 - 9 (1 bit)

ODR10 : ODR10
bits : 10 - 10 (1 bit)

ODR11 : ODR11
bits : 11 - 11 (1 bit)

ODR12 : ODR12
bits : 12 - 12 (1 bit)

ODR13 : ODR13
bits : 13 - 13 (1 bit)

ODR14 : ODR14
bits : 14 - 14 (1 bit)

ODR15 : ODR15
bits : 15 - 15 (1 bit)


GPIOK_BSRR (BSRR)

GPIO port bit set/reset register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_BSRR GPIOK_BSRR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BS0 BS1 BS2 BS3 BS4 BS5 BS6 BS7 BS8 BS9 BS10 BS11 BS12 BS13 BS14 BS15 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7 BR8 BR9 BR10 BR11 BR12 BR13 BR14 BR15

BS0 : BS0
bits : 0 - 0 (1 bit)

BS1 : BS1
bits : 1 - 1 (1 bit)

BS2 : BS2
bits : 2 - 2 (1 bit)

BS3 : BS3
bits : 3 - 3 (1 bit)

BS4 : BS4
bits : 4 - 4 (1 bit)

BS5 : BS5
bits : 5 - 5 (1 bit)

BS6 : BS6
bits : 6 - 6 (1 bit)

BS7 : BS7
bits : 7 - 7 (1 bit)

BS8 : BS8
bits : 8 - 8 (1 bit)

BS9 : BS9
bits : 9 - 9 (1 bit)

BS10 : BS10
bits : 10 - 10 (1 bit)

BS11 : BS11
bits : 11 - 11 (1 bit)

BS12 : BS12
bits : 12 - 12 (1 bit)

BS13 : BS13
bits : 13 - 13 (1 bit)

BS14 : BS14
bits : 14 - 14 (1 bit)

BS15 : BS15
bits : 15 - 15 (1 bit)

BR0 : BR0
bits : 16 - 16 (1 bit)

BR1 : BR1
bits : 17 - 17 (1 bit)

BR2 : BR2
bits : 18 - 18 (1 bit)

BR3 : BR3
bits : 19 - 19 (1 bit)

BR4 : BR4
bits : 20 - 20 (1 bit)

BR5 : BR5
bits : 21 - 21 (1 bit)

BR6 : BR6
bits : 22 - 22 (1 bit)

BR7 : BR7
bits : 23 - 23 (1 bit)

BR8 : BR8
bits : 24 - 24 (1 bit)

BR9 : BR9
bits : 25 - 25 (1 bit)

BR10 : BR10
bits : 26 - 26 (1 bit)

BR11 : BR11
bits : 27 - 27 (1 bit)

BR12 : BR12
bits : 28 - 28 (1 bit)

BR13 : BR13
bits : 29 - 29 (1 bit)

BR14 : BR14
bits : 30 - 30 (1 bit)

BR15 : BR15
bits : 31 - 31 (1 bit)


GPIOK_LCKR (LCKR)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_LCKR GPIOK_LCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK0 LCK1 LCK2 LCK3 LCK4 LCK5 LCK6 LCK7 LCK8 LCK9 LCK10 LCK11 LCK12 LCK13 LCK14 LCK15 LCKK

LCK0 : LCK0
bits : 0 - 0 (1 bit)

LCK1 : LCK1
bits : 1 - 1 (1 bit)

LCK2 : LCK2
bits : 2 - 2 (1 bit)

LCK3 : LCK3
bits : 3 - 3 (1 bit)

LCK4 : LCK4
bits : 4 - 4 (1 bit)

LCK5 : LCK5
bits : 5 - 5 (1 bit)

LCK6 : LCK6
bits : 6 - 6 (1 bit)

LCK7 : LCK7
bits : 7 - 7 (1 bit)

LCK8 : LCK8
bits : 8 - 8 (1 bit)

LCK9 : LCK9
bits : 9 - 9 (1 bit)

LCK10 : LCK10
bits : 10 - 10 (1 bit)

LCK11 : LCK11
bits : 11 - 11 (1 bit)

LCK12 : LCK12
bits : 12 - 12 (1 bit)

LCK13 : LCK13
bits : 13 - 13 (1 bit)

LCK14 : LCK14
bits : 14 - 14 (1 bit)

LCK15 : LCK15
bits : 15 - 15 (1 bit)

LCKK : LCKK
bits : 16 - 16 (1 bit)


GPIOK_AFRL (AFRL)

GPIO alternate function low register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_AFRL GPIOK_AFRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFR0 AFR1 AFR2 AFR3 AFR4 AFR5 AFR6 AFR7

AFR0 : AFR0
bits : 0 - 3 (4 bit)

AFR1 : AFR1
bits : 4 - 7 (4 bit)

AFR2 : AFR2
bits : 8 - 11 (4 bit)

AFR3 : AFR3
bits : 12 - 15 (4 bit)

AFR4 : AFR4
bits : 16 - 19 (4 bit)

AFR5 : AFR5
bits : 20 - 23 (4 bit)

AFR6 : AFR6
bits : 24 - 27 (4 bit)

AFR7 : AFR7
bits : 28 - 31 (4 bit)


GPIOK_AFRH (AFRH)

GPIO alternate function high register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_AFRH GPIOK_AFRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFR8 AFR9 AFR10 AFR11 AFR12 AFR13 AFR14 AFR15

AFR8 : AFR8
bits : 0 - 3 (4 bit)

AFR9 : AFR9
bits : 4 - 7 (4 bit)

AFR10 : AFR10
bits : 8 - 11 (4 bit)

AFR11 : AFR11
bits : 12 - 15 (4 bit)

AFR12 : AFR12
bits : 16 - 19 (4 bit)

AFR13 : AFR13
bits : 20 - 23 (4 bit)

AFR14 : AFR14
bits : 24 - 27 (4 bit)

AFR15 : AFR15
bits : 28 - 31 (4 bit)


GPIOK_BRR (BRR)

GPIO port bit reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_BRR GPIOK_BRR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7 BR8 BR9 BR10 BR11 BR12 BR13 BR14 BR15

BR0 : BR0
bits : 0 - 0 (1 bit)

BR1 : BR1
bits : 1 - 1 (1 bit)

BR2 : BR2
bits : 2 - 2 (1 bit)

BR3 : BR3
bits : 3 - 3 (1 bit)

BR4 : BR4
bits : 4 - 4 (1 bit)

BR5 : BR5
bits : 5 - 5 (1 bit)

BR6 : BR6
bits : 6 - 6 (1 bit)

BR7 : BR7
bits : 7 - 7 (1 bit)

BR8 : BR8
bits : 8 - 8 (1 bit)

BR9 : BR9
bits : 9 - 9 (1 bit)

BR10 : BR10
bits : 10 - 10 (1 bit)

BR11 : BR11
bits : 11 - 11 (1 bit)

BR12 : BR12
bits : 12 - 12 (1 bit)

BR13 : BR13
bits : 13 - 13 (1 bit)

BR14 : BR14
bits : 14 - 14 (1 bit)

BR15 : BR15
bits : 15 - 15 (1 bit)


GPIOK_HWCFGR10 (HWCFGR10)

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR10 GPIOK_HWCFGR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_IOP AF_SIZE SPEED_CFG LOCK_CFG SEC_CFG OR_CFG

AHB_IOP : AHB_IOP
bits : 0 - 3 (4 bit)

AF_SIZE : AF_SIZE
bits : 4 - 7 (4 bit)

SPEED_CFG : SPEED_CFG
bits : 8 - 11 (4 bit)

LOCK_CFG : LOCK_CFG
bits : 12 - 15 (4 bit)

SEC_CFG : SEC_CFG
bits : 16 - 19 (4 bit)

OR_CFG : OR_CFG
bits : 20 - 23 (4 bit)


GPIOK_HWCFGR9 (HWCFGR9)

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR9 GPIOK_HWCFGR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN_IO

EN_IO : EN_IO
bits : 0 - 15 (16 bit)


GPIOK_HWCFGR8 (HWCFGR8)

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR8 GPIOK_HWCFGR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AF_PRIO8 AF_PRIO9 AF_PRIO10 AF_PRIO11 AF_PRIO12 AF_PRIO13 AF_PRIO14 AF_PRIO15

AF_PRIO8 : AF_PRIO8
bits : 0 - 3 (4 bit)

AF_PRIO9 : AF_PRIO9
bits : 4 - 7 (4 bit)

AF_PRIO10 : AF_PRIO10
bits : 8 - 11 (4 bit)

AF_PRIO11 : AF_PRIO11
bits : 12 - 15 (4 bit)

AF_PRIO12 : AF_PRIO12
bits : 16 - 19 (4 bit)

AF_PRIO13 : AF_PRIO13
bits : 20 - 23 (4 bit)

AF_PRIO14 : AF_PRIO14
bits : 24 - 27 (4 bit)

AF_PRIO15 : AF_PRIO15
bits : 28 - 31 (4 bit)


GPIOK_HWCFGR7 (HWCFGR7)

GPIO hardware configuration register 7
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR7 GPIOK_HWCFGR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AF_PRIO0 AF_PRIO1 AF_PRIO2 AF_PRIO3 AF_PRIO4 AF_PRIO5 AF_PRIO6 AF_PRIO7

AF_PRIO0 : AF_PRIO0
bits : 0 - 3 (4 bit)

AF_PRIO1 : AF_PRIO1
bits : 4 - 7 (4 bit)

AF_PRIO2 : AF_PRIO2
bits : 8 - 11 (4 bit)

AF_PRIO3 : AF_PRIO3
bits : 12 - 15 (4 bit)

AF_PRIO4 : AF_PRIO4
bits : 16 - 19 (4 bit)

AF_PRIO5 : AF_PRIO5
bits : 20 - 23 (4 bit)

AF_PRIO6 : AF_PRIO6
bits : 24 - 27 (4 bit)

AF_PRIO7 : AF_PRIO7
bits : 28 - 31 (4 bit)


GPIOK_HWCFGR6 (HWCFGR6)

GPIO hardware configuration register 6
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR6 GPIOK_HWCFGR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODER_RES

MODER_RES : MODER_RES
bits : 0 - 31 (32 bit)


GPIOK_HWCFGR5 (HWCFGR5)

GPIO hardware configuration register 5
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR5 GPIOK_HWCFGR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PUPDR_RES

PUPDR_RES : PUPDR_RES
bits : 0 - 31 (32 bit)


GPIOK_HWCFGR4 (HWCFGR4)

GPIO hardware configuration register 4
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR4 GPIOK_HWCFGR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSPEED_RES

OSPEED_RES : OSPEED_RES
bits : 0 - 31 (32 bit)


GPIOK_HWCFGR3 (HWCFGR3)

GPIO hardware configuration register 3
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR3 GPIOK_HWCFGR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODR_RES OTYPER_RES

ODR_RES : ODR_RES
bits : 0 - 15 (16 bit)

OTYPER_RES : OTYPER_RES
bits : 16 - 31 (16 bit)


GPIOK_HWCFGR2 (HWCFGR2)

GPIO hardware configuration register 2
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR2 GPIOK_HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFRL_RES

AFRL_RES : AFRL_RES
bits : 0 - 31 (32 bit)


GPIOK_HWCFGR1 (HWCFGR1)

GPIO hardware configuration register 1
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR1 GPIOK_HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFRH_RES

AFRH_RES : AFRH_RES
bits : 0 - 31 (32 bit)


GPIOK_HWCFGR0 (HWCFGR0)

GPIO hardware configuration register 0
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_HWCFGR0 GPIOK_HWCFGR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OR_RES

OR_RES : OR_RES
bits : 0 - 15 (16 bit)


GPIOK_VERR (VERR)

GPIO version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_VERR GPIOK_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


GPIOK_IPIDR (IPIDR)

GPIO identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_IPIDR GPIOK_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPIDR

IPIDR : IPIDR
bits : 0 - 31 (32 bit)


GPIOK_SIDR (SIDR)

GPIO size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOK_SIDR GPIOK_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIDR

SIDR : SIDR
bits : 0 - 31 (32 bit)


GPIOK_OTYPER (OTYPER)

GPIO port output type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_OTYPER GPIOK_OTYPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OT0 OT1 OT2 OT3 OT4 OT5 OT6 OT7 OT8 OT9 OT10 OT11 OT12 OT13 OT14 OT15

OT0 : OT0
bits : 0 - 0 (1 bit)

OT1 : OT1
bits : 1 - 1 (1 bit)

OT2 : OT2
bits : 2 - 2 (1 bit)

OT3 : OT3
bits : 3 - 3 (1 bit)

OT4 : OT4
bits : 4 - 4 (1 bit)

OT5 : OT5
bits : 5 - 5 (1 bit)

OT6 : OT6
bits : 6 - 6 (1 bit)

OT7 : OT7
bits : 7 - 7 (1 bit)

OT8 : OT8
bits : 8 - 8 (1 bit)

OT9 : OT9
bits : 9 - 9 (1 bit)

OT10 : OT10
bits : 10 - 10 (1 bit)

OT11 : OT11
bits : 11 - 11 (1 bit)

OT12 : OT12
bits : 12 - 12 (1 bit)

OT13 : OT13
bits : 13 - 13 (1 bit)

OT14 : OT14
bits : 14 - 14 (1 bit)

OT15 : OT15
bits : 15 - 15 (1 bit)


GPIOK_OSPEEDR (OSPEEDR)

GPIO port output speed register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_OSPEEDR GPIOK_OSPEEDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSPEEDR0 OSPEEDR1 OSPEEDR2 OSPEEDR3 OSPEEDR4 OSPEEDR5 OSPEEDR6 OSPEEDR7 OSPEEDR8 OSPEEDR9 OSPEEDR10 OSPEEDR11 OSPEEDR12 OSPEEDR13 OSPEEDR14 OSPEEDR15

OSPEEDR0 : OSPEEDR0
bits : 0 - 1 (2 bit)

OSPEEDR1 : OSPEEDR1
bits : 2 - 3 (2 bit)

OSPEEDR2 : OSPEEDR2
bits : 4 - 5 (2 bit)

OSPEEDR3 : OSPEEDR3
bits : 6 - 7 (2 bit)

OSPEEDR4 : OSPEEDR4
bits : 8 - 9 (2 bit)

OSPEEDR5 : OSPEEDR5
bits : 10 - 11 (2 bit)

OSPEEDR6 : OSPEEDR6
bits : 12 - 13 (2 bit)

OSPEEDR7 : OSPEEDR7
bits : 14 - 15 (2 bit)

OSPEEDR8 : OSPEEDR8
bits : 16 - 17 (2 bit)

OSPEEDR9 : OSPEEDR9
bits : 18 - 19 (2 bit)

OSPEEDR10 : OSPEEDR10
bits : 20 - 21 (2 bit)

OSPEEDR11 : OSPEEDR11
bits : 22 - 23 (2 bit)

OSPEEDR12 : OSPEEDR12
bits : 24 - 25 (2 bit)

OSPEEDR13 : OSPEEDR13
bits : 26 - 27 (2 bit)

OSPEEDR14 : OSPEEDR14
bits : 28 - 29 (2 bit)

OSPEEDR15 : OSPEEDR15
bits : 30 - 31 (2 bit)


GPIOK_PUPDR (PUPDR)

GPIO port pull-up/pull-down register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOK_PUPDR GPIOK_PUPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PUPDR0 PUPDR1 PUPDR2 PUPDR3 PUPDR4 PUPDR5 PUPDR6 PUPDR7 PUPDR8 PUPDR9 PUPDR10 PUPDR11 PUPDR12 PUPDR13 PUPDR14 PUPDR15

PUPDR0 : PUPDR0
bits : 0 - 1 (2 bit)

PUPDR1 : PUPDR1
bits : 2 - 3 (2 bit)

PUPDR2 : PUPDR2
bits : 4 - 5 (2 bit)

PUPDR3 : PUPDR3
bits : 6 - 7 (2 bit)

PUPDR4 : PUPDR4
bits : 8 - 9 (2 bit)

PUPDR5 : PUPDR5
bits : 10 - 11 (2 bit)

PUPDR6 : PUPDR6
bits : 12 - 13 (2 bit)

PUPDR7 : PUPDR7
bits : 14 - 15 (2 bit)

PUPDR8 : PUPDR8
bits : 16 - 17 (2 bit)

PUPDR9 : PUPDR9
bits : 18 - 19 (2 bit)

PUPDR10 : PUPDR10
bits : 20 - 21 (2 bit)

PUPDR11 : PUPDR11
bits : 22 - 23 (2 bit)

PUPDR12 : PUPDR12
bits : 24 - 25 (2 bit)

PUPDR13 : PUPDR13
bits : 26 - 27 (2 bit)

PUPDR14 : PUPDR14
bits : 28 - 29 (2 bit)

PUPDR15 : PUPDR15
bits : 30 - 31 (2 bit)



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