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HSEM_IPXACT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

HSEM_R0 (R0)

HSEM_R4 (R4)

HSEM_C1IER (C1IER)

HSEM_C1ICR (C1ICR)

HSEM_C1ISR (C1ISR)

HSEM_C1MISR (C1MISR)

HSEM_C2IER (C2IER)

HSEM_C2ICR (C2ICR)

HSEM_C2ISR (C2ISR)

HSEM_C2MISR (C2MISR)

HSEM_R5 (R5)

HSEM_CR (CR)

HSEM_KEYR (KEYR)

HSEM_R6 (R6)

HSEM_R7 (R7)

HSEM_R8 (R8)

HSEM_R9 (R9)

HSEM_R10 (R10)

HSEM_R11 (R11)

HSEM_R12 (R12)

HSEM_R13 (R13)

HSEM_R14 (R14)

HSEM_R15 (R15)

HSEM_HWCFGR2 (HWCFGR2)

HSEM_HWCFGR1 (HWCFGR1)

HSEM_VERR (VERR)

HSEM_IPIDR (IPIDR)

HSEM_SIDR (SIDR)

HSEM_R1 (R1)

HSEM_R16 (R16)

HSEM_R17 (R17)

HSEM_R18 (R18)

HSEM_R19 (R19)

HSEM_R20 (R20)

HSEM_R21 (R21)

HSEM_R22 (R22)

HSEM_R23 (R23)

HSEM_R24 (R24)

HSEM_R25 (R25)

HSEM_R26 (R26)

HSEM_R27 (R27)

HSEM_R28 (R28)

HSEM_R29 (R29)

HSEM_R30 (R30)

HSEM_R31 (R31)

HSEM_R2 (R2)

HSEM_RLR0 (RLR0)

HSEM_RLR1 (RLR1)

HSEM_RLR2 (RLR2)

HSEM_RLR3 (RLR3)

HSEM_RLR4 (RLR4)

HSEM_RLR5 (RLR5)

HSEM_RLR6 (RLR6)

HSEM_RLR7 (RLR7)

HSEM_RLR8 (RLR8)

HSEM_RLR9 (RLR9)

HSEM_RLR10 (RLR10)

HSEM_RLR11 (RLR11)

HSEM_RLR12 (RLR12)

HSEM_RLR13 (RLR13)

HSEM_RLR14 (RLR14)

HSEM_RLR15 (RLR15)

HSEM_R3 (R3)

HSEM_RLR16 (RLR16)

HSEM_RLR17 (RLR17)

HSEM_RLR18 (RLR18)

HSEM_RLR19 (RLR19)

HSEM_RLR20 (RLR20)

HSEM_RLR21 (RLR21)

HSEM_RLR22 (RLR22)

HSEM_RLR23 (RLR23)

HSEM_RLR24 (RLR24)

HSEM_RLR25 (RLR25)

HSEM_RLR26 (RLR26)

HSEM_RLR27 (RLR27)

HSEM_RLR28 (RLR28)

HSEM_RLR29 (RLR29)

HSEM_RLR30 (RLR30)

HSEM_RLR31 (RLR31)


HSEM_R0 (R0)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R0 HSEM_R0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R4 (R4)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R4 HSEM_R4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_C1IER (C1IER)

HSEM i1terrupt enable register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1IER HSEM_C1IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISE

ISE : ISE
bits : 0 - 31 (32 bit)


HSEM_C1ICR (C1ICR)

HSEM i1terrupt clear register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1ICR HSEM_C1ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISC

ISC : ISC
bits : 0 - 31 (32 bit)


HSEM_C1ISR (C1ISR)

HSEM i1terrupt status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1ISR HSEM_C1ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISF

ISF : ISF
bits : 0 - 31 (32 bit)


HSEM_C1MISR (C1MISR)

HSEM i1terrupt status register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C1MISR HSEM_C1MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISF

MISF : MISF
bits : 0 - 31 (32 bit)


HSEM_C2IER (C2IER)

HSEM i2terrupt enable register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2IER HSEM_C2IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISE

ISE : ISE
bits : 0 - 31 (32 bit)


HSEM_C2ICR (C2ICR)

HSEM i2terrupt clear register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2ICR HSEM_C2ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISC

ISC : ISC
bits : 0 - 31 (32 bit)


HSEM_C2ISR (C2ISR)

HSEM i2terrupt status register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2ISR HSEM_C2ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISF

ISF : ISF
bits : 0 - 31 (32 bit)


HSEM_C2MISR (C2MISR)

HSEM i2terrupt status register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_C2MISR HSEM_C2MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISF

MISF : MISF
bits : 0 - 31 (32 bit)


HSEM_R5 (R5)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R5 HSEM_R5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_CR (CR)

Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_CR HSEM_CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COREID KEY

COREID : COREID
bits : 8 - 11 (4 bit)

KEY : KEY
bits : 16 - 31 (16 bit)


HSEM_KEYR (KEYR)

HSEM interrupt clear register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_KEYR HSEM_KEYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 16 - 31 (16 bit)


HSEM_R6 (R6)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R6 HSEM_R6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R7 (R7)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R7 HSEM_R7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R8 (R8)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R8 HSEM_R8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R9 (R9)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R9 HSEM_R9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R10 (R10)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R10 HSEM_R10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R11 (R11)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R11 HSEM_R11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R12 (R12)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R12 HSEM_R12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R13 (R13)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R13 HSEM_R13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R14 (R14)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R14 HSEM_R14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R15 (R15)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R15 HSEM_R15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_HWCFGR2 (HWCFGR2)

HSEM hardware configuration register 2
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_HWCFGR2 HSEM_HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTERID1 MASTERID2 MASTERID3 MASTERID4

MASTERID1 : MASTERID1
bits : 0 - 3 (4 bit)

MASTERID2 : MASTERID2
bits : 4 - 7 (4 bit)

MASTERID3 : MASTERID3
bits : 8 - 11 (4 bit)

MASTERID4 : MASTERID4
bits : 12 - 15 (4 bit)


HSEM_HWCFGR1 (HWCFGR1)

HSEM hardware configuration register 1
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_HWCFGR1 HSEM_HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NBSEM NBINT

NBSEM : NBSEM
bits : 0 - 7 (8 bit)

NBINT : NBINT
bits : 8 - 11 (4 bit)


HSEM_VERR (VERR)

HSEM IP version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_VERR HSEM_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


HSEM_IPIDR (IPIDR)

HSEM IP identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_IPIDR HSEM_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPID

IPID : IPID
bits : 0 - 31 (32 bit)


HSEM_SIDR (SIDR)

HSEM size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_SIDR HSEM_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


HSEM_R1 (R1)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R1 HSEM_R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R16 (R16)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R16 HSEM_R16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R17 (R17)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R17 HSEM_R17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R18 (R18)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R18 HSEM_R18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R19 (R19)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R19 HSEM_R19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R20 (R20)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R20 HSEM_R20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R21 (R21)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R21 HSEM_R21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R22 (R22)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R22 HSEM_R22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R23 (R23)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R23 HSEM_R23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R24 (R24)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R24 HSEM_R24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R25 (R25)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R25 HSEM_R25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R26 (R26)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R26 HSEM_R26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R27 (R27)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R27 HSEM_R27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R28 (R28)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R28 HSEM_R28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R29 (R29)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R29 HSEM_R29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R30 (R30)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R30 HSEM_R30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R31 (R31)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R31 HSEM_R31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R2 (R2)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R2 HSEM_R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR0 (RLR0)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR0 HSEM_RLR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR1 (RLR1)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR1 HSEM_RLR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR2 (RLR2)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR2 HSEM_RLR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR3 (RLR3)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR3 HSEM_RLR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR4 (RLR4)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR4 HSEM_RLR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR5 (RLR5)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR5 HSEM_RLR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR6 (RLR6)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR6 HSEM_RLR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR7 (RLR7)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR7 HSEM_RLR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR8 (RLR8)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR8 HSEM_RLR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR9 (RLR9)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR9 HSEM_RLR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR10 (RLR10)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR10 HSEM_RLR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR11 (RLR11)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR11 HSEM_RLR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR12 (RLR12)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR12 HSEM_RLR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR13 (RLR13)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR13 HSEM_RLR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR14 (RLR14)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR14 HSEM_RLR14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR15 (RLR15)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR15 HSEM_RLR15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_R3 (R3)

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSEM_R3 HSEM_R3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR16 (RLR16)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR16 HSEM_RLR16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR17 (RLR17)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR17 HSEM_RLR17 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR18 (RLR18)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR18 HSEM_RLR18 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR19 (RLR19)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR19 HSEM_RLR19 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR20 (RLR20)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR20 HSEM_RLR20 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR21 (RLR21)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR21 HSEM_RLR21 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR22 (RLR22)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR22 HSEM_RLR22 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR23 (RLR23)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR23 HSEM_RLR23 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR24 (RLR24)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR24 HSEM_RLR24 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR25 (RLR25)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR25 HSEM_RLR25 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR26 (RLR26)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR26 HSEM_RLR26 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR27 (RLR27)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR27 HSEM_RLR27 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR28 (RLR28)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR28 HSEM_RLR28 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR29 (RLR29)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR29 HSEM_RLR29 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR30 (RLR30)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR30 HSEM_RLR30 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


HSEM_RLR31 (RLR31)

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSEM_RLR31 HSEM_RLR31 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCID COREID LOCK

PROCID : PROCID
bits : 0 - 7 (8 bit)

COREID : COREID
bits : 8 - 11 (4 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)



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