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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. )
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOT0 : BOOT0
bits : 0 - 0 (1 bit)
access : read-only
BOOT1 : BOOT1
bits : 1 - 1 (1 bit)
access : read-only
BOOT2 : BOOT2
bits : 2 - 2 (1 bit)
access : read-only
BOOT0_PD : BOOT0_PD
bits : 4 - 4 (1 bit)
access : read-write
BOOT1_PD : BOOT1_PD
bits : 5 - 5 (1 bit)
access : read-write
BOOT2_PD : BOOT2_PD
bits : 6 - 6 (1 bit)
access : read-write
SYSCFG IO control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSLVEN_TRACE : HSLVEN_TRACE
bits : 0 - 0 (1 bit)
HSLVEN_QUADSPI : HSLVEN_QUADSPI
bits : 1 - 1 (1 bit)
HSLVEN_ETH : HSLVEN_ETH
bits : 2 - 2 (1 bit)
HSLVEN_SDMMC : HSLVEN_SDMMC
bits : 3 - 3 (1 bit)
HSLVEN_SPI : HSLVEN_SPI
bits : 4 - 4 (1 bit)
SYSCFG interconnect control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AXI_M0 : AXI_M0
bits : 0 - 0 (1 bit)
AXI_M1 : AXI_M1
bits : 1 - 1 (1 bit)
AXI_M2 : AXI_M2
bits : 2 - 2 (1 bit)
AXI_M3 : AXI_M3
bits : 3 - 3 (1 bit)
AXI_M5 : AXI_M5
bits : 5 - 5 (1 bit)
AXI_M6 : AXI_M6
bits : 6 - 6 (1 bit)
AXI_M7 : AXI_M7
bits : 7 - 7 (1 bit)
AXI_M8 : AXI_M8
bits : 8 - 8 (1 bit)
AXI_M9 : AXI_M9
bits : 9 - 9 (1 bit)
AXI_M10 : AXI_M10
bits : 10 - 10 (1 bit)
SYSCFG compensation cell control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_CTRL : SW_CTRL
bits : 1 - 1 (1 bit)
access : read-write
READY : READY
bits : 8 - 8 (1 bit)
access : read-only
RANSRC : RANSRC
bits : 16 - 19 (4 bit)
access : read-write
RAPSRC : RAPSRC
bits : 20 - 23 (4 bit)
access : read-write
ANSRC : ANSRC
bits : 24 - 27 (4 bit)
access : read-only
APSRC : APSRC
bits : 28 - 31 (4 bit)
access : read-only
SYSCFG compensation cell enable set register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU_EN : MPU_EN
bits : 0 - 0 (1 bit)
MCU_EN : MCU_EN
bits : 1 - 1 (1 bit)
SYSCFG compensation cell enable set register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU_EN : MPU_EN
bits : 0 - 0 (1 bit)
MCU_EN : MCU_EN
bits : 1 - 1 (1 bit)
SYSCFG control timer break register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLL : CLL
bits : 0 - 0 (1 bit)
PVDL : PVDL
bits : 2 - 2 (1 bit)
SYSCFG version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
SYSCFG identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
SYSCFG size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
SYSCFG peripheral mode configuration set register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C1_FMP : I2C1_FMP
bits : 0 - 0 (1 bit)
I2C2_FMP : I2C2_FMP
bits : 1 - 1 (1 bit)
I2C3_FMP : I2C3_FMP
bits : 2 - 2 (1 bit)
I2C4_FMP : I2C4_FMP
bits : 3 - 3 (1 bit)
I2C5_FMP : I2C5_FMP
bits : 4 - 4 (1 bit)
I2C6_FMP : I2C6_FMP
bits : 5 - 5 (1 bit)
EN_BOOSTER : EN_BOOSTER
bits : 8 - 8 (1 bit)
ANASWVDD : ANASWVDD
bits : 9 - 9 (1 bit)
ETH_CLK_SEL : ETH_CLK_SEL
bits : 16 - 16 (1 bit)
ETH_REF_CLK_SEL : ETH_REF_CLK_SEL
bits : 17 - 17 (1 bit)
ETH_SELMII : ETH_SELMII
bits : 20 - 20 (1 bit)
ETH_SEL : ETH_SEL
bits : 21 - 23 (3 bit)
ANA0_SEL : ANA0_SEL
bits : 24 - 24 (1 bit)
ANA1_SEL : ANA1_SEL
bits : 25 - 25 (1 bit)
SYSCFG peripheral mode configuration clear register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C1_FMP : I2C1_FMP
bits : 0 - 0 (1 bit)
I2C2_FMP : I2C2_FMP
bits : 1 - 1 (1 bit)
I2C3_FMP : I2C3_FMP
bits : 2 - 2 (1 bit)
I2C4_FMP : I2C4_FMP
bits : 3 - 3 (1 bit)
I2C5_FMP : I2C5_FMP
bits : 4 - 4 (1 bit)
I2C6_FMP : I2C6_FMP
bits : 5 - 5 (1 bit)
EN_BOOSTER : EN_BOOSTER
bits : 8 - 8 (1 bit)
ANASWVDD : ANASWVDD
bits : 9 - 9 (1 bit)
ETH_CLK_SEL : ETH_CLK_SEL
bits : 16 - 16 (1 bit)
ETH_REF_CLK_SEL : ETH_REF_CLK_SEL
bits : 17 - 17 (1 bit)
ETH_SELMII : ETH_SELMII
bits : 20 - 20 (1 bit)
ETH_SEL : ETH_SEL
bits : 21 - 23 (3 bit)
ANA0_SEL : ANA0_SEL
bits : 24 - 24 (1 bit)
ANA1_SEL : ANA1_SEL
bits : 25 - 25 (1 bit)
SYSCFG IO control register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSLVEN_TRACE : HSLVEN_TRACE
bits : 0 - 0 (1 bit)
HSLVEN_QUADSPI : HSLVEN_QUADSPI
bits : 1 - 1 (1 bit)
HSLVEN_ETH : HSLVEN_ETH
bits : 2 - 2 (1 bit)
HSLVEN_SDMMC : HSLVEN_SDMMC
bits : 3 - 3 (1 bit)
HSLVEN_SPI : HSLVEN_SPI
bits : 4 - 4 (1 bit)
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