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LPTIM3

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

LPTIM_ISR

LPTIM_CR

LPTIM_CMP

LPTIM_ARR

LPTIM_CNT

LPTIM3_CFGR2 (CFGR2)

LPTIM3_HWCFGR (HWCFGR)

LPTIM_VERR

LPTIM_PIDR

LPTIM_SIDR

LPTIM_ICR

LPTIM_IER

LPTIM_CFGR


LPTIM_ISR

LPTIM interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM_ISR LPTIM_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPM ARRM EXTTRIG CMPOK ARROK UP DOWN

CMPM : CMPM
bits : 0 - 0 (1 bit)

ARRM : ARRM
bits : 1 - 1 (1 bit)

EXTTRIG : EXTTRIG
bits : 2 - 2 (1 bit)

CMPOK : CMPOK
bits : 3 - 3 (1 bit)

ARROK : ARROK
bits : 4 - 4 (1 bit)

UP : UP
bits : 5 - 5 (1 bit)

DOWN : DOWN
bits : 6 - 6 (1 bit)


LPTIM_CR

LPTIM control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM_CR LPTIM_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SNGSTRT CNTSTRT COUNTRST RSTARE

ENABLE : ENABLE
bits : 0 - 0 (1 bit)

SNGSTRT : SNGSTRT
bits : 1 - 1 (1 bit)

CNTSTRT : CNTSTRT
bits : 2 - 2 (1 bit)

COUNTRST : COUNTRST
bits : 3 - 3 (1 bit)

RSTARE : RSTARE
bits : 4 - 4 (1 bit)


LPTIM_CMP

LPTIM compare register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM_CMP LPTIM_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : CMP
bits : 0 - 15 (16 bit)


LPTIM_ARR

LPTIM autoreload register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM_ARR LPTIM_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)


LPTIM_CNT

LPTIM counter register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM_CNT LPTIM_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 15 (16 bit)


LPTIM3_CFGR2 (CFGR2)

LPTIM3 configuration register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM3_CFGR2 LPTIM3_CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IN1SEL

IN1SEL : IN1SEL
bits : 0 - 1 (2 bit)


LPTIM3_HWCFGR (HWCFGR)

LPTIM 3 peripheral hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM3_HWCFGR LPTIM3_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG1 CFG2 CFG3 CFG4

CFG1 : CFG1
bits : 0 - 7 (8 bit)

CFG2 : CFG2
bits : 8 - 15 (8 bit)

CFG3 : CFG3
bits : 16 - 19 (4 bit)

CFG4 : CFG4
bits : 24 - 31 (8 bit)


LPTIM_VERR

LPTIM peripheral version identification register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM_VERR LPTIM_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


LPTIM_PIDR

LPTIM peripheral type identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM_PIDR LPTIM_PIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_ID

P_ID : P_ID
bits : 0 - 31 (32 bit)


LPTIM_SIDR

LPTIM registers map size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM_SIDR LPTIM_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_ID

S_ID : S_ID
bits : 0 - 31 (32 bit)


LPTIM_ICR

LPTIM interrupt clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LPTIM_ICR LPTIM_ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMCF ARRMCF EXTTRIGCF CMPOKCF ARROKCF UPCF DOWNCF

CMPMCF : CMPMCF
bits : 0 - 0 (1 bit)

ARRMCF : ARRMCF
bits : 1 - 1 (1 bit)

EXTTRIGCF : EXTTRIGCF
bits : 2 - 2 (1 bit)

CMPOKCF : CMPOKCF
bits : 3 - 3 (1 bit)

ARROKCF : ARROKCF
bits : 4 - 4 (1 bit)

UPCF : UPCF
bits : 5 - 5 (1 bit)

DOWNCF : DOWNCF
bits : 6 - 6 (1 bit)


LPTIM_IER

LPTIM interrupt enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM_IER LPTIM_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMIE ARRMIE EXTTRIGIE CMPOKIE ARROKIE UPIE DOWNIE

CMPMIE : CMPMIE
bits : 0 - 0 (1 bit)

ARRMIE : ARRMIE
bits : 1 - 1 (1 bit)

EXTTRIGIE : EXTTRIGIE
bits : 2 - 2 (1 bit)

CMPOKIE : CMPOKIE
bits : 3 - 3 (1 bit)

ARROKIE : ARROKIE
bits : 4 - 4 (1 bit)

UPIE : UPIE
bits : 5 - 5 (1 bit)

DOWNIE : DOWNIE
bits : 6 - 6 (1 bit)


LPTIM_CFGR

LPTIM configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTIM_CFGR LPTIM_CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSEL CKPOL CKFLT TRGFLT PRESC TRIGSEL TRIGEN TIMOUT WAVE WAVPOL PRELOAD COUNTMODE ENC

CKSEL : CKSEL
bits : 0 - 0 (1 bit)

CKPOL : CKPOL
bits : 1 - 2 (2 bit)

CKFLT : CKFLT
bits : 3 - 4 (2 bit)

TRGFLT : TRGFLT
bits : 6 - 7 (2 bit)

PRESC : PRESC
bits : 9 - 11 (3 bit)

TRIGSEL : TRIGSEL
bits : 13 - 15 (3 bit)

TRIGEN : TRIGEN
bits : 17 - 18 (2 bit)

TIMOUT : TIMOUT
bits : 19 - 19 (1 bit)

WAVE : WAVE
bits : 20 - 20 (1 bit)

WAVPOL : WAVPOL
bits : 21 - 21 (1 bit)

PRELOAD : PRELOAD
bits : 22 - 22 (1 bit)

COUNTMODE : COUNTMODE
bits : 23 - 23 (1 bit)

ENC : ENC
bits : 24 - 24 (1 bit)



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