\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
CEC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CECEN : CECEN
bits : 0 - 0 (1 bit)
access : read-write
TXSOM : TXSOM
bits : 1 - 1 (1 bit)
access : read-write
TXEOM : TXEOM
bits : 2 - 2 (1 bit)
access : read-write
CEC Interrupt and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBR : RXBR
bits : 0 - 0 (1 bit)
access : read-write
RXEND : RXEND
bits : 1 - 1 (1 bit)
access : read-write
RXOVR : RXOVR
bits : 2 - 2 (1 bit)
access : read-write
BRE : BRE
bits : 3 - 3 (1 bit)
access : read-write
SBPE : SBPE
bits : 4 - 4 (1 bit)
access : read-write
LBPE : LBPE
bits : 5 - 5 (1 bit)
access : read-write
RXACKE : RXACKE
bits : 6 - 6 (1 bit)
access : read-write
ARBLST : ARBLST
bits : 7 - 7 (1 bit)
access : read-write
TXBR : TXBR
bits : 8 - 8 (1 bit)
access : read-write
TXEND : TXEND
bits : 9 - 9 (1 bit)
access : read-write
TXUDR : TXUDR
bits : 10 - 10 (1 bit)
access : read-write
TXERR : TXERR
bits : 11 - 11 (1 bit)
access : read-write
TXACKE : TXACKE
bits : 12 - 12 (1 bit)
access : read-write
CEC interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBRIE : RXBRIE
bits : 0 - 0 (1 bit)
access : read-write
RXENDIE : RXENDIE
bits : 1 - 1 (1 bit)
access : read-write
RXOVRIE : RXOVRIE
bits : 2 - 2 (1 bit)
access : read-write
BREIE : BREIE
bits : 3 - 3 (1 bit)
access : read-write
SBPEIE : SBPEIE
bits : 4 - 4 (1 bit)
access : read-write
LBPEIE : LBPEIE
bits : 5 - 5 (1 bit)
access : read-write
RXACKIE : RXACKIE
bits : 6 - 6 (1 bit)
access : read-write
ARBLSTIE : ARBLSTIE
bits : 7 - 7 (1 bit)
access : read-write
TXBRIE : TXBRIE
bits : 8 - 8 (1 bit)
access : read-write
TXENDIE : TXENDIE
bits : 9 - 9 (1 bit)
access : read-write
TXUDRIE : TXUDRIE
bits : 10 - 10 (1 bit)
access : read-write
TXERRIE : TXERRIE
bits : 11 - 11 (1 bit)
access : read-write
TXACKIE : TXACKIE
bits : 12 - 12 (1 bit)
access : read-write
This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFT : SFT
bits : 0 - 2 (3 bit)
access : read-write
RXTOL : RXTOL
bits : 3 - 3 (1 bit)
access : read-write
BRESTP : BRESTP
bits : 4 - 4 (1 bit)
access : read-write
BREGEN : BREGEN
bits : 5 - 5 (1 bit)
access : read-write
LBPEGEN : LBPEGEN
bits : 6 - 6 (1 bit)
access : read-write
BRDNOGEN : BRDNOGEN
bits : 7 - 7 (1 bit)
access : read-write
SFTOP : SFTOP
bits : 8 - 8 (1 bit)
access : read-write
OAR : OAR
bits : 16 - 30 (15 bit)
access : read-write
LSTN : LSTN
bits : 31 - 31 (1 bit)
access : read-write
CEC Tx data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXD : TXD
bits : 0 - 7 (8 bit)
access : write-only
CEC Rx data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXD : RXD
bits : 0 - 7 (8 bit)
access : read-only
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