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HDMI_CEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CEC_CR

CEC_ISR

CEC_IER

CEC_CFGR

CEC_TXDR

CEC_RXDR


CEC_CR

CEC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEC_CR CEC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECEN TXSOM TXEOM

CECEN : CECEN
bits : 0 - 0 (1 bit)
access : read-write

TXSOM : TXSOM
bits : 1 - 1 (1 bit)
access : read-write

TXEOM : TXEOM
bits : 2 - 2 (1 bit)
access : read-write


CEC_ISR

CEC Interrupt and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEC_ISR CEC_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBR RXEND RXOVR BRE SBPE LBPE RXACKE ARBLST TXBR TXEND TXUDR TXERR TXACKE

RXBR : RXBR
bits : 0 - 0 (1 bit)
access : read-write

RXEND : RXEND
bits : 1 - 1 (1 bit)
access : read-write

RXOVR : RXOVR
bits : 2 - 2 (1 bit)
access : read-write

BRE : BRE
bits : 3 - 3 (1 bit)
access : read-write

SBPE : SBPE
bits : 4 - 4 (1 bit)
access : read-write

LBPE : LBPE
bits : 5 - 5 (1 bit)
access : read-write

RXACKE : RXACKE
bits : 6 - 6 (1 bit)
access : read-write

ARBLST : ARBLST
bits : 7 - 7 (1 bit)
access : read-write

TXBR : TXBR
bits : 8 - 8 (1 bit)
access : read-write

TXEND : TXEND
bits : 9 - 9 (1 bit)
access : read-write

TXUDR : TXUDR
bits : 10 - 10 (1 bit)
access : read-write

TXERR : TXERR
bits : 11 - 11 (1 bit)
access : read-write

TXACKE : TXACKE
bits : 12 - 12 (1 bit)
access : read-write


CEC_IER

CEC interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEC_IER CEC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBRIE RXENDIE RXOVRIE BREIE SBPEIE LBPEIE RXACKIE ARBLSTIE TXBRIE TXENDIE TXUDRIE TXERRIE TXACKIE

RXBRIE : RXBRIE
bits : 0 - 0 (1 bit)
access : read-write

RXENDIE : RXENDIE
bits : 1 - 1 (1 bit)
access : read-write

RXOVRIE : RXOVRIE
bits : 2 - 2 (1 bit)
access : read-write

BREIE : BREIE
bits : 3 - 3 (1 bit)
access : read-write

SBPEIE : SBPEIE
bits : 4 - 4 (1 bit)
access : read-write

LBPEIE : LBPEIE
bits : 5 - 5 (1 bit)
access : read-write

RXACKIE : RXACKIE
bits : 6 - 6 (1 bit)
access : read-write

ARBLSTIE : ARBLSTIE
bits : 7 - 7 (1 bit)
access : read-write

TXBRIE : TXBRIE
bits : 8 - 8 (1 bit)
access : read-write

TXENDIE : TXENDIE
bits : 9 - 9 (1 bit)
access : read-write

TXUDRIE : TXUDRIE
bits : 10 - 10 (1 bit)
access : read-write

TXERRIE : TXERRIE
bits : 11 - 11 (1 bit)
access : read-write

TXACKIE : TXACKIE
bits : 12 - 12 (1 bit)
access : read-write


CEC_CFGR

This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEC_CFGR CEC_CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFT RXTOL BRESTP BREGEN LBPEGEN BRDNOGEN SFTOP OAR LSTN

SFT : SFT
bits : 0 - 2 (3 bit)
access : read-write

RXTOL : RXTOL
bits : 3 - 3 (1 bit)
access : read-write

BRESTP : BRESTP
bits : 4 - 4 (1 bit)
access : read-write

BREGEN : BREGEN
bits : 5 - 5 (1 bit)
access : read-write

LBPEGEN : LBPEGEN
bits : 6 - 6 (1 bit)
access : read-write

BRDNOGEN : BRDNOGEN
bits : 7 - 7 (1 bit)
access : read-write

SFTOP : SFTOP
bits : 8 - 8 (1 bit)
access : read-write

OAR : OAR
bits : 16 - 30 (15 bit)
access : read-write

LSTN : LSTN
bits : 31 - 31 (1 bit)
access : read-write


CEC_TXDR

CEC Tx data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEC_TXDR CEC_TXDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXD

TXD : TXD
bits : 0 - 7 (8 bit)
access : write-only


CEC_RXDR

CEC Rx data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CEC_RXDR CEC_RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXD

RXD : RXD
bits : 0 - 7 (8 bit)
access : read-only



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