\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDIFRXEN : SPDIFRXEN
bits : 0 - 1 (2 bit)
access : read-write
RXDMAEN : RXDMAEN
bits : 2 - 2 (1 bit)
access : read-write
RXSTEO : RXSTEO
bits : 3 - 3 (1 bit)
access : read-write
DRFMT : DRFMT
bits : 4 - 5 (2 bit)
access : read-write
PMSK : PMSK
bits : 6 - 6 (1 bit)
access : read-write
VMSK : VMSK
bits : 7 - 7 (1 bit)
access : read-write
CUMSK : CUMSK
bits : 8 - 8 (1 bit)
access : read-write
PTMSK : PTMSK
bits : 9 - 9 (1 bit)
access : read-write
CBDMAEN : CBDMAEN
bits : 10 - 10 (1 bit)
access : read-write
CHSEL : CHSEL
bits : 11 - 11 (1 bit)
access : read-write
NBTR : NBTR
bits : 12 - 13 (2 bit)
access : read-write
WFA : WFA
bits : 14 - 14 (1 bit)
access : read-write
INSEL : INSEL
bits : 16 - 18 (3 bit)
access : read-write
CKSEN : CKSEN
bits : 20 - 20 (1 bit)
access : read-write
CKSBKPEN : CKSBKPEN
bits : 21 - 21 (1 bit)
access : read-write
This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00:
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DR : DR
bits : 0 - 23 (24 bit)
access : read-only
PE : PE
bits : 24 - 24 (1 bit)
access : read-only
V : V
bits : 25 - 25 (1 bit)
access : read-only
U : U
bits : 26 - 26 (1 bit)
access : read-only
C : C
bits : 27 - 27 (1 bit)
access : read-only
PT : PT
bits : 28 - 29 (2 bit)
access : read-only
Channel status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USR : USR
bits : 0 - 15 (16 bit)
access : read-only
CS : CS
bits : 16 - 23 (8 bit)
access : read-only
SOB : SOB
bits : 24 - 24 (1 bit)
access : read-only
Debug information register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
THI : THI
bits : 0 - 12 (13 bit)
access : read-only
TLO : TLO
bits : 16 - 28 (13 bit)
access : read-only
SPDIFRX version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
access : read-only
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
access : read-only
SPDIFRX identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
access : read-only
SPDIFRX size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
access : read-only
Interrupt mask register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNEIE : RXNEIE
bits : 0 - 0 (1 bit)
access : read-write
CSRNEIE : CSRNEIE
bits : 1 - 1 (1 bit)
access : read-write
PERRIE : PERRIE
bits : 2 - 2 (1 bit)
access : read-write
OVRIE : OVRIE
bits : 3 - 3 (1 bit)
access : read-write
SBLKIE : SBLKIE
bits : 4 - 4 (1 bit)
access : read-write
SYNCDIE : SYNCDIE
bits : 5 - 5 (1 bit)
access : read-write
IFEIE : IFEIE
bits : 6 - 6 (1 bit)
access : read-write
Status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXNE : RXNE
bits : 0 - 0 (1 bit)
access : read-only
CSRNE : CSRNE
bits : 1 - 1 (1 bit)
access : read-only
PERR : PERR
bits : 2 - 2 (1 bit)
access : read-only
OVR : OVR
bits : 3 - 3 (1 bit)
access : read-only
SBD : SBD
bits : 4 - 4 (1 bit)
access : read-only
SYNCD : SYNCD
bits : 5 - 5 (1 bit)
access : read-only
FERR : FERR
bits : 6 - 6 (1 bit)
access : read-only
SERR : SERR
bits : 7 - 7 (1 bit)
access : read-only
TERR : TERR
bits : 8 - 8 (1 bit)
access : read-only
WIDTH5 : WIDTH5
bits : 16 - 30 (15 bit)
access : read-only
Interrupt flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERRCF : PERRCF
bits : 2 - 2 (1 bit)
access : write-only
OVRCF : OVRCF
bits : 3 - 3 (1 bit)
access : write-only
SBDCF : SBDCF
bits : 4 - 4 (1 bit)
access : write-only
SYNCDCF : SYNCDCF
bits : 5 - 5 (1 bit)
access : write-only
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