\n
address_offset : 0x0 Bytes (0x0)
size : 0x100000 byte (0x0)
mem_usage : registers
protection :
AXIMC master 0 packing functionality register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : BYPASS_MERGE
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 1 packing functionality register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : BYPASS_MERGE
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 1 read priority register
address_offset : 0x10DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 1 write priority register
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 1 issuing capability override functionality register
address_offset : 0x10E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC peripheral ID4 register
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEP106CON : JEP106CON
bits : 0 - 3 (4 bit)
access : read-only
K4COUNT : K4COUNT
bits : 4 - 7 (4 bit)
access : read-only
AXIMC peripheral ID5 register
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_5 : PERIPH_ID_5
bits : 0 - 7 (8 bit)
access : read-only
AXIMC peripheral ID6 register
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_6 : PERIPH_ID_6
bits : 0 - 7 (8 bit)
access : read-only
AXIMC peripheral ID7 register
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_7 : PERIPH_ID_7
bits : 0 - 7 (8 bit)
access : read-only
AXIMC peripheral ID0 register
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_0 : PERIPH_ID_0
bits : 0 - 7 (8 bit)
access : read-only
AXIMC peripheral ID1 register
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_1 : PERIPH_ID_1
bits : 0 - 7 (8 bit)
access : read-only
AXIMC peripheral ID2 register
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPH_ID_2 : PERIPH_ID_2
bits : 0 - 7 (8 bit)
access : read-only
AXIMC peripheral ID3 register
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUST_MOD_NUM : CUST_MOD_NUM
bits : 0 - 3 (4 bit)
access : read-only
REV_AND : REV_AND
bits : 4 - 7 (4 bit)
access : read-only
AXIMC component ID0 register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : PREAMBLE
bits : 0 - 7 (8 bit)
access : read-only
AXIMC component ID1 register
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : PREAMBLE
bits : 0 - 3 (4 bit)
access : read-only
CLASS : CLASS
bits : 4 - 7 (4 bit)
access : read-only
AXIMC component ID2 register
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : PREAMBLE
bits : 0 - 7 (8 bit)
access : read-only
AXIMC component ID3 register
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : PREAMBLE
bits : 0 - 7 (8 bit)
access : read-only
AXIMC master 2 packing functionality register
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : BYPASS_MERGE
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 2 read priority register
address_offset : 0x20DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 2 write priority register
address_offset : 0x20E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 2 issuing capability override functionality register
address_offset : 0x20E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 5 packing functionality register
address_offset : 0x3000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : BYPASS_MERGE
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 5 read priority register
address_offset : 0x30DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 5 write priority register
address_offset : 0x30E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 5 issuing capability override functionality register
address_offset : 0x30E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 3 read priority register
address_offset : 0x40DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 3 write priority register
address_offset : 0x40E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 3 packing functionality register
address_offset : 0x40E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 0 AHB conversion override functionality register
address_offset : 0x42028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : RD_INC_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WR_INC_OVERRIDE : WR_INC_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 1 AHB conversion override functionality register
address_offset : 0x43028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : RD_INC_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WR_INC_OVERRIDE : WR_INC_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 2 AHB conversion override functionality register
address_offset : 0x44028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : RD_INC_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WR_INC_OVERRIDE : WR_INC_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 5 AHB conversion override functionality register
address_offset : 0x45028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : RD_INC_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WR_INC_OVERRIDE : WR_INC_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC long burst capability inhibition register
address_offset : 0x4A02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FN_MOD_LB : FN_MOD_LB
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 6 AHB conversion override functionality register
address_offset : 0x4D028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_INC_OVERRIDE : RD_INC_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WR_INC_OVERRIDE : WR_INC_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 7 read priority register
address_offset : 0x50DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 7 write priority register
address_offset : 0x50E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 7 issuing capability override functionality register
address_offset : 0x50E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 8 read priority register
address_offset : 0x60DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 8 write priority register
address_offset : 0x60E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 8 issuing capability override functionality register
address_offset : 0x60E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 4 packing functionality register
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : BYPASS_MERGE
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 4 read priority register
address_offset : 0x80DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 4 write priority register
address_offset : 0x80E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 4 packing functionality register
address_offset : 0x80E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 9 read priority register
address_offset : 0x90DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 9 write priority register
address_offset : 0x90E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 9 issuing capability override functionality register
address_offset : 0x90E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 10 read priority register
address_offset : 0xA0DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 10 write priority register
address_offset : 0xA0E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 10 issuing capability override functionality register
address_offset : 0xA0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 6 packing functionality register
address_offset : 0xB000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS_MERGE : BYPASS_MERGE
bits : 0 - 0 (1 bit)
access : read-write
AXIMC master 6 read priority register
address_offset : 0xB0DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 6 write priority register
address_offset : 0xB0E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 6 issuing capability override functionality register
address_offset : 0xB0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 0 read priority register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR_QOS : AR_QOS
bits : 0 - 3 (4 bit)
access : read-write
AXIMC master 0 issuing capability override functionality register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)
access : read-write
WRITE_ISS_OVERRIDE : WRITE_ISS_OVERRIDE
bits : 1 - 1 (1 bit)
access : read-write
AXIMC master 0 write priority register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AW_QOS : AW_QOS
bits : 0 - 3 (4 bit)
access : read-write
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