\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
TIM15 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write
UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write
URS : URS
bits : 2 - 2 (1 bit)
access : read-write
OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write
ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write
CKD : CKD
bits : 8 - 9 (2 bit)
access : read-write
UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write
TIM15 status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write
CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write
CC2IF : CC2IF
bits : 2 - 2 (1 bit)
access : read-write
COMIF : COMIF
bits : 5 - 5 (1 bit)
access : read-write
TIF : TIF
bits : 6 - 6 (1 bit)
access : read-write
BIF : BIF
bits : 7 - 7 (1 bit)
access : read-write
CC1OF : CC1OF
bits : 9 - 9 (1 bit)
access : read-write
CC2OF : CC2OF
bits : 10 - 10 (1 bit)
access : read-write
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation
bits : 0 - 0 (1 bit)
CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)
CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)
COMG : COMG
bits : 5 - 5 (1 bit)
TG : Trigger generation
bits : 6 - 6 (1 bit)
BG : BG
bits : 7 - 7 (1 bit)
capture/compare mode register 1 (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
OC1FE : Output compare 1 fast enable
bits : 2 - 2 (1 bit)
OC1PE : Output compare 1 preload enable
bits : 3 - 3 (1 bit)
OC1M : Output compare 1 mode
bits : 4 - 6 (3 bit)
OC1CE : Output compare 1 clear enable
bits : 7 - 7 (1 bit)
CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)
OC2FE : Output compare 2 fast enable
bits : 10 - 10 (1 bit)
OC2PE : Output compare 2 preload enable
bits : 11 - 11 (1 bit)
OC2M : Output compare 2 mode
bits : 12 - 14 (3 bit)
OC2CE : Output compare 2 clear enable
bits : 15 - 15 (1 bit)
OC1M_3 : Output Compare 1 mode - bit 3
bits : 16 - 16 (1 bit)
OC2M_3 : Output Compare 2 mode - bit 3
bits : 24 - 24 (1 bit)
capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIMx_CCMR1_Output
reset_Mask : 0x0
CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)
IC1PSC : Input capture 1 prescaler
bits : 2 - 3 (2 bit)
IC1F : Input capture 1 filter
bits : 4 - 7 (4 bit)
CC2S : Capture/compare 2 selection
bits : 8 - 9 (2 bit)
IC2PSC : Input capture 2 prescaler
bits : 10 - 11 (2 bit)
IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)
TIM15 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : CC1E
bits : 0 - 0 (1 bit)
access : read-write
CC1P : CC1P
bits : 1 - 1 (1 bit)
access : read-write
CC1NE : CC1NE
bits : 2 - 2 (1 bit)
access : read-write
CC1NP : CC1NP
bits : 3 - 3 (1 bit)
access : read-write
CC2E : CC2E
bits : 4 - 4 (1 bit)
access : read-write
CC2P : CC2P
bits : 5 - 5 (1 bit)
access : read-write
CC2NP : CC2NP
bits : 7 - 7 (1 bit)
access : read-write
TIM15 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write
UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only
TIM15 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC
bits : 0 - 15 (16 bit)
access : read-write
TIM15 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ARR
bits : 0 - 15 (16 bit)
access : read-write
TIM15 repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP : REP
bits : 0 - 7 (8 bit)
access : read-write
TIM15 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : CCR1
bits : 0 - 15 (16 bit)
access : read-write
TIM15 capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : CCR2
bits : 0 - 15 (16 bit)
access : read-write
TIM15 control register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPC : CCPC
bits : 0 - 0 (1 bit)
access : read-write
CCUS : CCUS
bits : 2 - 2 (1 bit)
access : read-write
CCDS : CCDS
bits : 3 - 3 (1 bit)
access : read-write
MMS : MMS
bits : 4 - 6 (3 bit)
access : read-write
TI1S : TI1S
bits : 7 - 7 (1 bit)
access : read-write
OIS1 : OIS1
bits : 8 - 8 (1 bit)
access : read-write
OIS1N : OIS1N
bits : 9 - 9 (1 bit)
access : read-write
OIS2 : OIS2
bits : 10 - 10 (1 bit)
access : read-write
As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTG : DTG
bits : 0 - 7 (8 bit)
access : read-write
LOCK : LOCK
bits : 8 - 9 (2 bit)
access : read-write
OSSI : OSSI
bits : 10 - 10 (1 bit)
access : read-write
OSSR : OSSR
bits : 11 - 11 (1 bit)
access : read-write
BKE : BKE
bits : 12 - 12 (1 bit)
access : read-write
BKP : BKP
bits : 13 - 13 (1 bit)
access : read-write
AOE : AOE
bits : 14 - 14 (1 bit)
access : read-write
MOE : MOE
bits : 15 - 15 (1 bit)
access : read-write
BKF : BKF
bits : 16 - 19 (4 bit)
access : read-write
BKDSRM : BKDSRM
bits : 26 - 26 (1 bit)
access : read-write
BKBID : BKBID
bits : 28 - 28 (1 bit)
access : read-write
TIM15 DMA control register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DBA
bits : 0 - 4 (5 bit)
access : read-write
DBL : DBL
bits : 8 - 12 (5 bit)
access : read-write
TIM15 DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMAB
bits : 0 - 15 (16 bit)
access : read-write
TIM15 alternate register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKINE : BKINE
bits : 0 - 0 (1 bit)
access : read-write
BKDF1BK0E : BKDF1BK0E
bits : 8 - 8 (1 bit)
access : read-write
BKINP : BKINP
bits : 9 - 9 (1 bit)
access : read-write
TIM15 input selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
access : read-write
TI2SEL : TI2SEL
bits : 8 - 11 (4 bit)
access : read-write
slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : Slave mode selection
bits : 0 - 2 (3 bit)
TS : Trigger selection
bits : 4 - 6 (3 bit)
MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
SMS_3 : Slave mode selection - bit 3
bits : 16 - 16 (1 bit)
TS_4_3 : Trigger selection
bits : 20 - 21 (2 bit)
TIM15 DMA/interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write
CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write
CC2IE : CC2IE
bits : 2 - 2 (1 bit)
access : read-write
COMIE : COMIE
bits : 5 - 5 (1 bit)
access : read-write
TIE : TIE
bits : 6 - 6 (1 bit)
access : read-write
BIE : BIE
bits : 7 - 7 (1 bit)
access : read-write
UDE : UDE
bits : 8 - 8 (1 bit)
access : read-write
CC1DE : CC1DE
bits : 9 - 9 (1 bit)
access : read-write
CC2DE : CC2DE
bits : 10 - 10 (1 bit)
access : read-write
COMDE : COMDE
bits : 13 - 13 (1 bit)
access : read-write
TDE : TDE
bits : 14 - 14 (1 bit)
access : read-write
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