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TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TIMx_CR1

TIMx_SR

TIMx_EGR

TIMx_CCER

TIMx_CNT

TIMx_PSC

TIMx_ARR

TIMx_RCR

TIMx_CCR1

TIMx_CR2

TIMx_BDTR

TIMx_DCR

TIMx_DMAR

TIM17_AF1 (TIMx_AF1)

TIM17_TISEL (TIMx_TISEL)

TIMx_DIER


TIMx_CR1

TIM16/TIM17 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CR1 TIMx_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM ARPE CKD UIFREMAP

CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write

UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write

URS : URS
bits : 2 - 2 (1 bit)
access : read-write

OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write

ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write

CKD : CKD
bits : 8 - 9 (2 bit)
access : read-write

UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write


TIMx_SR

TIM16/TIM17 status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_SR TIMx_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF COMIF BIF CC1OF

UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write

CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write

COMIF : COMIF
bits : 5 - 5 (1 bit)
access : read-write

BIF : BIF
bits : 7 - 7 (1 bit)
access : read-write

CC1OF : CC1OF
bits : 9 - 9 (1 bit)
access : read-write


TIMx_EGR

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TIMx_EGR TIMx_EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG

UG : Update generation
bits : 0 - 0 (1 bit)


TIMx_CCER

TIM16/TIM17 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CCER TIMx_CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NE CC1NP

CC1E : CC1E
bits : 0 - 0 (1 bit)
access : read-write

CC1P : CC1P
bits : 1 - 1 (1 bit)
access : read-write

CC1NE : CC1NE
bits : 2 - 2 (1 bit)
access : read-write

CC1NP : CC1NP
bits : 3 - 3 (1 bit)
access : read-write


TIMx_CNT

TIM16/TIM17 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CNT TIMx_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT UIFCPY

CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write

UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only


TIMx_PSC

TIM16/TIM17 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_PSC TIMx_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 15 (16 bit)
access : read-write


TIMx_ARR

TIM16/TIM17 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_ARR TIMx_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)
access : read-write


TIMx_RCR

TIM16/TIM17 repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_RCR TIMx_RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP

REP : REP
bits : 0 - 7 (8 bit)
access : read-write


TIMx_CCR1

TIM16/TIM17 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CCR1 TIMx_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : CCR1
bits : 0 - 15 (16 bit)
access : read-write


TIMx_CR2

TIM16/TIM17 control register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_CR2 TIMx_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCPC CCUS CCDS OIS1 OIS1N

CCPC : CCPC
bits : 0 - 0 (1 bit)
access : read-write

CCUS : CCUS
bits : 2 - 2 (1 bit)
access : read-write

CCDS : CCDS
bits : 3 - 3 (1 bit)
access : read-write

OIS1 : OIS1
bits : 8 - 8 (1 bit)
access : read-write

OIS1N : OIS1N
bits : 9 - 9 (1 bit)
access : read-write


TIMx_BDTR

As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_BDTR TIMx_BDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTG LOCK OSSI OSSR BKE BKP AOE MOE BKF BKDSRM BKBID

DTG : DTG
bits : 0 - 7 (8 bit)
access : read-write

LOCK : LOCK
bits : 8 - 9 (2 bit)
access : read-write

OSSI : OSSI
bits : 10 - 10 (1 bit)
access : read-write

OSSR : OSSR
bits : 11 - 11 (1 bit)
access : read-write

BKE : BKE
bits : 12 - 12 (1 bit)
access : read-write

BKP : BKP
bits : 13 - 13 (1 bit)
access : read-write

AOE : AOE
bits : 14 - 14 (1 bit)
access : read-write

MOE : MOE
bits : 15 - 15 (1 bit)
access : read-write

BKF : BKF
bits : 16 - 19 (4 bit)
access : read-write

BKDSRM : BKDSRM
bits : 26 - 26 (1 bit)
access : read-write

BKBID : BKBID
bits : 28 - 28 (1 bit)
access : read-write


TIMx_DCR

TIM16/TIM17 DMA control register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_DCR TIMx_DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA DBL

DBA : DBA
bits : 0 - 4 (5 bit)
access : read-write

DBL : DBL
bits : 8 - 12 (5 bit)
access : read-write


TIMx_DMAR

TIM16/TIM17 DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_DMAR TIMx_DMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAB

DMAB : DMAB
bits : 0 - 15 (16 bit)
access : read-write


TIM17_AF1 (TIMx_AF1)

TIM17 alternate function register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM17_AF1 TIM17_AF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKINE BKDF1BK2E BKINP

BKINE : BKINE
bits : 0 - 0 (1 bit)
access : read-write

BKDF1BK2E : BKDF1BK2E
bits : 8 - 8 (1 bit)
access : read-write

BKINP : BKINP
bits : 9 - 9 (1 bit)
access : read-write


TIM17_TISEL (TIMx_TISEL)

TIM17 input selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM17_TISEL TIM17_TISEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI1SEL

TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
access : read-write


TIMx_DIER

TIM16/TIM17 DMA/interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMx_DIER TIMx_DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE COMIE BIE UDE CC1DE COMDE

UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write

CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write

COMIE : COMIE
bits : 5 - 5 (1 bit)
access : read-write

BIE : BIE
bits : 7 - 7 (1 bit)
access : read-write

UDE : UDE
bits : 8 - 8 (1 bit)
access : read-write

CC1DE : CC1DE
bits : 9 - 9 (1 bit)
access : read-write

COMDE : COMDE
bits : 13 - 13 (1 bit)
access : read-write



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