\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
TIM16/TIM17 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : CEN
bits : 0 - 0 (1 bit)
access : read-write
UDIS : UDIS
bits : 1 - 1 (1 bit)
access : read-write
URS : URS
bits : 2 - 2 (1 bit)
access : read-write
OPM : OPM
bits : 3 - 3 (1 bit)
access : read-write
ARPE : ARPE
bits : 7 - 7 (1 bit)
access : read-write
CKD : CKD
bits : 8 - 9 (2 bit)
access : read-write
UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)
access : read-write
TIM16/TIM17 status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write
CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write
COMIF : COMIF
bits : 5 - 5 (1 bit)
access : read-write
BIF : BIF
bits : 7 - 7 (1 bit)
access : read-write
CC1OF : CC1OF
bits : 9 - 9 (1 bit)
access : read-write
event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation
bits : 0 - 0 (1 bit)
TIM16/TIM17 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : CC1E
bits : 0 - 0 (1 bit)
access : read-write
CC1P : CC1P
bits : 1 - 1 (1 bit)
access : read-write
CC1NE : CC1NE
bits : 2 - 2 (1 bit)
access : read-write
CC1NP : CC1NP
bits : 3 - 3 (1 bit)
access : read-write
TIM16/TIM17 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
access : read-write
UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)
access : read-only
TIM16/TIM17 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC
bits : 0 - 15 (16 bit)
access : read-write
TIM16/TIM17 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ARR
bits : 0 - 15 (16 bit)
access : read-write
TIM16/TIM17 repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP : REP
bits : 0 - 7 (8 bit)
access : read-write
TIM16/TIM17 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : CCR1
bits : 0 - 15 (16 bit)
access : read-write
TIM16/TIM17 control register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPC : CCPC
bits : 0 - 0 (1 bit)
access : read-write
CCUS : CCUS
bits : 2 - 2 (1 bit)
access : read-write
CCDS : CCDS
bits : 3 - 3 (1 bit)
access : read-write
OIS1 : OIS1
bits : 8 - 8 (1 bit)
access : read-write
OIS1N : OIS1N
bits : 9 - 9 (1 bit)
access : read-write
As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTG : DTG
bits : 0 - 7 (8 bit)
access : read-write
LOCK : LOCK
bits : 8 - 9 (2 bit)
access : read-write
OSSI : OSSI
bits : 10 - 10 (1 bit)
access : read-write
OSSR : OSSR
bits : 11 - 11 (1 bit)
access : read-write
BKE : BKE
bits : 12 - 12 (1 bit)
access : read-write
BKP : BKP
bits : 13 - 13 (1 bit)
access : read-write
AOE : AOE
bits : 14 - 14 (1 bit)
access : read-write
MOE : MOE
bits : 15 - 15 (1 bit)
access : read-write
BKF : BKF
bits : 16 - 19 (4 bit)
access : read-write
BKDSRM : BKDSRM
bits : 26 - 26 (1 bit)
access : read-write
BKBID : BKBID
bits : 28 - 28 (1 bit)
access : read-write
TIM16/TIM17 DMA control register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBA : DBA
bits : 0 - 4 (5 bit)
access : read-write
DBL : DBL
bits : 8 - 12 (5 bit)
access : read-write
TIM16/TIM17 DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAB : DMAB
bits : 0 - 15 (16 bit)
access : read-write
TIM17 alternate function register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKINE : BKINE
bits : 0 - 0 (1 bit)
access : read-write
BKDF1BK2E : BKDF1BK2E
bits : 8 - 8 (1 bit)
access : read-write
BKINP : BKINP
bits : 9 - 9 (1 bit)
access : read-write
TIM17 input selection register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)
access : read-write
TIM16/TIM17 DMA/interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : UIE
bits : 0 - 0 (1 bit)
access : read-write
CC1IE : CC1IE
bits : 1 - 1 (1 bit)
access : read-write
COMIE : COMIE
bits : 5 - 5 (1 bit)
access : read-write
BIE : BIE
bits : 7 - 7 (1 bit)
access : read-write
UDE : UDE
bits : 8 - 8 (1 bit)
access : read-write
CC1DE : CC1DE
bits : 9 - 9 (1 bit)
access : read-write
COMDE : COMDE
bits : 13 - 13 (1 bit)
access : read-write
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