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DCMI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DCMI_CR (CR)

DCMI_MIS (MIS)

DCMI_ICR (ICR)

DCMI_ESCR (ESCR)

DCMI_ESUR (ESUR)

DCMI_CWSTRT (CWSTRT)

DCMI_CWSIZE (CWSIZE)

DCMI_DR (DR)

DCMI_SR (SR)

DCMI_RIS (RIS)

DCMI_IER (IER)


DCMI_CR (CR)

DCMI control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCMI_CR DCMI_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTURE CM CROP JPEG ESS PCKPOL HSPOL VSPOL FCRC EDM ENABLE BSM OEBS LSM OELS

CAPTURE : CAPTURE
bits : 0 - 0 (1 bit)

CM : CM
bits : 1 - 1 (1 bit)

CROP : CROP
bits : 2 - 2 (1 bit)

JPEG : JPEG
bits : 3 - 3 (1 bit)

ESS : ESS
bits : 4 - 4 (1 bit)

PCKPOL : PCKPOL
bits : 5 - 5 (1 bit)

HSPOL : HSPOL
bits : 6 - 6 (1 bit)

VSPOL : VSPOL
bits : 7 - 7 (1 bit)

FCRC : FCRC
bits : 8 - 9 (2 bit)

EDM : EDM
bits : 10 - 11 (2 bit)

ENABLE : ENABLE
bits : 14 - 14 (1 bit)

BSM : BSM
bits : 16 - 17 (2 bit)

OEBS : OEBS
bits : 18 - 18 (1 bit)

LSM : LSM
bits : 19 - 19 (1 bit)

OELS : OELS
bits : 20 - 20 (1 bit)


DCMI_MIS (MIS)

This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCMI_MIS DCMI_MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_MIS OVR_MIS ERR_MIS VSYNC_MIS LINE_MIS

FRAME_MIS : FRAME_MIS
bits : 0 - 0 (1 bit)

OVR_MIS : OVR_MIS
bits : 1 - 1 (1 bit)

ERR_MIS : ERR_MIS
bits : 2 - 2 (1 bit)

VSYNC_MIS : VSYNC_MIS
bits : 3 - 3 (1 bit)

LINE_MIS : LINE_MIS
bits : 4 - 4 (1 bit)


DCMI_ICR (ICR)

The DCMI_ICR register is write-only.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DCMI_ICR DCMI_ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_ISC OVR_ISC ERR_ISC VSYNC_ISC LINE_ISC

FRAME_ISC : FRAME_ISC
bits : 0 - 0 (1 bit)

OVR_ISC : OVR_ISC
bits : 1 - 1 (1 bit)

ERR_ISC : ERR_ISC
bits : 2 - 2 (1 bit)

VSYNC_ISC : VSYNC_ISC
bits : 3 - 3 (1 bit)

LINE_ISC : LINE_ISC
bits : 4 - 4 (1 bit)


DCMI_ESCR (ESCR)

DCMI embedded synchronization code register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCMI_ESCR DCMI_ESCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSC LSC LEC FEC

FSC : FSC
bits : 0 - 7 (8 bit)

LSC : LSC
bits : 8 - 15 (8 bit)

LEC : LEC
bits : 16 - 23 (8 bit)

FEC : FEC
bits : 24 - 31 (8 bit)


DCMI_ESUR (ESUR)

DCMI embedded synchronization unmask register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCMI_ESUR DCMI_ESUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSU LSU LEU FEU

FSU : FSU
bits : 0 - 7 (8 bit)

LSU : LSU
bits : 8 - 15 (8 bit)

LEU : LEU
bits : 16 - 23 (8 bit)

FEU : FEU
bits : 24 - 31 (8 bit)


DCMI_CWSTRT (CWSTRT)

DCMI crop window start
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCMI_CWSTRT DCMI_CWSTRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOFFCNT VST

HOFFCNT : HOFFCNT
bits : 0 - 13 (14 bit)

VST : VST
bits : 16 - 28 (13 bit)


DCMI_CWSIZE (CWSIZE)

DCMI crop window size
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCMI_CWSIZE DCMI_CWSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPCNT VLINE

CAPCNT : CAPCNT
bits : 0 - 13 (14 bit)

VLINE : VLINE
bits : 16 - 29 (14 bit)


DCMI_DR (DR)

DCMI data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCMI_DR DCMI_DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Byte0 Byte1 Byte2 Byte3

Byte0 : Byte0
bits : 0 - 7 (8 bit)

Byte1 : Byte1
bits : 8 - 15 (8 bit)

Byte2 : Byte2
bits : 16 - 23 (8 bit)

Byte3 : Byte3
bits : 24 - 31 (8 bit)


DCMI_SR (SR)

DCMI status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCMI_SR DCMI_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSYNC VSYNC FNE

HSYNC : HSYNC
bits : 0 - 0 (1 bit)

VSYNC : VSYNC
bits : 1 - 1 (1 bit)

FNE : FNE
bits : 2 - 2 (1 bit)


DCMI_RIS (RIS)

DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCMI_RIS DCMI_RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_RIS OVR_RIS ERR_RIS VSYNC_RIS LINE_RIS

FRAME_RIS : FRAME_RIS
bits : 0 - 0 (1 bit)

OVR_RIS : OVR_RIS
bits : 1 - 1 (1 bit)

ERR_RIS : ERR_RIS
bits : 2 - 2 (1 bit)

VSYNC_RIS : VSYNC_RIS
bits : 3 - 3 (1 bit)

LINE_RIS : LINE_RIS
bits : 4 - 4 (1 bit)


DCMI_IER (IER)

The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCMI_IER DCMI_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_IE OVR_IE ERR_IE VSYNC_IE LINE_IE

FRAME_IE : FRAME_IE
bits : 0 - 0 (1 bit)

OVR_IE : OVR_IE
bits : 1 - 1 (1 bit)

ERR_IE : ERR_IE
bits : 2 - 2 (1 bit)

VSYNC_IE : VSYNC_IE
bits : 3 - 3 (1 bit)

LINE_IE : LINE_IE
bits : 4 - 4 (1 bit)



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