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address_offset : 0x0 Bytes (0x0)
size : 0xBD4 byte (0x0)
mem_usage : registers
protection :
The MAC Configuration Register establishes the operating mode of the MAC.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE : RE
bits : 0 - 0 (1 bit)
access : read-write
TE : TE
bits : 1 - 1 (1 bit)
access : read-write
PRELEN : PRELEN
bits : 2 - 3 (2 bit)
access : read-write
DC : DC
bits : 4 - 4 (1 bit)
access : read-write
BL : BL
bits : 5 - 6 (2 bit)
access : read-write
DR : DR
bits : 8 - 8 (1 bit)
access : read-write
DCRS : DCRS
bits : 9 - 9 (1 bit)
access : read-write
DO : DO
bits : 10 - 10 (1 bit)
access : read-write
ECRSFD : ECRSFD
bits : 11 - 11 (1 bit)
access : read-write
LM : LM
bits : 12 - 12 (1 bit)
access : read-write
DM : DM
bits : 13 - 13 (1 bit)
access : read-write
FES : FES
bits : 14 - 14 (1 bit)
access : read-write
PS : PS
bits : 15 - 15 (1 bit)
access : read-write
JE : JE
bits : 16 - 16 (1 bit)
access : read-write
JD : JD
bits : 17 - 17 (1 bit)
access : read-write
BE : BE
bits : 18 - 18 (1 bit)
access : read-write
WD : WD
bits : 19 - 19 (1 bit)
access : read-write
ACS : ACS
bits : 20 - 20 (1 bit)
access : read-write
CST : CST
bits : 21 - 21 (1 bit)
access : read-write
S2KP : S2KP
bits : 22 - 22 (1 bit)
access : read-write
GPSLCE : GPSLCE
bits : 23 - 23 (1 bit)
access : read-write
IPG : IPG
bits : 24 - 26 (3 bit)
access : read-write
IPC : IPC
bits : 27 - 27 (1 bit)
access : read-write
SARC : SARC
bits : 28 - 30 (3 bit)
access : read-write
ARPEN : ARPEN
bits : 31 - 31 (1 bit)
access : read-write
The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT31T0 : HT31T0
bits : 0 - 31 (32 bit)
access : read-write
The version register identifies the version of the Ethernet peripheral.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SNPSVER : SNPSVER
bits : 0 - 7 (8 bit)
access : read-only
USERVER : USERVER
bits : 8 - 15 (8 bit)
access : read-only
The Debug register provides the debug status of various MAC blocks.
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPESTS : RPESTS
bits : 0 - 0 (1 bit)
access : read-only
RFCFCSTS : RFCFCSTS
bits : 1 - 2 (2 bit)
access : read-only
TPESTS : TPESTS
bits : 16 - 16 (1 bit)
access : read-only
TFCSTS : TFCSTS
bits : 17 - 18 (2 bit)
access : read-only
This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXFIFOSIZE : RXFIFOSIZE
bits : 0 - 4 (5 bit)
access : read-only
TXFIFOSIZE : TXFIFOSIZE
bits : 6 - 10 (5 bit)
access : read-only
OSTEN : OSTEN
bits : 11 - 11 (1 bit)
access : read-only
PTOEN : PTOEN
bits : 12 - 12 (1 bit)
access : read-only
ADVTHWORD : ADVTHWORD
bits : 13 - 13 (1 bit)
access : read-only
ADDR64 : ADDR64
bits : 14 - 15 (2 bit)
access : read-only
DCBEN : DCBEN
bits : 16 - 16 (1 bit)
access : read-only
SPHEN : SPHEN
bits : 17 - 17 (1 bit)
access : read-only
TSOEN : TSOEN
bits : 18 - 18 (1 bit)
access : read-only
DBGMEMA : DBGMEMA
bits : 19 - 19 (1 bit)
access : read-only
AVSEL : AVSEL
bits : 20 - 20 (1 bit)
access : read-only
HASHTBLSZ : HASHTBLSZ
bits : 24 - 25 (2 bit)
access : read-only
L3L4FNUM : L3L4FNUM
bits : 27 - 30 (4 bit)
access : read-only
This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXQCNT : RXQCNT
bits : 0 - 3 (4 bit)
access : read-only
TXQCNT : TXQCNT
bits : 6 - 9 (4 bit)
access : read-only
RXCHCNT : RXCHCNT
bits : 12 - 15 (4 bit)
access : read-only
TXCHCNT : TXCHCNT
bits : 18 - 21 (4 bit)
access : read-only
PPSOUTNUM : PPSOUTNUM
bits : 24 - 26 (3 bit)
access : read-only
AUXSNAPNUM : AUXSNAPNUM
bits : 28 - 30 (3 bit)
access : read-only
The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT63T32 : HT63T32
bits : 0 - 31 (32 bit)
access : read-write
The MDIO Address register controls the management cycles to external PHY through a management interface.
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GB : GB
bits : 0 - 0 (1 bit)
access : read-write
C45E : C45E
bits : 1 - 1 (1 bit)
access : read-write
GOC : GOC
bits : 2 - 3 (2 bit)
access : read-write
SKAP : SKAP
bits : 4 - 4 (1 bit)
access : read-write
CR : CR
bits : 8 - 11 (4 bit)
access : read-write
NTC : NTC
bits : 12 - 14 (3 bit)
access : read-write
RDA : RDA
bits : 16 - 20 (5 bit)
access : read-write
PA : PA
bits : 21 - 25 (5 bit)
access : read-write
BTB : BTB
bits : 26 - 26 (1 bit)
access : read-write
PSE : PSE
bits : 27 - 27 (1 bit)
access : read-write
The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register.
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GD : GD
bits : 0 - 15 (16 bit)
access : read-write
RA : RA
bits : 16 - 31 (16 bit)
access : read-write
The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
access : read-write
AE : AE
bits : 31 - 31 (1 bit)
access : read-only
The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
access : read-write
The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
access : read-write
MBC : MBC
bits : 24 - 29 (6 bit)
access : read-write
SA : SA
bits : 30 - 30 (1 bit)
access : read-write
AE : AE
bits : 31 - 31 (1 bit)
access : read-write
The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
access : read-write
The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
access : read-write
MBC : MBC
bits : 24 - 29 (6 bit)
access : read-write
SA : SA
bits : 30 - 30 (1 bit)
access : read-write
AE : AE
bits : 31 - 31 (1 bit)
access : read-write
The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
access : read-write
The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
access : read-write
MBC : MBC
bits : 24 - 29 (6 bit)
access : read-write
SA : SA
bits : 30 - 30 (1 bit)
access : read-write
AE : AE
bits : 31 - 31 (1 bit)
access : read-write
The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
access : read-write
The MAC Extended Configuration Register establishes the operating mode of the MAC.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPSL : GPSL
bits : 0 - 13 (14 bit)
access : read-write
DCRCC : DCRCC
bits : 16 - 16 (1 bit)
access : read-write
SPEN : SPEN
bits : 17 - 17 (1 bit)
access : read-write
USP : USP
bits : 18 - 18 (1 bit)
access : read-write
EIPGEN : EIPGEN
bits : 24 - 24 (1 bit)
access : read-write
EIPG : EIPG
bits : 25 - 29 (5 bit)
access : read-write
The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VL : VL
bits : 0 - 15 (16 bit)
access : read-write
ETV : ETV
bits : 16 - 16 (1 bit)
access : read-write
VTIM : VTIM
bits : 17 - 17 (1 bit)
access : read-write
ESVL : ESVL
bits : 18 - 18 (1 bit)
access : read-write
ERSVLM : ERSVLM
bits : 19 - 19 (1 bit)
access : read-write
DOVLTC : DOVLTC
bits : 20 - 20 (1 bit)
access : read-write
EVLS : EVLS
bits : 21 - 22 (2 bit)
access : read-write
EVLRXS : EVLRXS
bits : 24 - 24 (1 bit)
access : read-write
VTHM : VTHM
bits : 25 - 25 (1 bit)
access : read-write
EDVLP : EDVLP
bits : 26 - 26 (1 bit)
access : read-write
ERIVLT : ERIVLT
bits : 27 - 27 (1 bit)
access : read-write
EIVLS : EIVLS
bits : 28 - 29 (2 bit)
access : read-write
EIVLRXS : EIVLRXS
bits : 31 - 31 (1 bit)
access : read-write
When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). Perform bitwise reversal for the value obtained in step 1. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLHT : VLHT
bits : 0 - 15 (16 bit)
access : read-write
The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLT : VLT
bits : 0 - 15 (16 bit)
access : read-write
VLC : VLC
bits : 16 - 17 (2 bit)
access : read-write
VLP : VLP
bits : 18 - 18 (1 bit)
access : read-write
CSVL : CSVL
bits : 19 - 19 (1 bit)
access : read-write
VLTI : VLTI
bits : 20 - 20 (1 bit)
access : read-write
The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLT : VLT
bits : 0 - 15 (16 bit)
access : read-write
VLC : VLC
bits : 16 - 17 (2 bit)
access : read-write
VLP : VLP
bits : 18 - 18 (1 bit)
access : read-write
CSVL : CSVL
bits : 19 - 19 (1 bit)
access : read-write
VLTI : VLTI
bits : 20 - 20 (1 bit)
access : read-write
The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCB_BPA : FCB_BPA
bits : 0 - 0 (1 bit)
access : read-write
TFE : TFE
bits : 1 - 1 (1 bit)
access : read-write
PLT : PLT
bits : 4 - 6 (3 bit)
access : read-write
DZPQ : DZPQ
bits : 7 - 7 (1 bit)
access : read-write
PT : PT
bits : 16 - 31 (16 bit)
access : read-write
This register configures the MMC operating mode.
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTRST : CNTRST
bits : 0 - 0 (1 bit)
access : read-write
CNTSTOPRO : CNTSTOPRO
bits : 1 - 1 (1 bit)
access : read-write
RSTONRD : RSTONRD
bits : 2 - 2 (1 bit)
access : read-write
CNTFREEZ : CNTFREEZ
bits : 3 - 3 (1 bit)
access : read-write
CNTPRST : CNTPRST
bits : 4 - 4 (1 bit)
access : read-write
CNTPRSTLVL : CNTPRSTLVL
bits : 5 - 5 (1 bit)
access : read-write
UCDBC : UCDBC
bits : 8 - 8 (1 bit)
access : read-write
This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCRCERPIS : RXCRCERPIS
bits : 5 - 5 (1 bit)
access : read-only
RXALGNERPIS : RXALGNERPIS
bits : 6 - 6 (1 bit)
access : read-only
RXUCGPIS : RXUCGPIS
bits : 17 - 17 (1 bit)
access : read-only
RXLPIUSCIS : RXLPIUSCIS
bits : 26 - 26 (1 bit)
access : read-only
RXLPITRCIS : RXLPITRCIS
bits : 27 - 27 (1 bit)
access : read-only
This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXSCOLGPIS : TXSCOLGPIS
bits : 14 - 14 (1 bit)
access : read-only
TXMCOLGPIS : TXMCOLGPIS
bits : 15 - 15 (1 bit)
access : read-only
TXGPKTIS : TXGPKTIS
bits : 21 - 21 (1 bit)
access : read-only
TXLPIUSCIS : TXLPIUSCIS
bits : 26 - 26 (1 bit)
access : read-only
TXLPITRCIS : TXLPITRCIS
bits : 27 - 27 (1 bit)
access : read-only
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values.
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCRCERPIM : RXCRCERPIM
bits : 5 - 5 (1 bit)
access : read-write
RXALGNERPIM : RXALGNERPIM
bits : 6 - 6 (1 bit)
access : read-write
RXUCGPIM : RXUCGPIM
bits : 17 - 17 (1 bit)
access : read-write
RXLPIUSCIM : RXLPIUSCIM
bits : 26 - 26 (1 bit)
access : read-write
RXLPITRCIM : RXLPITRCIM
bits : 27 - 27 (1 bit)
access : read-only
This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration.
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSCOLGPIM : TXSCOLGPIM
bits : 14 - 14 (1 bit)
access : read-write
TXMCOLGPIM : TXMCOLGPIM
bits : 15 - 15 (1 bit)
access : read-write
TXGPKTIM : TXGPKTIM
bits : 21 - 21 (1 bit)
access : read-write
TXLPIUSCIM : TXLPIUSCIM
bits : 26 - 26 (1 bit)
access : read-write
TXLPITRCIM : TXLPITRCIM
bits : 27 - 27 (1 bit)
access : read-only
This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode.
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXSNGLCOLG : TXSNGLCOLG
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode.
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXMULTCOLG : TXMULTCOLG
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of good packets transmitted by Ethernet peripheral.
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTG : TXPKTG
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of packets received by Ethernet peripheral with CRC error.
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCRCERR : RXCRCERR
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode.
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXALGNERR : RXALGNERR
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of good unicast packets received by Ethernet peripheral.
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXUCASTG : RXUCASTG
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral.
address_offset : 0x7EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXLPIUSC : TXLPIUSC
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of times Ethernet peripheral has entered Tx LPI.
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXLPITRC : TXLPITRC
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral.
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXLPIUSC : RXLPIUSC
bits : 0 - 31 (32 bit)
access : read-only
This register provides the number of times Ethernet peripheral has entered Rx LPI.
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXLPITRC : RXLPITRC
bits : 0 - 31 (32 bit)
access : read-only
The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : PR
bits : 0 - 0 (1 bit)
access : read-write
HUC : HUC
bits : 1 - 1 (1 bit)
access : read-write
HMC : HMC
bits : 2 - 2 (1 bit)
access : read-write
DAIF : DAIF
bits : 3 - 3 (1 bit)
access : read-write
PM : PM
bits : 4 - 4 (1 bit)
access : read-write
DBF : DBF
bits : 5 - 5 (1 bit)
access : read-write
PCF : PCF
bits : 6 - 7 (2 bit)
access : read-write
SAIF : SAIF
bits : 8 - 8 (1 bit)
access : read-write
SAF : SAF
bits : 9 - 9 (1 bit)
access : read-write
HPF : HPF
bits : 10 - 10 (1 bit)
access : read-write
VTFE : VTFE
bits : 16 - 16 (1 bit)
access : read-write
IPFE : IPFE
bits : 20 - 20 (1 bit)
access : read-write
DNTU : DNTU
bits : 21 - 21 (1 bit)
access : read-write
RA : RA
bits : 31 - 31 (1 bit)
access : read-write
The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RFE
bits : 0 - 0 (1 bit)
access : read-write
UP : UP
bits : 1 - 1 (1 bit)
access : read-write
The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3PEN0 : L3PEN0
bits : 0 - 0 (1 bit)
access : read-write
L3SAM0 : L3SAM0
bits : 2 - 2 (1 bit)
access : read-write
L3SAIM0 : L3SAIM0
bits : 3 - 3 (1 bit)
access : read-write
L3DAM0 : L3DAM0
bits : 4 - 4 (1 bit)
access : read-write
L3DAIM0 : L3DAIM0
bits : 5 - 5 (1 bit)
access : read-write
L3HSBM0 : L3HSBM0
bits : 6 - 10 (5 bit)
access : read-write
L3HDBM0 : L3HDBM0
bits : 11 - 15 (5 bit)
access : read-write
L4PEN0 : L4PEN0
bits : 16 - 16 (1 bit)
access : read-write
L4SPM0 : L4SPM0
bits : 18 - 18 (1 bit)
access : read-write
L4SPIM0 : L4SPIM0
bits : 19 - 19 (1 bit)
access : read-write
L4DPM0 : L4DPM0
bits : 20 - 20 (1 bit)
access : read-write
L4DPIM0 : L4DPIM0
bits : 21 - 21 (1 bit)
access : read-write
Layer4 address filter 0 register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L4SP0 : L4SP0
bits : 0 - 15 (16 bit)
access : read-write
L4DP0 : L4DP0
bits : 16 - 31 (16 bit)
access : read-write
For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A00 : L3A00
bits : 0 - 31 (32 bit)
access : read-write
For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A10 : L3A10
bits : 0 - 31 (32 bit)
access : read-write
The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A20 : L3A20
bits : 0 - 31 (32 bit)
access : read-write
The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A30 : L3A30
bits : 0 - 31 (32 bit)
access : read-write
The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3PEN1 : L3PEN1
bits : 0 - 0 (1 bit)
access : read-write
L3SAM1 : L3SAM1
bits : 2 - 2 (1 bit)
access : read-write
L3SAIM1 : L3SAIM1
bits : 3 - 3 (1 bit)
access : read-write
L3DAM1 : L3DAM1
bits : 4 - 4 (1 bit)
access : read-write
L3DAIM1 : L3DAIM1
bits : 5 - 5 (1 bit)
access : read-write
L3HSBM1 : L3HSBM1
bits : 6 - 10 (5 bit)
access : read-write
L3HDBM1 : L3HDBM1
bits : 11 - 15 (5 bit)
access : read-write
L4PEN1 : L4PEN1
bits : 16 - 16 (1 bit)
access : read-write
L4SPM1 : L4SPM1
bits : 18 - 18 (1 bit)
access : read-write
L4SPIM1 : L4SPIM1
bits : 19 - 19 (1 bit)
access : read-write
L4DPM1 : L4DPM1
bits : 20 - 20 (1 bit)
access : read-write
L4DPIM1 : L4DPIM1
bits : 21 - 21 (1 bit)
access : read-write
The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L4SP1 : L4SP1
bits : 0 - 15 (16 bit)
access : read-write
L4DP1 : L4DP1
bits : 16 - 31 (16 bit)
access : read-write
For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A01 : L3A01
bits : 0 - 31 (32 bit)
access : read-write
For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A11 : L3A11
bits : 0 - 31 (32 bit)
access : read-write
The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A21 : L3A21
bits : 0 - 31 (32 bit)
access : read-write
The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A31 : L3A31
bits : 0 - 31 (32 bit)
access : read-write
The transmit queue priority mapping 0 register contains the priority values assigned to Tx queue 0 and tx queue 1.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PSTQ0 : PSTQ0
bits : 0 - 7 (8 bit)
access : read-only
PSTQ1 : PSTQ1
bits : 8 - 15 (8 bit)
access : read-only
The Receive Queue Control 0 register controls the queue management in the MAC Receiver.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXQ0EN : RXQ0EN
bits : 0 - 1 (2 bit)
access : read-write
RXQ1EN : RXQ1EN
bits : 2 - 3 (2 bit)
access : read-write
The Receive Queue Control 1 register controls queue 1 management in the MAC receiver.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AVCPQ : AVCPQ
bits : 0 - 2 (3 bit)
access : read-write
AVPTPQ : AVPTPQ
bits : 4 - 6 (3 bit)
access : read-write
UPQ : UPQ
bits : 12 - 14 (3 bit)
access : read-write
MCBCQ : MCBCQ
bits : 16 - 18 (3 bit)
access : read-write
MCBCQEN : MCBCQEN
bits : 20 - 20 (1 bit)
access : read-write
TACPQE : TACPQE
bits : 21 - 21 (1 bit)
access : read-write
This register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx queue 0 and 1.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSRQ0 : PSRQ0
bits : 0 - 7 (8 bit)
access : read-write
PSRQ1 : PSRQ1
bits : 8 - 15 (8 bit)
access : read-write
The ARP Address register contains the IPv4 Destination Address of the MAC.
address_offset : 0xAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARPPA : ARPPA
bits : 0 - 31 (32 bit)
access : read-write
The Interrupt Status register contains the status of interrupts.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RGSMIIIS : RGSMIIIS
bits : 0 - 0 (1 bit)
access : read-only
PHYIS : PHYIS
bits : 3 - 3 (1 bit)
access : read-only
PMTIS : PMTIS
bits : 4 - 4 (1 bit)
access : read-only
LPIIS : LPIIS
bits : 5 - 5 (1 bit)
access : read-only
MMCIS : MMCIS
bits : 8 - 8 (1 bit)
access : read-only
MMCRXIS : MMCRXIS
bits : 9 - 9 (1 bit)
access : read-only
MMCTXIS : MMCTXIS
bits : 10 - 10 (1 bit)
access : read-only
TSIS : TSIS
bits : 12 - 12 (1 bit)
access : read-only
TXSTSIS : TXSTSIS
bits : 13 - 13 (1 bit)
access : read-only
RXSTSIS : RXSTSIS
bits : 14 - 14 (1 bit)
access : read-only
This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver.
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSENA : TSENA
bits : 0 - 0 (1 bit)
access : read-write
TSCFUPDT : TSCFUPDT
bits : 1 - 1 (1 bit)
access : read-write
TSINIT : TSINIT
bits : 2 - 2 (1 bit)
access : read-write
TSUPDT : TSUPDT
bits : 3 - 3 (1 bit)
access : read-write
TSADDREG : TSADDREG
bits : 5 - 5 (1 bit)
access : read-write
TSENALL : TSENALL
bits : 8 - 8 (1 bit)
access : read-write
TSCTRLSSR : TSCTRLSSR
bits : 9 - 9 (1 bit)
access : read-write
TSVER2ENA : TSVER2ENA
bits : 10 - 10 (1 bit)
access : read-write
TSIPENA : TSIPENA
bits : 11 - 11 (1 bit)
access : read-write
TSIPV6ENA : TSIPV6ENA
bits : 12 - 12 (1 bit)
access : read-write
TSIPV4ENA : TSIPV4ENA
bits : 13 - 13 (1 bit)
access : read-write
TSEVNTENA : TSEVNTENA
bits : 14 - 14 (1 bit)
access : read-write
TSMSTRENA : TSMSTRENA
bits : 15 - 15 (1 bit)
access : read-write
SNAPTYPSEL : SNAPTYPSEL
bits : 16 - 17 (2 bit)
access : read-write
TSENMACADDR : TSENMACADDR
bits : 18 - 18 (1 bit)
access : read-write
CSC : CSC
bits : 19 - 19 (1 bit)
access : read-only
TXTSSTSM : TXTSSTSM
bits : 24 - 24 (1 bit)
access : read-write
AV8021ASMEN : AV8021ASMEN
bits : 28 - 28 (1 bit)
access : read-write
The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNSINC : SNSINC
bits : 8 - 15 (8 bit)
access : read-write
SSINC : SSINC
bits : 16 - 23 (8 bit)
access : read-write
The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSS : TSS
bits : 0 - 31 (32 bit)
access : read-only
The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSSS : TSSS
bits : 0 - 30 (31 bit)
access : read-only
The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : TSS
bits : 0 - 31 (32 bit)
access : read-write
This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input.
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSS : TSSS
bits : 0 - 30 (31 bit)
access : read-write
ADDSUB : ADDSUB
bits : 31 - 31 (1 bit)
access : read-write
The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows.
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAR : TSAR
bits : 0 - 31 (32 bit)
access : read-write
The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register.
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSSOVF : TSSOVF
bits : 0 - 0 (1 bit)
access : read-only
TSTARGT0 : TSTARGT0
bits : 1 - 1 (1 bit)
access : read-only
AUXTSTRIG : AUXTSTRIG
bits : 2 - 2 (1 bit)
access : read-only
TSTRGTERR0 : TSTRGTERR0
bits : 3 - 3 (1 bit)
access : read-only
TXTSSIS : TXTSSIS
bits : 15 - 15 (1 bit)
access : read-only
ATSSTN : ATSSTN
bits : 16 - 19 (4 bit)
access : read-only
ATSSTM : ATSSTM
bits : 24 - 24 (1 bit)
access : read-only
ATSNS : ATSNS
bits : 25 - 29 (5 bit)
access : read-only
This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled.
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXTSSLO : TXTSSLO
bits : 0 - 30 (31 bit)
access : read-only
TXTSSMIS : TXTSSMIS
bits : 31 - 31 (1 bit)
access : read-only
The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted.
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXTSSHI : TXTSSHI
bits : 0 - 31 (32 bit)
access : read-only
The Interrupt Enable register contains the masks for generating the interrupts.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGSMIIIE : RGSMIIIE
bits : 0 - 0 (1 bit)
access : read-write
PHYIE : PHYIE
bits : 3 - 3 (1 bit)
access : read-write
PMTIE : PMTIE
bits : 4 - 4 (1 bit)
access : read-write
LPIIE : LPIIE
bits : 5 - 5 (1 bit)
access : read-write
TSIE : TSIE
bits : 12 - 12 (1 bit)
access : read-write
TXSTSIE : TXSTSIE
bits : 13 - 13 (1 bit)
access : read-write
RXSTSIE : RXSTSIE
bits : 14 - 14 (1 bit)
access : read-write
The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot.
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATSFC : ATSFC
bits : 0 - 0 (1 bit)
access : read-write
ATSEN0 : ATSEN0
bits : 4 - 4 (1 bit)
access : read-write
ATSEN1 : ATSEN1
bits : 5 - 5 (1 bit)
access : read-write
ATSEN2 : ATSEN2
bits : 6 - 6 (1 bit)
access : read-write
ATSEN3 : ATSEN3
bits : 7 - 7 (1 bit)
access : read-write
The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read.
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AUXTSLO : AUXTSLO
bits : 0 - 30 (31 bit)
access : read-only
The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register.
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AUXTSHI : AUXTSHI
bits : 0 - 31 (32 bit)
access : read-only
The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages.
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSTIAC : OSTIAC
bits : 0 - 31 (32 bit)
access : read-write
The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages.
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSTEAC : OSTEAC
bits : 0 - 31 (32 bit)
access : read-write
This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path.
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSIC : TSIC
bits : 0 - 31 (32 bit)
access : read-write
This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path.
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEC : TSEC
bits : 0 - 31 (32 bit)
access : read-write
The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected.
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSCTRL : PPSCTRL
bits : 0 - 3 (4 bit)
access : read-write
PPSEN0 : PPSEN0
bits : 4 - 4 (1 bit)
access : read-write
TRGTMODSEL0 : TRGTMODSEL0
bits : 5 - 6 (2 bit)
access : read-write
The Receive Transmit Status register contains the Receive and Transmit Error status.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TJT : TJT
bits : 0 - 0 (1 bit)
access : read-only
NCARR : NCARR
bits : 1 - 1 (1 bit)
access : read-only
LCARR : LCARR
bits : 2 - 2 (1 bit)
access : read-only
EXDEF : EXDEF
bits : 3 - 3 (1 bit)
access : read-only
LCOL : LCOL
bits : 4 - 4 (1 bit)
access : read-only
EXCOL : EXCOL
bits : 5 - 5 (1 bit)
access : read-only
RWT : RWT
bits : 8 - 8 (1 bit)
access : read-only
The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers.
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTRH0 : TSTRH0
bits : 0 - 31 (32 bit)
access : read-write
The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected.
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TTSL0 : TTSL0
bits : 0 - 30 (31 bit)
access : read-write
TRGTBUSY0 : TRGTBUSY0
bits : 31 - 31 (1 bit)
access : read-write
The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]).
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSINT0 : PPSINT0
bits : 0 - 31 (32 bit)
access : read-write
The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o).
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSWIDTH0 : PPSWIDTH0
bits : 0 - 31 (32 bit)
access : read-write
This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected.
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOEN : PTOEN
bits : 0 - 0 (1 bit)
access : read-write
ASYNCEN : ASYNCEN
bits : 1 - 1 (1 bit)
access : read-write
APDREQEN : APDREQEN
bits : 2 - 2 (1 bit)
access : read-write
ASYNCTRIG : ASYNCTRIG
bits : 4 - 4 (1 bit)
access : read-write
APDREQTRIG : APDREQTRIG
bits : 5 - 5 (1 bit)
access : read-write
DRRDIS : DRRDIS
bits : 6 - 6 (1 bit)
access : read-write
DN : DN
bits : 8 - 15 (8 bit)
access : read-write
This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.
address_offset : 0xBC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI0 : SPI0
bits : 0 - 31 (32 bit)
access : read-write
This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1 : SPI1
bits : 0 - 31 (32 bit)
access : read-write
This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node.
address_offset : 0xBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI2 : SPI2
bits : 0 - 15 (16 bit)
access : read-write
This register contains the periodic intervals for automatic PTP packet generation.
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSI : LSI
bits : 0 - 7 (8 bit)
access : read-write
DRSYNCR : DRSYNCR
bits : 8 - 10 (3 bit)
access : read-write
LMPDRI : LMPDRI
bits : 24 - 31 (8 bit)
access : read-write
The Watchdog Timeout register controls the watchdog timeout for received packets.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTO : WTO
bits : 0 - 3 (4 bit)
access : read-write
PWE : PWE
bits : 8 - 8 (1 bit)
access : read-write
The PMT Control and Status Register is present only when you select the PMT module in coreConsultant.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRDWN : PWRDWN
bits : 0 - 0 (1 bit)
access : read-write
MGKPKTEN : MGKPKTEN
bits : 1 - 1 (1 bit)
access : read-write
RWKPKTEN : RWKPKTEN
bits : 2 - 2 (1 bit)
access : read-write
MGKPRCVD : MGKPRCVD
bits : 5 - 5 (1 bit)
access : read-only
RWKPRCVD : RWKPRCVD
bits : 6 - 6 (1 bit)
access : read-only
GLBLUCAST : GLBLUCAST
bits : 9 - 9 (1 bit)
access : read-write
RWKPFE : RWKPFE
bits : 10 - 10 (1 bit)
access : read-write
RWKPTR : RWKPTR
bits : 24 - 28 (5 bit)
access : read-only
RWKFILTRST : RWKFILTRST
bits : 31 - 31 (1 bit)
access : read-write
The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLPIEN : TLPIEN
bits : 0 - 0 (1 bit)
access : read-only
TLPIEX : TLPIEX
bits : 1 - 1 (1 bit)
access : read-only
RLPIEN : RLPIEN
bits : 2 - 2 (1 bit)
access : read-only
RLPIEX : RLPIEX
bits : 3 - 3 (1 bit)
access : read-only
TLPIST : TLPIST
bits : 8 - 8 (1 bit)
access : read-only
RLPIST : RLPIST
bits : 9 - 9 (1 bit)
access : read-only
LPIEN : LPIEN
bits : 16 - 16 (1 bit)
access : read-write
PLS : PLS
bits : 17 - 17 (1 bit)
access : read-write
PLSEN : PLSEN
bits : 18 - 18 (1 bit)
access : read-write
LPITXA : LPITXA
bits : 19 - 19 (1 bit)
access : read-write
LPITE : LPITE
bits : 20 - 20 (1 bit)
access : read-write
The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLPIEN : TLPIEN
bits : 0 - 0 (1 bit)
access : read-only
TLPIEX : TLPIEX
bits : 1 - 1 (1 bit)
access : read-only
RLPIEN : RLPIEN
bits : 2 - 2 (1 bit)
access : read-only
RLPIEX : RLPIEX
bits : 3 - 3 (1 bit)
access : read-only
TLPIST : TLPIST
bits : 8 - 8 (1 bit)
access : read-only
RLPIST : RLPIST
bits : 9 - 9 (1 bit)
access : read-only
LPIEN : LPIEN
bits : 16 - 16 (1 bit)
access : read-write
PLS : PLS
bits : 17 - 17 (1 bit)
access : read-write
PLSEN : PLSEN
bits : 18 - 18 (1 bit)
access : read-write
LPITXA : LPITXA
bits : 19 - 19 (1 bit)
access : read-write
LPITE : LPITE
bits : 20 - 20 (1 bit)
access : read-write
The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWT : TWT
bits : 0 - 15 (16 bit)
access : read-write
LST : LST
bits : 16 - 25 (10 bit)
access : read-write
The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIET : LPIET
bits : 3 - 19 (17 bit)
access : read-write
This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIC_1US_CNTR : TIC_1US_CNTR
bits : 0 - 11 (12 bit)
access : read-write
The PHY Interface Control and Status register indicates the status signals received by the, RGMII interface from the PHY.
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : TC
bits : 0 - 0 (1 bit)
access : read-write
LUD : LUD
bits : 1 - 1 (1 bit)
access : read-write
LNKMOD : LNKMOD
bits : 16 - 16 (1 bit)
access : read-only
LNKSPEED : LNKSPEED
bits : 17 - 18 (2 bit)
access : read-only
LNKSTS : LNKSTS
bits : 19 - 19 (1 bit)
access : read-only
JABTO : JABTO
bits : 20 - 20 (1 bit)
access : read-only
FALSCARDET : FALSCARDET
bits : 21 - 21 (1 bit)
access : read-only
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