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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
The Operating Mode register establishes the Transmit and Receive operating modes and commands.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTXSTS : DTXSTS
bits : 1 - 1 (1 bit)
access : read-write
RAA : RAA
bits : 2 - 2 (1 bit)
access : read-write
SCHALG : SCHALG
bits : 5 - 6 (2 bit)
access : read-write
CNTPRST : CNTPRST
bits : 8 - 8 (1 bit)
access : read-write
CNTCLR : CNTCLR
bits : 9 - 9 (1 bit)
access : read-write
Tx queue 0 operating mode Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTQ : FTQ
bits : 0 - 0 (1 bit)
access : read-write
TSF : TSF
bits : 1 - 1 (1 bit)
access : read-write
TXQEN : TXQEN
bits : 2 - 3 (2 bit)
access : read-write
TTC : TTC
bits : 4 - 5 (2 bit)
access : read-write
TQS : TQS
bits : 16 - 24 (9 bit)
access : read-write
Tx queue 0 underflow register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UFFRMCNT : UFFRMCNT
bits : 0 - 10 (11 bit)
access : read-only
UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only
Tx queue 0 underflow register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)
access : read-only
TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)
access : read-only
TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)
access : read-only
TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)
access : read-only
TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)
access : read-only
PTXQ : PTXQ
bits : 16 - 18 (3 bit)
access : read-only
STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)
access : read-only
Tx queue x ETS status Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ABS : ABS
bits : 0 - 23 (24 bit)
access : read-only
Queue 0 interrupt control status Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)
access : read-only
ABPSIS : ABPSIS
bits : 1 - 1 (1 bit)
access : read-write
TXUIE : TXUIE
bits : 8 - 8 (1 bit)
access : read-write
ABPSIE : ABPSIE
bits : 9 - 9 (1 bit)
access : read-write
RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)
access : read-write
RXOIE : RXOIE
bits : 24 - 24 (1 bit)
access : read-write
Rx queue 0 operating mode register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write
FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write
FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write
RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write
DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write
EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write
RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write
RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write
RQS : RQS
bits : 20 - 23 (4 bit)
access : read-only
Rx queue 0 missed packet and overflow counter register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)
access : read-only
OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only
MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)
access : read-only
MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)
access : read-only
Rx queue i debug register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)
access : read-only
RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)
access : read-only
RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)
access : read-only
PRXQ : PRXQ
bits : 16 - 29 (14 bit)
access : read-only
Rx queue 0 control register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXQ_WEGT : RXQ_WEGT
bits : 0 - 2 (3 bit)
access : read-only
RXQ_FRM_ARBIT : RXQ_FRM_ARBIT
bits : 3 - 3 (1 bit)
access : read-only
Tx queue 1 operating mode Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTQ : FTQ
bits : 0 - 0 (1 bit)
access : read-write
TSF : TSF
bits : 1 - 1 (1 bit)
access : read-write
TXQEN : TXQEN
bits : 2 - 3 (2 bit)
access : read-write
TTC : TTC
bits : 4 - 5 (2 bit)
access : read-write
TQS : TQS
bits : 16 - 24 (9 bit)
access : read-write
Tx queue 1 underflow register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UFFRMCNT : UFFRMCNT
bits : 0 - 10 (11 bit)
access : read-only
UFCNTOVF : UFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only
Tx queue 1 underflow register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXQPAUSED : TXQPAUSED
bits : 0 - 0 (1 bit)
access : read-only
TRCSTS : TRCSTS
bits : 1 - 2 (2 bit)
access : read-only
TWCSTS : TWCSTS
bits : 3 - 3 (1 bit)
access : read-only
TXQSTS : TXQSTS
bits : 4 - 4 (1 bit)
access : read-only
TXSTSFSTS : TXSTSFSTS
bits : 5 - 5 (1 bit)
access : read-only
PTXQ : PTXQ
bits : 16 - 18 (3 bit)
access : read-only
STXSTSF : STXSTSF
bits : 20 - 22 (3 bit)
access : read-only
The Queue ETS Control register controls the enhanced transmission selection operation.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AVALG : AVALG
bits : 2 - 2 (1 bit)
access : read-write
CC : CC
bits : 3 - 3 (1 bit)
access : read-write
SLC : SLC
bits : 4 - 6 (3 bit)
access : read-write
Tx queue x ETS status Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ABS : ABS
bits : 0 - 23 (24 bit)
access : read-only
This register provides the average traffic transmitted on queue 1.
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISCQW : ISCQW
bits : 0 - 20 (21 bit)
access : read-write
The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSC : SSC
bits : 0 - 13 (14 bit)
access : read-write
The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue.
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HC : HC
bits : 0 - 28 (29 bit)
access : read-write
The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue.
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LC : LC
bits : 0 - 28 (29 bit)
access : read-write
Queue 1 interrupt control status Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUNFIS : TXUNFIS
bits : 0 - 0 (1 bit)
access : read-only
ABPSIS : ABPSIS
bits : 1 - 1 (1 bit)
access : read-write
TXUIE : TXUIE
bits : 8 - 8 (1 bit)
access : read-write
ABPSIE : ABPSIE
bits : 9 - 9 (1 bit)
access : read-write
RXOVFIS : RXOVFIS
bits : 16 - 16 (1 bit)
access : read-write
RXOIE : RXOIE
bits : 24 - 24 (1 bit)
access : read-write
Rx queue 1 operating mode register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : RTC
bits : 0 - 1 (2 bit)
access : read-write
FUP : FUP
bits : 3 - 3 (1 bit)
access : read-write
FEP : FEP
bits : 4 - 4 (1 bit)
access : read-write
RSF : RSF
bits : 5 - 5 (1 bit)
access : read-write
DIS_TCP_EF : DIS_TCP_EF
bits : 6 - 6 (1 bit)
access : read-write
EHFC : EHFC
bits : 7 - 7 (1 bit)
access : read-write
RFA : RFA
bits : 8 - 10 (3 bit)
access : read-write
RFD : RFD
bits : 14 - 16 (3 bit)
access : read-write
RQS : RQS
bits : 20 - 23 (4 bit)
access : read-only
Rx queue 1 missed packet and overflow counter register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVFPKTCNT : OVFPKTCNT
bits : 0 - 10 (11 bit)
access : read-only
OVFCNTOVF : OVFCNTOVF
bits : 11 - 11 (1 bit)
access : read-only
MISPKTCNT : MISPKTCNT
bits : 16 - 26 (11 bit)
access : read-only
MISCNTOVF : MISCNTOVF
bits : 27 - 27 (1 bit)
access : read-only
Rx queue i debug register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RWCSTS : RWCSTS
bits : 0 - 0 (1 bit)
access : read-only
RRCSTS : RRCSTS
bits : 1 - 2 (2 bit)
access : read-only
RXQSTS : RXQSTS
bits : 4 - 5 (2 bit)
access : read-only
PRXQ : PRXQ
bits : 16 - 29 (14 bit)
access : read-only
Rx queue 1 control register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXQ_WEGT : RXQ_WEGT
bits : 0 - 2 (3 bit)
access : read-only
RXQ_FRM_ARBIT : RXQ_FRM_ARBIT
bits : 3 - 3 (1 bit)
access : read-only
The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Q0IS : Q0IS
bits : 0 - 0 (1 bit)
access : read-only
Q1IS : Q1IS
bits : 1 - 1 (1 bit)
access : read-only
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