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TIM13

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TIM13_CR1 (CR1)

TIM13_SR (SR)

TIM13_EGR (EGR)

TIM13_CCMR1 (CCMR1)

TIM13_CCER (CCER)

TIM13_CNT (CNT)

TIM13_PSC (PSC)

TIM13_ARR (ARR)

TIM13_CCR1 (CCR1)

TIM13_TISEL (TISEL)

TIM13_DIER (DIER)


TIM13_CR1 (CR1)

TIM13 control register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_CR1 TIM13_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM ARPE CKD UIFREMAP

CEN : CEN
bits : 0 - 0 (1 bit)

UDIS : UDIS
bits : 1 - 1 (1 bit)

URS : URS
bits : 2 - 2 (1 bit)

OPM : OPM
bits : 3 - 3 (1 bit)

ARPE : ARPE
bits : 7 - 7 (1 bit)

CKD : CKD
bits : 8 - 9 (2 bit)

UIFREMAP : UIFREMAP
bits : 11 - 11 (1 bit)


TIM13_SR (SR)

TIM13 status register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_SR TIM13_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC1OF

UIF : UIF
bits : 0 - 0 (1 bit)

CC1IF : CC1IF
bits : 1 - 1 (1 bit)

CC1OF : CC1OF
bits : 9 - 9 (1 bit)


TIM13_EGR (EGR)

TIM13 event generation register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TIM13_EGR TIM13_EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G

UG : UG
bits : 0 - 0 (1 bit)

CC1G : CC1G
bits : 1 - 1 (1 bit)


TIM13_CCMR1 (CCMR1)

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_CCMR1 TIM13_CCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M OC1M3

CC1S : CC1S
bits : 0 - 1 (2 bit)

OC1FE : OC1FE
bits : 2 - 2 (1 bit)

OC1PE : OC1PE
bits : 3 - 3 (1 bit)

OC1M : OC1M
bits : 4 - 6 (3 bit)

OC1M3 : OC1M3
bits : 16 - 16 (1 bit)


TIM13_CCER (CCER)

TIM13 capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_CCER TIM13_CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NP

CC1E : CC1E
bits : 0 - 0 (1 bit)

CC1P : CC1P
bits : 1 - 1 (1 bit)

CC1NP : CC1NP
bits : 3 - 3 (1 bit)


TIM13_CNT (CNT)

TIM13 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_CNT TIM13_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT UIFCPY

CNT : CNT
bits : 0 - 15 (16 bit)

UIFCPY : UIFCPY
bits : 31 - 31 (1 bit)


TIM13_PSC (PSC)

TIM13 prescaler
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_PSC TIM13_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 15 (16 bit)


TIM13_ARR (ARR)

TIM13 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_ARR TIM13_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)


TIM13_CCR1 (CCR1)

TIM13 capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_CCR1 TIM13_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : CCR1
bits : 0 - 15 (16 bit)


TIM13_TISEL (TISEL)

TIM13 timer input selection register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_TISEL TIM13_TISEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI1SEL

TI1SEL : TI1SEL
bits : 0 - 3 (4 bit)


TIM13_DIER (DIER)

TIM13 Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM13_DIER TIM13_DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE

UIE : UIE
bits : 0 - 0 (1 bit)

CC1IE : CC1IE
bits : 1 - 1 (1 bit)



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