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I2C2_IPXACT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

I2C_CR1

I2C_TIMINGR

I2C_TIMEOUTR

I2C_ISR

I2C_ICR

I2C_PECR

I2C_RXDR

I2C_TXDR

I2C_HWCFGR

I2C_VERR

I2C_IPIDR

I2C_SIDR

I2C_CR2

I2C_OAR1

I2C_OAR2


I2C_CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CR1 I2C_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE TXIE RXIE ADDRIE NACKIE STOPIE TCIE ERRIE DNF ANFOFF TXDMAEN RXDMAEN SBC NOSTRETCH WUPEN GCEN SMBHEN SMBDEN ALERTEN PECEN

PE : PE
bits : 0 - 0 (1 bit)

TXIE : TXIE
bits : 1 - 1 (1 bit)

RXIE : RXIE
bits : 2 - 2 (1 bit)

ADDRIE : ADDRIE
bits : 3 - 3 (1 bit)

NACKIE : NACKIE
bits : 4 - 4 (1 bit)

STOPIE : STOPIE
bits : 5 - 5 (1 bit)

TCIE : TCIE
bits : 6 - 6 (1 bit)

ERRIE : ERRIE
bits : 7 - 7 (1 bit)

DNF : DNF
bits : 8 - 11 (4 bit)

ANFOFF : ANFOFF
bits : 12 - 12 (1 bit)

TXDMAEN : TXDMAEN
bits : 14 - 14 (1 bit)

RXDMAEN : RXDMAEN
bits : 15 - 15 (1 bit)

SBC : SBC
bits : 16 - 16 (1 bit)

NOSTRETCH : NOSTRETCH
bits : 17 - 17 (1 bit)

WUPEN : WUPEN
bits : 18 - 18 (1 bit)

GCEN : GCEN
bits : 19 - 19 (1 bit)

SMBHEN : SMBHEN
bits : 20 - 20 (1 bit)

SMBDEN : SMBDEN
bits : 21 - 21 (1 bit)

ALERTEN : ALERTEN
bits : 22 - 22 (1 bit)

PECEN : PECEN
bits : 23 - 23 (1 bit)


I2C_TIMINGR

Access: No wait states
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TIMINGR I2C_TIMINGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLL SCLH SDADEL SCLDEL PRESC

SCLL : SCLL
bits : 0 - 7 (8 bit)

SCLH : SCLH
bits : 8 - 15 (8 bit)

SDADEL : SDADEL
bits : 16 - 19 (4 bit)

SCLDEL : SCLDEL
bits : 20 - 23 (4 bit)

PRESC : PRESC
bits : 28 - 31 (4 bit)


I2C_TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TIMEOUTR I2C_TIMEOUTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUTA TIDLE TIMOUTEN TIMEOUTB TEXTEN

TIMEOUTA : TIMEOUTA
bits : 0 - 11 (12 bit)

TIDLE : TIDLE
bits : 12 - 12 (1 bit)

TIMOUTEN : TIMOUTEN
bits : 15 - 15 (1 bit)

TIMEOUTB : TIMEOUTB
bits : 16 - 27 (12 bit)

TEXTEN : TEXTEN
bits : 31 - 31 (1 bit)


I2C_ISR

Access: No wait states
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_ISR I2C_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXE TXIS RXNE ADDR NACKF STOPF TC TCR BERR ARLO OVR PECERR TIMEOUT ALERT BUSY DIR ADDCODE

TXE : TXE
bits : 0 - 0 (1 bit)
access : read-write

TXIS : TXIS
bits : 1 - 1 (1 bit)
access : read-write

RXNE : RXNE
bits : 2 - 2 (1 bit)
access : read-only

ADDR : ADDR
bits : 3 - 3 (1 bit)
access : read-only

NACKF : NACKF
bits : 4 - 4 (1 bit)
access : read-only

STOPF : STOPF
bits : 5 - 5 (1 bit)
access : read-only

TC : TC
bits : 6 - 6 (1 bit)
access : read-only

TCR : TCR
bits : 7 - 7 (1 bit)
access : read-only

BERR : BERR
bits : 8 - 8 (1 bit)
access : read-only

ARLO : ARLO
bits : 9 - 9 (1 bit)
access : read-only

OVR : OVR
bits : 10 - 10 (1 bit)
access : read-only

PECERR : PECERR
bits : 11 - 11 (1 bit)
access : read-only

TIMEOUT : TIMEOUT
bits : 12 - 12 (1 bit)
access : read-only

ALERT : ALERT
bits : 13 - 13 (1 bit)
access : read-only

BUSY : BUSY
bits : 15 - 15 (1 bit)
access : read-only

DIR : DIR
bits : 16 - 16 (1 bit)
access : read-only

ADDCODE : ADDCODE
bits : 17 - 23 (7 bit)
access : read-only


I2C_ICR

Access: No wait states
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2C_ICR I2C_ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRCF NACKCF STOPCF BERRCF ARLOCF OVRCF PECCF TIMOUTCF ALERTCF

ADDRCF : ADDRCF
bits : 3 - 3 (1 bit)

NACKCF : NACKCF
bits : 4 - 4 (1 bit)

STOPCF : STOPCF
bits : 5 - 5 (1 bit)

BERRCF : BERRCF
bits : 8 - 8 (1 bit)

ARLOCF : ARLOCF
bits : 9 - 9 (1 bit)

OVRCF : OVRCF
bits : 10 - 10 (1 bit)

PECCF : PECCF
bits : 11 - 11 (1 bit)

TIMOUTCF : TIMOUTCF
bits : 12 - 12 (1 bit)

ALERTCF : ALERTCF
bits : 13 - 13 (1 bit)


I2C_PECR

Access: No wait states
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2C_PECR I2C_PECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEC

PEC : PEC
bits : 0 - 7 (8 bit)


I2C_RXDR

Access: No wait states
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2C_RXDR I2C_RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RXDATA
bits : 0 - 7 (8 bit)


I2C_TXDR

Access: No wait states
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TXDR I2C_TXDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TXDATA
bits : 0 - 7 (8 bit)


I2C_HWCFGR

I2C hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2C_HWCFGR I2C_HWCFGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMBUS ASYN WKP

SMBUS : SMBUS
bits : 0 - 3 (4 bit)

ASYN : ASYN
bits : 4 - 7 (4 bit)

WKP : WKP
bits : 8 - 11 (4 bit)


I2C_VERR

I2C version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2C_VERR I2C_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : MINREV
bits : 0 - 3 (4 bit)

MAJREV : MAJREV
bits : 4 - 7 (4 bit)


I2C_IPIDR

I2C identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2C_IPIDR I2C_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : ID
bits : 0 - 31 (32 bit)


I2C_SIDR

I2C size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2C_SIDR I2C_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : SID
bits : 0 - 31 (32 bit)


I2C_CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CR2 I2C_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADD RD_WRN ADD10 HEAD10R START STOP NACK NBYTES RELOAD AUTOEND PECBYTE

SADD : SADD
bits : 0 - 9 (10 bit)

RD_WRN : RD_WRN
bits : 10 - 10 (1 bit)

ADD10 : ADD10
bits : 11 - 11 (1 bit)

HEAD10R : HEAD10R
bits : 12 - 12 (1 bit)

START : START
bits : 13 - 13 (1 bit)

STOP : STOP
bits : 14 - 14 (1 bit)

NACK : NACK
bits : 15 - 15 (1 bit)

NBYTES : NBYTES
bits : 16 - 23 (8 bit)

RELOAD : RELOAD
bits : 24 - 24 (1 bit)

AUTOEND : AUTOEND
bits : 25 - 25 (1 bit)

PECBYTE : PECBYTE
bits : 26 - 26 (1 bit)


I2C_OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_OAR1 I2C_OAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA1 OA1MODE OA1EN

OA1 : OA1
bits : 0 - 9 (10 bit)

OA1MODE : OA1MODE
bits : 10 - 10 (1 bit)

OA1EN : OA1EN
bits : 15 - 15 (1 bit)


I2C_OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_OAR2 I2C_OAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OA2 OA2MSK OA2EN

OA2 : OA2
bits : 1 - 7 (7 bit)

OA2MSK : OA2MSK
bits : 8 - 10 (3 bit)

OA2EN : OA2EN
bits : 15 - 15 (1 bit)



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