\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : PE
bits : 0 - 0 (1 bit)
TXIE : TXIE
bits : 1 - 1 (1 bit)
RXIE : RXIE
bits : 2 - 2 (1 bit)
ADDRIE : ADDRIE
bits : 3 - 3 (1 bit)
NACKIE : NACKIE
bits : 4 - 4 (1 bit)
STOPIE : STOPIE
bits : 5 - 5 (1 bit)
TCIE : TCIE
bits : 6 - 6 (1 bit)
ERRIE : ERRIE
bits : 7 - 7 (1 bit)
DNF : DNF
bits : 8 - 11 (4 bit)
ANFOFF : ANFOFF
bits : 12 - 12 (1 bit)
TXDMAEN : TXDMAEN
bits : 14 - 14 (1 bit)
RXDMAEN : RXDMAEN
bits : 15 - 15 (1 bit)
SBC : SBC
bits : 16 - 16 (1 bit)
NOSTRETCH : NOSTRETCH
bits : 17 - 17 (1 bit)
WUPEN : WUPEN
bits : 18 - 18 (1 bit)
GCEN : GCEN
bits : 19 - 19 (1 bit)
SMBHEN : SMBHEN
bits : 20 - 20 (1 bit)
SMBDEN : SMBDEN
bits : 21 - 21 (1 bit)
ALERTEN : ALERTEN
bits : 22 - 22 (1 bit)
PECEN : PECEN
bits : 23 - 23 (1 bit)
Access: No wait states
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLL : SCLL
bits : 0 - 7 (8 bit)
SCLH : SCLH
bits : 8 - 15 (8 bit)
SDADEL : SDADEL
bits : 16 - 19 (4 bit)
SCLDEL : SCLDEL
bits : 20 - 23 (4 bit)
PRESC : PRESC
bits : 28 - 31 (4 bit)
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUTA : TIMEOUTA
bits : 0 - 11 (12 bit)
TIDLE : TIDLE
bits : 12 - 12 (1 bit)
TIMOUTEN : TIMOUTEN
bits : 15 - 15 (1 bit)
TIMEOUTB : TIMEOUTB
bits : 16 - 27 (12 bit)
TEXTEN : TEXTEN
bits : 31 - 31 (1 bit)
Access: No wait states
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXE : TXE
bits : 0 - 0 (1 bit)
access : read-write
TXIS : TXIS
bits : 1 - 1 (1 bit)
access : read-write
RXNE : RXNE
bits : 2 - 2 (1 bit)
access : read-only
ADDR : ADDR
bits : 3 - 3 (1 bit)
access : read-only
NACKF : NACKF
bits : 4 - 4 (1 bit)
access : read-only
STOPF : STOPF
bits : 5 - 5 (1 bit)
access : read-only
TC : TC
bits : 6 - 6 (1 bit)
access : read-only
TCR : TCR
bits : 7 - 7 (1 bit)
access : read-only
BERR : BERR
bits : 8 - 8 (1 bit)
access : read-only
ARLO : ARLO
bits : 9 - 9 (1 bit)
access : read-only
OVR : OVR
bits : 10 - 10 (1 bit)
access : read-only
PECERR : PECERR
bits : 11 - 11 (1 bit)
access : read-only
TIMEOUT : TIMEOUT
bits : 12 - 12 (1 bit)
access : read-only
ALERT : ALERT
bits : 13 - 13 (1 bit)
access : read-only
BUSY : BUSY
bits : 15 - 15 (1 bit)
access : read-only
DIR : DIR
bits : 16 - 16 (1 bit)
access : read-only
ADDCODE : ADDCODE
bits : 17 - 23 (7 bit)
access : read-only
Access: No wait states
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDRCF : ADDRCF
bits : 3 - 3 (1 bit)
NACKCF : NACKCF
bits : 4 - 4 (1 bit)
STOPCF : STOPCF
bits : 5 - 5 (1 bit)
BERRCF : BERRCF
bits : 8 - 8 (1 bit)
ARLOCF : ARLOCF
bits : 9 - 9 (1 bit)
OVRCF : OVRCF
bits : 10 - 10 (1 bit)
PECCF : PECCF
bits : 11 - 11 (1 bit)
TIMOUTCF : TIMOUTCF
bits : 12 - 12 (1 bit)
ALERTCF : ALERTCF
bits : 13 - 13 (1 bit)
Access: No wait states
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PEC : PEC
bits : 0 - 7 (8 bit)
Access: No wait states
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RXDATA
bits : 0 - 7 (8 bit)
Access: No wait states
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TXDATA
bits : 0 - 7 (8 bit)
I2C hardware configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SMBUS : SMBUS
bits : 0 - 3 (4 bit)
ASYN : ASYN
bits : 4 - 7 (4 bit)
WKP : WKP
bits : 8 - 11 (4 bit)
I2C version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINREV : MINREV
bits : 0 - 3 (4 bit)
MAJREV : MAJREV
bits : 4 - 7 (4 bit)
I2C identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : ID
bits : 0 - 31 (32 bit)
I2C size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SID : SID
bits : 0 - 31 (32 bit)
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADD : SADD
bits : 0 - 9 (10 bit)
RD_WRN : RD_WRN
bits : 10 - 10 (1 bit)
ADD10 : ADD10
bits : 11 - 11 (1 bit)
HEAD10R : HEAD10R
bits : 12 - 12 (1 bit)
START : START
bits : 13 - 13 (1 bit)
STOP : STOP
bits : 14 - 14 (1 bit)
NACK : NACK
bits : 15 - 15 (1 bit)
NBYTES : NBYTES
bits : 16 - 23 (8 bit)
RELOAD : RELOAD
bits : 24 - 24 (1 bit)
AUTOEND : AUTOEND
bits : 25 - 25 (1 bit)
PECBYTE : PECBYTE
bits : 26 - 26 (1 bit)
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1 : OA1
bits : 0 - 9 (10 bit)
OA1MODE : OA1MODE
bits : 10 - 10 (1 bit)
OA1EN : OA1EN
bits : 15 - 15 (1 bit)
Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA2 : OA2
bits : 1 - 7 (7 bit)
OA2MSK : OA2MSK
bits : 8 - 10 (3 bit)
OA2EN : OA2EN
bits : 15 - 15 (1 bit)
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