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STGENC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

STGENC_CNTCR (CNTCR)

STGENC_CNTFID0 (CNTFID0)

STGENC_CNTSR (CNTSR)

STGENC_CNTCVL (CNTCVL)

STGENC_CNTCVU (CNTCVU)

STGENC_PIDR4 (PIDR4)

STGENC_PIDR5 (PIDR5)

STGENC_PIDR6 (PIDR6)

STGENC_PIDR7 (PIDR7)

STGENC_PIDR0 (PIDR0)

STGENC_PIDR1 (PIDR1)

STGENC_PIDR2 (PIDR2)

STGENC_PIDR3 (PIDR3)

STGENC_CIDR0 (CIDR0)

STGENC_CIDR1 (CIDR1)

STGENC_CIDR2 (CIDR2)

STGENC_CIDR3 (CIDR3)


STGENC_CNTCR (CNTCR)

STGENC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STGENC_CNTCR STGENC_CNTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HLTDBG

EN : EN
bits : 0 - 0 (1 bit)

HLTDBG : HLTDBG
bits : 1 - 1 (1 bit)


STGENC_CNTFID0 (CNTFID0)

the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STGENC_CNTFID0 STGENC_CNTFID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ

FREQ : FREQ
bits : 0 - 31 (32 bit)


STGENC_CNTSR (CNTSR)

STGENC status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_CNTSR STGENC_CNTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HLTDBG

EN : EN
bits : 0 - 0 (1 bit)

HLTDBG : HLTDBG
bits : 1 - 1 (1 bit)


STGENC_CNTCVL (CNTCVL)

the control interface must clear the STGENC_CNTCR.EN bit before writing to this register.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STGENC_CNTCVL STGENC_CNTCVL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTCVL_L_32

CNTCVL_L_32 : CNTCVL_L_32
bits : 0 - 31 (32 bit)


STGENC_CNTCVU (CNTCVU)

the control interface must clear the STGENC_CNTCR.EN bit before writing to this register.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STGENC_CNTCVU STGENC_CNTCVU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTCVU_U_32

CNTCVU_U_32 : CNTCVU_U_32
bits : 0 - 31 (32 bit)


STGENC_PIDR4 (PIDR4)

STGENC peripheral ID4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR4 STGENC_PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DES_2 SIZE

DES_2 : DES_2
bits : 0 - 3 (4 bit)

SIZE : SIZE
bits : 4 - 7 (4 bit)


STGENC_PIDR5 (PIDR5)

STGENC peripheral ID5 register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR5 STGENC_PIDR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR5

PIDR5 : PIDR5
bits : 0 - 31 (32 bit)


STGENC_PIDR6 (PIDR6)

STGENC peripheral ID6 register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR6 STGENC_PIDR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR6

PIDR6 : PIDR6
bits : 0 - 31 (32 bit)


STGENC_PIDR7 (PIDR7)

STGENC peripheral ID7 register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR7 STGENC_PIDR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIDR7

PIDR7 : PIDR7
bits : 0 - 31 (32 bit)


STGENC_PIDR0 (PIDR0)

STGENC peripheral ID0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR0 STGENC_PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_0

PART_0 : PART_0
bits : 0 - 7 (8 bit)


STGENC_PIDR1 (PIDR1)

STGENC peripheral ID1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR1 STGENC_PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_1 DES_0

PART_1 : PART_1
bits : 0 - 3 (4 bit)

DES_0 : DES_0
bits : 4 - 7 (4 bit)


STGENC_PIDR2 (PIDR2)

STGENC peripheral ID2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR2 STGENC_PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DES_1 JEDEC REVISION

DES_1 : DES_1
bits : 0 - 2 (3 bit)

JEDEC : JEDEC
bits : 3 - 3 (1 bit)

REVISION : REVISION
bits : 4 - 7 (4 bit)


STGENC_PIDR3 (PIDR3)

STGENC peripheral ID3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_PIDR3 STGENC_PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMOD REVAND

CMOD : CMOD
bits : 0 - 3 (4 bit)

REVAND : REVAND
bits : 4 - 7 (4 bit)


STGENC_CIDR0 (CIDR0)

STGENC component ID0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_CIDR0 STGENC_CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_0

PRMBL_0 : PRMBL_0
bits : 0 - 7 (8 bit)


STGENC_CIDR1 (CIDR1)

STGENC component ID1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_CIDR1 STGENC_CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_1 CLASS

PRMBL_1 : PRMBL_1
bits : 0 - 3 (4 bit)

CLASS : CLASS
bits : 4 - 7 (4 bit)


STGENC_CIDR2 (CIDR2)

STGENC component ID2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_CIDR2 STGENC_CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_2

PRMBL_2 : PRMBL_2
bits : 0 - 7 (8 bit)


STGENC_CIDR3 (CIDR3)

STGENC component ID3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STGENC_CIDR3 STGENC_CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_3

PRMBL_3 : PRMBL_3
bits : 0 - 7 (8 bit)



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