\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNTCVL_L_32 : CNTCVL_L_32
bits : 0 - 31 (32 bit)
the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNTCVU_U_32 : CNTCVU_U_32
bits : 0 - 31 (32 bit)
STGENR peripheral ID4 register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DES_2 : DES_2
bits : 0 - 3 (4 bit)
SIZE : SIZE
bits : 4 - 7 (4 bit)
STGENR peripheral ID5 register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR5 : PIDR5
bits : 0 - 31 (32 bit)
STGENR peripheral ID6 register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR6 : PIDR6
bits : 0 - 31 (32 bit)
STGENR peripheral ID7 register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDR7 : PIDR7
bits : 0 - 31 (32 bit)
STGENR peripheral ID0 register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_0 : PART_0
bits : 0 - 7 (8 bit)
STGENR peripheral ID1 register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_1 : PART_1
bits : 0 - 3 (4 bit)
DES_0 : DES_0
bits : 4 - 7 (4 bit)
STGENR peripheral ID2 register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DES_1 : DES_1
bits : 0 - 2 (3 bit)
JEDEC : JEDEC
bits : 3 - 3 (1 bit)
REVISION : REVISION
bits : 4 - 7 (4 bit)
STGENR peripheral ID3 register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMOD : CMOD
bits : 0 - 3 (4 bit)
REVAND : REVAND
bits : 4 - 7 (4 bit)
STGENR component ID0 register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : PRMBL_0
bits : 0 - 7 (8 bit)
STGENR component ID1 register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : PRMBL_1
bits : 0 - 3 (4 bit)
CLASS : CLASS
bits : 4 - 7 (4 bit)
STGENR component ID2 register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : PRMBL_2
bits : 0 - 7 (8 bit)
STGENR component ID3 register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : PRMBL_3
bits : 0 - 7 (8 bit)
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